JP2003022222A - Information processor and its maintenance method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of specifying a device, in which error is detected on a PCI bus, and improving maintenability accompanying error processing. SOLUTION: In this information processor having a plurality of devices interconnected through buses 60 and 70, the device is provided with a detecting means 230 for detecting an error at the time of executing the transaction of the bus and recoding means 170 and 200 for recording the kind of the error and the information of the device which detect the error as an error event in a recording medium 240 according to the detected result of the detecting means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an error logging process in which an error logging function when an error occurs in the information processing apparatus is strengthened and maintainability is improved.

[0002]

2. Description of the Related Art Recent PC servers and workstations have a PCI (Periphera) having a 32-bit data bus width as a system bus on a motherboard.
l Component Interconnect)
It is equipped with a high-speed synchronous bus called. A device on the PCI bus or a device on the PCI bus connected to an expansion slot on the motherboard is defined to handle events that occur on the PCI bus. PC
In order to detect whether an error has occurred in the information transmitted using the address / data signal or control signal on the I bus, P
A parity line is prepared on the CI bus. Especially PC
When the I-device detects an address parity error or a data parity error on the PCI bus,
It is defined to issue an R (Parity Error) signal on the PCI bus. When the PCI device detects a fatal system error on the PCI bus, the PCI device sends a SERR (System Error) signal to the PC.
Output on I bus. PERR signal or SE on PCI
When the RR signal is detected, the device that manages the PCI bus generates a non-maskable interrupt signal (hereinafter referred to as NMI) to the CPU, and only the fact that an error occurs in the nonvolatile memory called SEL. I remembered. That is, when the PERR signal is detected on the PCI bus, only the data indicating the generation of the PERR signal is stored in the non-volatile memory. Similarly, S on the PCI bus
When the ERR signal is detected, the SER is stored in the nonvolatile memory.
Only the data indicating the generation of the R signal was stored. The maintenance staff later read the value stored in the nonvolatile memory and analyzed in detail what error occurred and how.

Further, Japanese Laid-Open Patent Publication No. 11-16420 discloses a technique for performing a non-recoverable error logging process for a memory parity error or a system bus. In this conventional technique, when an error is detected, the CP
The U is notified of a system management interrupt (hereinafter referred to as SMI) signal. The error processing routine started by the SMI signal reads the data from the latch circuit that holds the address value of the CPU when the error occurs, and stores the error occurrence address in the nonvolatile memory. The maintenance staff later read the value stored in the nonvolatile memory and analyzed in detail what error occurred and how.

However, in the prior art, when an error occurs on the PCI bus, only the fact of the error occurrence is stored in the non-volatile memory. In addition, JP-A-11-16420
In the error logging process of the publication, the address value of the CPU is stored in the non-volatile memory. Therefore, it is difficult for the maintenance personnel to specify which device has generated the error and has detected the error. If the location of the error could not be identified, it was necessary to replace the entire motherboard or the entire expansion board installed in the expansion slot.

[0005]

In the above-mentioned prior art, since only the fact that an error occurred on the system bus can be stored in the non-volatile memory, it is not possible to know which device has generated the error and the error occurs. There was a problem that we could not pursue the cause of.

Therefore, the present invention has been made to solve the above problems, and the information processing apparatus of the present invention is
The purpose of the present invention is to identify the device that has detected an error and to improve the maintainability associated with error processing.

[0007]

SUMMARY OF THE INVENTION The present invention is an information processing apparatus having a plurality of devices connected via a bus, wherein the devices are:
The recording medium further comprises a detection unit for detecting an error, and further includes a recording unit for recording the information of the device in which the error is detected as an error event on a recording medium according to the detection result of the detection unit. And

With such a structure, it is possible to identify the device in which the error is detected and improve the maintainability associated with the error processing.

Further, the present invention is directed to an information processing apparatus having a plurality of devices connected via a bus, and having a recording medium in which the information of the device in which an error is detected is recorded as an error event together with the type of error. In the step of reading the error event recorded in the storage medium, and the reading result of the reading step,
And a step of identifying a device that has detected an error.

Because of such a configuration, it is possible to identify the device in which the error is detected and improve the maintainability associated with the error processing.

Further, according to the present invention, in an information processing apparatus having a plurality of devices connected via a bus, the type of error and the information of the device in which the error is detected are recorded as an error event. It is characterized by comprising a medium, a unit for reading out an error event recorded in the storage medium, and a unit for specifying a device in which an error is detected according to a reading result of the reading unit.

Because of such a configuration, it is possible to identify the device in which the error is detected and improve the maintainability associated with the error processing.

[0013]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an information processing apparatus according to an embodiment of the present invention. This information processing device
A workstation-type or server-type computer system whose motherboard has
Host bus 30, PCI buses 60, 70, memory bus 8
0, system management bus (hereinafter referred to as SM bus) 14
0, an industry standard architecture bus (hereinafter referred to as ISA bus) 150 and an internal integrated circuit bus (hereinafter referred to as I2C bus) 250 are wired.

In the main body of the computer, a CPU 1
0, 20, CPU-PCI bridge device (hereinafter referred to as north bridge) 40, main memory 50, display device 9
0, a RAID device 100, a LAN device 110, a card bus device 120, a PCI-ISA bridge device (hereinafter referred to as a south bridge) 130, a GA 160 in which various input / output peripheral devices are system-integrated, a BIOS-ROM 170,
Keyboard device (hereinafter referred to as KB) 180, floppy disk drive device (hereinafter referred to as FDD) 19
0, a motherboard management controller (hereinafter referred to as BMC) 200, a field replacement unit (hereinafter referred to as FRU) 210, a sensor data storage device (hereinafter referred to as SDR) 220, a sensor 230, a system event log (hereinafter referred to as 240) and the like.

Next, the function and configuration of each component provided in the computer main body of FIG. 1 will be described.

The CPUs 10 and 20 are realized by, for example, microprocessors manufactured and sold by Intel Corporation of the United States. The host bus 30 directly connected to the input / output pins of the CPUs 10 and 20 has a 64-bit width data bus having a bandwidth of 133 Mhz.
Further, the CPUs 10 and 20 have pins for inputting SMI signals.

The main memory 50 is a memory device that stores an operating system, a device driver, an application program to be executed, processing data, etc., and is composed of a plurality of dual in-memory modules (hereinafter referred to as DIMMs). To be done. The main memory 50 is composed of a system memory mounted on the motherboard in advance and an expansion memory mounted by the user as needed. As the DIMMs forming the system memory and the extended memory, a high-speed memory such as a synchronous DRAM or a Rambus that needs to be supplied with a memory clock for each bank is used.

The main memory 50 is connected to the north bridge 40 via a dedicated memory bus 80 having a 64-bit data bus having a bandwidth of 133 Mhz. The data bus of the host bus 30 can also be used as the data bus of the memory bus 80. in this case,
The memory bus 80 is composed of an address bus and various memory control signal lines.

The north bridge 40 is a bridge LS that connects the host bus 30 and the two PCI buses 60 and 70.
I, and functions as one of the bus masters of the PCI buses 60 and 70. This north bridge 40 is a PCI bus 6.
0 and 70, a bus arbitration circuit between devices, a function of bidirectionally converting a bus cycle including data and an address between the host bus 40 and the PCI buses 60 and 70, and a main memory bus 80. It has a function of controlling access to the memory 50.

The PCI buses 60 and 70 are clock synchronous type input / output buses, and all bus cycles on the PCI buses 60 and 70 are performed in synchronization with the bus clock. PCI
The maximum frequency of the bus clock is 33 MHz. PC
The I buses 60 and 70 are addresses / time-divisionally used.
It has a data bus. This address / data bus is 32 bits wide.

According to the PCI standard Rev. 2.2 issued on December 18, 1998, the data transfer cycle between the PCI devices (initiator and target) on the PCI buses 60 and 70 is the address phase and the subsequent 1 It consists of the above data phases. In the address phase, the address and transfer type are output, and in the data phase, 8-bit, 16-bit, 24-bit or 32-bit data is output.

Display device 90 connected to PCI bus 60
Includes a video memory (hereinafter referred to as VRAM), stores the image data expanded in the main memory 50 in the VRAM, and stores the image data in an LCD (not shown) or an external CR.
Display on the T display.

The RAID device 100 connected to the PCI bus 60 is a RAID that controls a plurality of hard disk drives (hereinafter referred to as HDDs) arranged in an array.
Built-in controller. RAID controller is H
As a measure against a DD failure, redundant information for restoring the original data is stored in the HDD forming the array. Furthermore, R
The AID device 100 stores an operating system of a computer system, application programs, and data.

LAN device 1 connected to PCI bus 70
10 indicates packet data of 10 Mbps / 100 Mbps
Control the asynchronous data transfer of s. LAN device 110
Is connected to an external LAN line via an RJ45 connection port (not shown).

The card bus device 120 connected to the PCI bus 70 has a plurality of slots for inserting and removing a PC card (not shown), and for various settings of the PC card and data transfer between the PCI bus 70 and the PC card. Function as an interface.

The south bridge 130 is a PCI bus 60.
Is a bridge LSI that connects the SM bus 140 and the ISA bus 150. This South Bridge 130 has S
The M bus 140 and the ISA bus 150 are connected and function as an interface between various buses. In addition, the south bridge 130 sends the SMI signal to the CPU upon detection of the PERR signal or the SERR signal on the PCI buses 60 and 70.
It has a built-in circuit for issuing to 10 and 20.

The ISA bus 150 has a GA 16 integrated with various input / output circuits such as KBC and FDC.
0, and the BIOS-ROM 17 in which the error logging processing program according to the embodiment of the present invention and the program for setting the computer configuration are stored.
0 is connected. KBC is KB18 for data input
The control of 0 is executed. The FDD 190 stores an FD that stores a maintenance tool program according to an embodiment of the present invention.
Can be loaded.

The SM bus 140 is a serial bus having a clock signal and a data / address line, and is a BMC 20.
Connected to 0. The south bridge 130 is a BIOS-
Under the control of the error processing program recorded in the ROM 180, communication is performed with the BMC 200 via the SM bus 140, and the BMC 200 is notified of error information generated on the PCI buses 60 and 70. November 1, 1999
Intelligent Putform Management Interface Standards (hereinafter referred to as IPMI) Rev. 5 issued 1.1 discloses a method (protocol) for accessing the BMC 200. The execution of the error logging process, which is an embodiment of the present invention, will be described in detail later. In addition, the BMC connected to the I2C bus 250
The 200 functions as an interface between the SM bus 140 and the I2C bus.

The I2C bus 250 is a bidirectional bus composed of one clock signal line and one data line,
FRU210, SDR220, sensor 230, and SE
It is connected to L240.

The FRU 210 is a serial bus connection type EEPROM, and in order to describe information (types of mother board and various devices) of each module constituting the computer, a vendor ID such as a maker number and a serial number.
Information indicating the device ID is stored at the time of manufacture. When the maintenance tool program according to the embodiment of the present invention is executed,
Referring to the serial number stored in FRU210, PC
Identify the failing device on the I-bus 60, 70.

The SDR 220 is a serial bus connection type EEPROM, and stores the types of sensors (temperature, voltage, etc.) managed by the BMC 220, threshold values for identifying abnormalities, and the like during manufacturing.

The sensor 230 is an output voltage (± 12, ± 5, +3.3, etc.) from the voltage circuit on the motherboard, PC
SERR signal / PER issued on I-bus 60, 70
Issuance of R signal and temperature of CPU etc. are monitored. The sensor 230 is polled by the BMC 200 at predetermined intervals.

The SEL 240 is a serial bus type E
It is an EPROM and stores error information when the BMC 200 detects an abnormality on the motherboard or when the sensor 230 detects an error exceeding a threshold value.

As one embodiment of the present invention, the devices on the PCI bus are the north bridge 40, the display device 90,
The RAID device 100, the LAN device 110, the card bus device 120, and the south bridge 130. Each PCI
Functions common to the devices are described as follows.

Each PCI device contains a configuration register such as a device identification register and a status register, and a configuration space for accessing the register is provided with about 256 bytes. The device identification register is arranged at addresses 00hex and 02hex in the configuration space and stores the values of the vendor ID and the device ID. The vendor ID indicates the manufacturer of the PCI device. Device ID
Identifies PCI devices manufactured by the manufacturer specified by the vendor ID. The status register is located at address 06hex in the configuration space and is used to record the event that occurred on the PCI bus. When an unrecoverable system error is detected on the PCI bus and the PCI device outputs the SERR signal, the value of bit 14 of the status register is set to 1. When the PCI device detects a data parity or address parity error, it sets the value of bit 15 of the status register to 1.

Further, the PCI device arranges a command register at 04hex in the configuration space. Bit 6 of this command register, called the Parity Error Response, controls the operation of the device when a parity error occurs. When the value of bit 6 of this command register is 1, the PCI device issues a PERR signal on the PCI bus in response to a data or address parity error. Bit 8 of this command register is S
Called ERR enable, the PCI device is
Controls whether to drive the signal. When the value of bit 8 of this command register is 1, the driving for generating the SERR signal is permitted.

The PCI devices (initiator and target) check the parity line in the data phase of the transaction. In the write cycle of a transaction on the PCI bus, if the target detects a data parity error, the value of the parity error detection bit in the status register is set to 1. When the value of the parity error response bit of the command register is set to 1, the target issues the PERR signal in the cycle. When the initiator of the cycle detects that the target issues the PERR signal,
Set the data parity error detection bit in the status register. Also, if the initiator detects a data parity error in a read cycle of a transaction on the PCI bus, the initiator issues a PERR signal. The initiator sets the data parity error detection bit in the status register.

The PCI devices (initiator and target) also check the parity line in the address phase of the transaction. The PCI device that has detected the address / parity error always sets the value of the parity error detection bit to 1 as in the case of the data parity error. The PCI device issues a SERR signal on the PCI bus if both the SERR signal enable bit and the parity error response bit in the command register are set.

Furthermore, if the PCI device detects some kind of error and determines that the error is fatal to the computer system, or if another method cannot notify the system of the error or recover the error. If so, the PCI device issues a SERR signal on the PCI bus. When outputting the SERR signal, the PCI device always sets the value of the system notification bit of the status register to 1.

Next, the north bridge 40 has the CPU 1
A configuration cycle generating circuit is built in for accessing the configuration register of each PCI device by 0 and 20. CPU10,20
When accessing the configuration register, four levels of address designation of bus number, device number, function number, and register number are set in the configuration address register. The bus number indicates the PCI bus number. The device number indicates the device number designated on one bus number. The function number is used to identify the function included in one device, that is, included in the multi-function device. What is a register number?
It is used to specify the address address of the configuration space assigned to one function.

In one embodiment of the present invention, as shown in FIG. 2, the bus number, device number, and function number of the north bridge 40 are "0, 0, 0", respectively. The bus number, device number, and function number of the south bridge 130 are "0, 1, 0", respectively. The bus number, device number, and function number of the display device 90 are “0, 2,
It is 0 ". The bus number, device number, and function number of the RAID device 100 are “0, 3, 0”, respectively. The bus number, device number, and function number of the card bus device 120 are “1, 1, 0”, respectively. The bus number, device number, and function number of the LAN device 110 are “1,
2, 0 ".

Further, the configuration address register of the north bridge 40 is a double word register, and the CPUs 10 and 20 are 0C of the I / O address space.
Double word I / O read or I to F8hex
When the / O write is executed, the register is processed as a read or a write.

The north bridge 40 also contains a configuration data register. The configuration register is a double word register
Located in the "0CFC hex" of the / O address space,
Read or write access is performed to the data register at the address specified by the configuration address register from the CPU. In one embodiment of the present invention, the data register is a status register, which is read-accessed by the CPUs 10 and 20.

FIG. 3 shows an SE according to an embodiment of the present invention.
The recording format of L240 is shown. SEL240 is
The BMC 200 writes predetermined information in a predetermined address for each event. The recording format of SEL240 is
Along with the entry (serial) number, the device that stored the information, the time, and the SERR signal as event data 1 /
Information indicating the generation of the PERR signal is written at a predetermined address. In one embodiment of the present invention, event data 2 is prepared at the reserved address of the SEL 240 format in order to further write information indicating the bus number, function number and device number.

FIG. 4 shows an error logging process according to the embodiment of the present invention.

Next, referring to FIG. 4, a BIOS-ROM
The process of writing the error event stored in 170 and writing to the SEL 240 when the SERR signal / PERR signal is generated will be described as follows.

The sensor 230 detects the SERR signal / PERR signal issued by the PCI device on the PCI buses 60 and 70. The sensor 230 uses the SERR signal / PER
When the R signal is detected, the south bridge 130 is instructed to output the SMI signal to the CPUs 10 and 20. The south bridge 130 outputs an SMI signal to the CPUs 10 and 20 according to an instruction from the sensor 230. When the CPUs 10 and 20 receive the SMI signal, they switch the operation mode of the CPUs 10 and 20 to the system management mode (hereinafter referred to as SMM). SM placed on SMM mode after switching to SMM mode
The I handler activates the error logging processing program stored in the BIOS-ROM 170.

In response to the SMI signal, the activated error logging processing program sequentially determines which device on the PCI buses 60, 70 output the SERR signal / PERR signal, bit 14 of the status register of each device. Check the values of 15 and 15.

As described above, the status register of each PCI device is arranged in the configuration space, and the bus number, device number, function number, and register number are specified in the configuration address register of the north bridge 40, From the configuration data register, it is checked whether or not there is a bit indicating the issue / detection of the PERR signal / SERR signal.

The error logging processing program sets the bus number, device number, function number and register number in the configuration address register to "0, 0, 0,
Set to 0 ”and I / O for the PCI device to be inspected.
O read access is executed (S100). The error logging processing program ticks the values of bits 14 and 15 of the status register read via the configuration data register (S110).

Status register bit 14 or 15
When it is determined that the value of is set to 1, that is, when this PCI device issues and detects the SERR signal / PERR signal, the error logging processing program is
In the event data 1 and 2 of the SEL 240 shown in FIG.
R signal), and the bus number, function number, and device number of the device that issued / detected the error. Based on the instruction, the BMC 200 records, as an error event, additional information such as the serial number of the event, the type of sensor and the time in the SEL 240 (S1).
10: Yes → S190).

On the other hand, in S110, the device
If it is determined that the R signal / PERR signal is not issued / detected, the error logging processing program increments the value of the function number by 1 (No in S110 → S120).
The error logging processing program sends I address to the address specified by the configuration address register.
/ O Read access is executed.

As a result of the I / O read access, if it is determined that the target device does not exist on the PCI bus, the error logging processing program sets the function number to 0,
The value of the device number is incremented by 1 (No in S130 →
S140). The error logging processing program executes I / O read access to the address specified by the configuration address register.

If it is determined as a result of the I / O read access that the target device does not exist on the PCI bus, the error logging processing program sets the device number and the function number to 0 and sets the value of the bus number to 1 only. Increase (S15
0 No → S160). The error logging processing program executes I / O read access to the address specified by the configuration address register.

If it is determined that the target device does not exist on the PCI bus as a result of the I / O read access, the error logging processing program determines whether all PCI devices have been checked. If it is determined that all PCI devices have not been checked, the error logging processing program returns the processing to S120 (No in S170 →
No of S180 → S120). When the error logging processing program determines that all PCI devices have been checked, the processing ends (Yes in S180).
s).

On the other hand, as a result of the I / O read access, the PC
If it is determined that the target device exists on the I-bus (Yes in S130, Yes in S150, Y in S170).
es), the error logging processing program checks the values of bits 14 and 15 of the status register of the PCI device as in the processing of S110. PCI device is S
If the ERR signal / PERR signal has been issued / detected, the error logging processing program determines the error type (SERR signal / PERR signal) and the device that issued / detected the error in events 1 and 2 of SEL240 as error events. Instruct the BMC 200 to write the bus number, function number, and device number of the device (S1
90).

FIG. 5 relates to an embodiment of the present invention,
An example of the error event recorded in SEL240 by the error logging processing program is shown. In particular, RAI
This is an error event in which the D device 100 issues a SERR signal.

FIG. 6 relates to one embodiment of the present invention,
The processing of a maintenance tool program is shown.

Next, with reference to FIGS. 5 and 6, the procedure for identifying the device that issued the SERR signal will be described below.

When the SERR signal is issued, since the system has an unrecoverable error, the OS of the computer system normally stops the processing. A user of a computer system requests maintenance personnel to recover or repair the system. The maintenance staff uses the FDD 1 of the computer system to store the FD in which the maintenance tool program brought in is written.
Load 90 and power on the system.

The maintenance tool program is started from the FD at the same time when the computer system is turned on and executes the initialization of the computer system. The activated maintenance tool program instructs the BMC 200 to read the error event of the SEL 240. BMC200
SEL24 according to the instructions of the maintenance tool program.
Event data recorded in 0 is sequentially read and SERR recorded in SEL240 by error logging processing.
Only the event of the signal / PERR signal is acquired. That is,
BMC200 reads the entry (serial number)
Then, it is checked whether or not the data 04hex or 005hex indicating the detection of the SERR signal / PERR signal is recorded in the event data 1 (S200).

If the event data 1 has a SERR signal / P
If it is determined that the data indicating the detection of the ERR signal is not recorded, the maintenance tool program executes SEL240.
Reads the next entry from (No in S200 → S25
0). The maintenance tool program checks whether the event data 1 of the read entry is data indicating the detection of the SERR signal / PERR signal.

On the other hand, in S200, S is added to the event data 1.
When it is determined that the data indicating the detection of the ERR signal / PERR signal is recorded, the BMC 200 acquires the value of the event data 2 of the entry according to the instruction of the maintenance tool program, and the bus number, the device number, the function number. Is obtained (S210). In this case, PCI
When an error occurs in the SERR signal on the bus, the bus number, device number, and function number are "0, 0, 0Bhex", respectively.
Is.

Next, the maintenance tool program sets the acquired bus number, device number, and function number to the north bridge 4
Set to 0 configuration address register,
Acquire the vendor ID and device ID data of the PCI device from the configuration data register (S
220). The maintenance tool program is the acquired PCI
In order to specify the vendor ID of the device and the name of the PCI device for the data of the device ID, the name of the device is acquired from the device configuration list table stored in the FRU 210. The name of the device that issued the SERR signal is displayed on the display device 90 (S230).

The maintenance tool program waits until all the entries recorded in SEL240 are checked, until the S200
~ The process of S230 is repeated (No of S240). When the last entry is checked, the maintenance tool program ends the process (Yes in S240).

By adopting the configuration of the present invention,
The maintenance staff can easily identify the failed PCI device from the name of the PCI device that issued / detected the error displayed on the display screen.

In the embodiment of the present invention, the sensor 230 is configured to detect the SERR signal / PERR signal issued by the device on the PCI buses 60 and 70. By connecting to the interrupt input (IRQ) terminal of the bridge 130, the south bridge 130 can detect the SERR signal / PERR signal and issue an SMI signal to the CPUs 10 and 20.

Further, in the embodiment of the present invention, the SEL 240 is used as the record of the error logging process, but it is stored in the HDD of the RAID device 100 or the FD of the FDD 190 as a record of the error event of the error logging process in a file format. You can also let it.

[0070]

As described above, according to the present invention, the device in which an error has occurred or the device in which an error has been detected can be specified, and the maintainability associated with error processing can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing an address number of each PCI device of the computer system according to the embodiment.

FIG. 3 is a view showing a recording format of SEL according to the same embodiment.

FIG. 4 is a flowchart showing an error logging process according to the same embodiment.

FIG. 5 is a diagram showing error information recorded in SEL by the error logging process according to the embodiment.

FIG. 6 is a flowchart showing processing of a maintenance tool program according to the same embodiment.

[Explanation of symbols]

10, 20 ... CPU, 30 ... Processor bus, 40 ... Northbridge, 50 ... DIMM, 60 ... PCI bus 0,
70 ... PCI bus 1, 80 ... Memory bus, 90 ... Display device, 100 ... RAID device, 110 ... LAN controller device, 120 ... Card bus controller device, 130
… South Bridge, 140… SM Bus, 150… ISA
Bus, 160 ... System I / O, 170 ... BIOS-R
OM, 180 ... keyboard (KB), 190 ... FDD,
200 ... BMC, 210 ... FRU, 220 ... SDR, 2
30 ... Sensor, 240 ... SEL, 250 ... I2C bus

Claims (9)

[Claims] 1. An information processing apparatus having a plurality of devices connected via a bus, wherein the device comprises a detection means for detecting an error during a transaction of the bus, and further comprises: An information processing apparatus, comprising: a recording unit that records, as an error event, information of a device in which an error is detected on a recording medium, according to a detection result, together with the type of the error. 2. The information processing apparatus according to claim 1, wherein the device information includes at least a number for identifying a bus type, a number for identifying a device type, and a number for identifying a function. . 3. An information processing apparatus comprising: a plurality of devices connected via a bus; and a recording medium in which information of a device in which an error has been detected is recorded as an error event together with the type of error. An information processing apparatus maintenance method, comprising: a step of reading an error event recorded in a storage medium; and a step of identifying a device in which an error is detected according to a reading result of the reading step. 4. The maintenance method for an information processing apparatus according to claim 3, wherein in the step of reading the error event, information of a device in which an error is detected recorded in the storage medium is read. 5. The maintenance method for an information processing apparatus according to claim 4, wherein the identifying step displays the device on a display device based on the information of the device in which the error is detected in the reading step. 6. An information processing apparatus having a plurality of devices connected via a bus, together with the type of error,
A recording medium in which information of a device in which an error is detected is recorded as an error event, a unit for reading out the error event recorded in the storage medium, and a unit for identifying the device in which the error is detected according to the reading result of the reading unit. An information processing apparatus comprising: 7. The information processing apparatus according to claim 6, wherein the reading unit reads information of a device in which an error is detected, which is recorded in the storage medium. 8. The information processing apparatus according to claim 7, wherein the specifying unit displays the device on a display device based on information of the device in which the error is detected. 9. The information processing apparatus according to claim 8, wherein the device information includes at least a number for identifying a bus type, a number for identifying a device type, and a number for identifying a function. .