CN107451028A - Error condition storage method and server - Google Patents
Error condition storage method and server Download PDFInfo
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- CN107451028A CN107451028A CN201610381977.1A CN201610381977A CN107451028A CN 107451028 A CN107451028 A CN 107451028A CN 201610381977 A CN201610381977 A CN 201610381977A CN 107451028 A CN107451028 A CN 107451028A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
Abstract
A kind of error condition storage method, by a server perform, the server include a processing unit, a basic input output system, at least one peripheral device, and one comprise at least a non-voltile memory chipset.This method includes：The processing unit produces a processing interrupt requests, the periphery erroneous trigger is that at least one of which for being relevant at least one peripheral device is in error condition according to a periphery erroneous trigger；The basic input output system is according to the processing interrupt requests of the processing unit, record the status data of each of at least one peripheral device, and be stored in the program of the non-voltile memory of the chipset, the status data report include a device identification and a pair should device identification state categories.By the error condition storage method, the status data of each of at least one peripheral device can be saved, to help user to find out the reason at least one of which of at least one peripheral device makes a mistake, so as to carry out more quickly except mistake.
Description
Technical field
The invention relates to a kind of storage method and equipment, particularly relates to a kind of error condition storage method and server.
Background technology
Existing server is during operation, a wrong such as perimeter component interconnection means (PCI device) mistake that may occur, the perimeter component interconnection means are, for example, network card, graphics processing card, video signal accelerator card etc., and can record an error condition in its status register when the perimeter component interconnection means make a mistake.In order to improve system reliability, one basic input output system of the server is generally assembled when such mistake occurs, to perform a system management interrupt (System Management Interruption) program to read the status register of the perimeter component interconnection means and record the error condition.
But, if user needs repairing during error detection, error condition for being relevant to the perimeter component interconnection means to make a mistake that the basic input output system is recorded can not probably be only transmitted, the reason for making mistake is seen at a glance, and must be with maintenance micro-judgment, or time-consumingly all perimeter component interconnection means are detected one by one, it can just find the place of error.In addition, the system management interrupt program of the basic input output system is usually designed to remove the status data of all status registers after the basic input output system records the error condition, causes user to be difficult to detect mistake to the perimeter component interconnection means to make a mistake and is diagnosed to be reason.
The content of the invention
It is an object of the invention to provide a kind of error condition storage method.
For the above-mentioned purpose, error condition storage method of the present invention, the server includes a processing unit, at least one peripheral device, a basic input output system, a control chip group, and one electrically connect the control chip group chipset, and one electrically connect the chipset internal memory, the chipset comprises at least a non-voltile memory and a baseboard management controller, and the error condition storage method includes a step（A）, a step（B）, a step（C）, and a step（D）.
The step（A）It is that the processing unit handles interrupt requests according to a periphery erroneous trigger, generation one, the periphery erroneous trigger is that at least one of which for being relevant at least one peripheral device is in error condition.
The step（B）Be processing interrupt requests of the basic input output system according to the processing unit, the status data of each of at least one peripheral device be stored into the internal memory, the status data report include a device identification and a pair should device identification state categories.
The step（C）The basic input output system sends a data and is ready for baseboard management controller of the order via the control chip group to the chipset, and the data are ready for order and indicate that the status data of each of at least one peripheral device has been written into the internal memory.
The step（D）The baseboard management controller is ready for order according to the data, to access the status data of each of at least one peripheral device from the internal memory, and writes the non-voltile memory of the chipset.
It is another object of the present invention to provide a kind of server that can implement the error condition storage method.
For the above-mentioned purpose, server of the present invention include a processing unit, at least one peripheral device, a basic input output system, one electrically connect the basic input output system control chip group, one electrically connect the control chip group chipset, and one electrically connect the chipset internal memory.
The chipset comprises at least a non-voltile memory, and a baseboard management controller.
The processing unit produces a processing interrupt requests, the periphery erroneous trigger is that at least one of which for being relevant at least one peripheral device is in error condition according to a periphery erroneous trigger.
The status data of each of at least one peripheral device is stored into the internal memory according to the processing interrupt requests of the processing unit by the basic input output system, the status data report include a device identification and a pair should device identification state categories.
The basic input output system sends a data and is ready for baseboard management controller of the order via the control chip group to the chipset, and the data are ready for order and indicate that the status data of each of at least one peripheral device has been written into the internal memory.
The baseboard management controller is ready for order according to the data, to access the status data of each of at least one peripheral device from the internal memory, and writes the non-voltile memory of the chipset.
Compared with prior art, error condition storage method and server of the present invention are by when at least one of which for finding at least one peripheral device is in error condition, trigger the basic input output system and the status data of each of at least one peripheral device is stored into the internal memory, and the baseboard management controller is from the memory access status data and is stored into the non-voltile memory, the status data of each of at least one peripheral device can be saved, to help user to find out the reason at least one of which of at least one peripheral device makes a mistake, so as to carry out more quickly except mistake.
【Brief description of the drawings】
The other features and effect of the present invention, will clearly it be presented in the embodiment with reference to schema, wherein：
Fig. 1 is a block diagram, illustrates an embodiment of server of the present invention.
Fig. 2 is a flow chart, illustrates an embodiment of error condition storage method of the present invention.
【Embodiment】
Refering to Fig. 1, an embodiment of server of the present invention, periphery connection bus 1, a peripheral device 2, a control chip group 3, a chipset 4, a basic input output system (Basic Input/Output are included
System) 5, one internal memory 6, and a processing unit 7.
The interconnection of a periphery connection bus 1 such as perimeter component (Peripheral Component Interconnect,
PCI) bus or e.g. a high speed perimeter component interconnection bus (Peripheral Component
Interconnect express, PCIe)。
The peripheral device 2 is perimeter component interconnection means (PCI device), electrically connects periphery connection bus 1, and for example, network card, graph processing chips, video signal speed-up chip etc..The present embodiment for convenience of description for the sake of, peripheral device 2 is only drawn in Fig. 1 as signal, but its number can also be two, three etc.., without being limited with illustrated.The peripheral device 2 has a status register（It is not shown）, and when operating normal, the peripheral device 2 can record a normal operating conditions in the status register, and when running makes a mistake, and can record an error condition in the status register.Herein it should be noted that, the error condition mentioned in the present embodiment, it is that can correct perimeter component interconnection errors (correctable PCI error) selected from together bit-errors (PERR), a system mistake (SERR), one, one can not correct perimeter component interconnection errors (uncorrectable PCI error), the one of which of a fatal perimeter component interconnection errors (fatal PCI error).
The chipset 4 includes a peripheral device 41, a baseboard management controller (Baseboard Management Controller) 42, an and non-voltile memory 44, in the present embodiment, the non-voltile memory 44 is located in the baseboard management controller 42 of the chipset 4, but is not limited thereto.The peripheral device 41 is connected to periphery connection bus 1, and e.g. one plate (on-board) visual graphic array (VGA) chip, and there is a status register（It is not shown）, the peripheral device 41 operate it is normal when, the normal operating conditions can be recorded in the status register, and when running makes a mistake, the error condition can be recorded in the status register.The baseboard management controller 42 to supervise the server such as rotation speed of the fan, supply voltage, operation situation system temperature, and the non-voltile memory 44 of the baseboard management controller 42 includes the system journal (system log) 45 of a System Event Log (system event log) 43 and one, the System Event Log 43 to record a device identification (device ID) and a pair should device identification error condition.The system journal (system log) is recording the status data of such as peripheral device 2, the peripheral device 41, the status data report include a device identification and a pair should device identification state categories, and the state categories can be the normal operating conditions and the one of which of the error condition.
The control chip group 3 be a platform controller hub (Platform Controller Hub,
PCH), a for example, South Bridge chip, and the control chip group 3 electrically connects periphery connection bus 1, the chipset 4 and the basic input output system 5.When the control chip group 3 connects bus 1 via the periphery, read the peripheral device 2 status register and or the peripheral device 41 status register, and learn the peripheral device 2 and or the peripheral device 41 when being in the error condition, a periphery erroneous trigger can be produced, to indicate that any one peripheral device that the connection of bus 1 is connected with the periphery is in the error condition.
The internal memory 6 includes state storage block 61, and state storage block 61 is that the peripheral device 41 (that is, the VGA chips) that the chipset 4 is distributed in the internal memory 6 is deposited data and can accessed for the baseboard management controller 42.The internal memory 6 is, for example, DRAM (DRAM), second generation double data rate (DDR2) internal memory or for example, third generation double data rate (DDR3) internal memory for the peripheral device 41 (that is, the VGA chips) storage data.
The processing unit 7 is the CPU of the server, electrically connect periphery connection bus 1 and including a north bridge chips 71, the north bridge chips 71 are used to handle high-speed signal, such as high speed perimeter component interconnection (PCIe) interface signal etc., the communication being also responsible between the control chip group 3.The north bridge chips 71 also have the function of the similar control chip group 3, when it connects bus 1 via the periphery, read the peripheral device 2 and or the peripheral device 41 status register, and learn the peripheral device 2 and or the peripheral device 41 when being in the error condition, a periphery erroneous trigger can be produced, to indicate that any one peripheral device that the connection of bus 1 is connected with the periphery is in the error condition.
The basic input output system 5 electrically connects the control chip group 3, and has a system management interrupt processing module (system management interrupt
handler)51.When the processing unit 7 receives the periphery erroneous trigger from the control chip group 3, or during the periphery erroneous trigger from the north bridge chips 71, into a SMM (System Management Mode,
SMM), and by the system management interrupt processing module 51 of system control right transfer to the basic input output system 5, to be judged to interrupt Producing reason by the system management interrupt processing module 51.The system management interrupt processing module 51 for example can be a program.
Refering to Fig. 2, an embodiment of error condition storage method of the present invention, performed in the server shown in Fig. 1, and the method includes the steps of.
First, in step（A）, the processing unit 7 is according to a periphery erroneous trigger, the processing interrupt requests of generation one.As it was previously stated, the periphery erroneous trigger is when the peripheral device 2 is in the error condition, as produced by the control chip group 3, or as produced by the north bridge chips 71.The processing interrupt requests are a system management interrupt (System Management
Interruption, SMI), now, the processing unit 7 enters the SMM (System Management Mode, SMM) and by the system management interrupt processing module 51 of system control right transfer to the basic input output system 5.
Then, in step（E）Processing interrupt requests of the system management interrupt processing module 51 of the basic input output system 5 in response to the processing unit 7, record the periphery wrong data, the periphery wrong data is the status data of the peripheral device in error condition, and including a device identification and a pair should device identification error condition.Such as, when the peripheral device 2 operates abnormal, the periphery wrong data report includes the device identification of the peripheral device 2, and corresponding error condition, example as the aforementioned the same bit-errors, the system mistake, this can correct perimeter component interconnection errors, this can not correct perimeter component interconnection errors, and the one of which of the fatal perimeter component interconnection errors.In the present embodiment, the size of the periphery wrong data is about 12 bytes.
Then, in step（F）, the system management interrupt processing module 51 of the basic input output system 5 sends the periphery wrong data, via the baseboard management controller 42 of the control chip group 3 to the chipset 4.
Then, in step（G）, the baseboard management controller 42 writes the periphery wrong data System Event Log 43 of the non-voltile memory 44.
Then, in step（B）, the status data of each peripheral device is stored into the internal memory 6 by the system management interrupt processing module 51 of the basic input output system 5 according to the processing interrupt requests.The step（B）Including following sub-step.
Step（B0）, the system management interrupt processing module 51 of the basic input output system 5 records the status data of each peripheral device 2.Specifically, the basic input output system 5 scans all peripheral devices connected in periphery connection bus 1, to read the status data of each peripheral device (peripheral device 2, the peripheral device 41 in this example), and it is temporarily stored into such as one external DRAM (DRAM) of the processing unit 7（It is not shown）.Such as the peripheral device 2 operates exception, the peripheral device 41 is normal operation, the status data that the basic input output system 5 is recorded, device identification and the corresponding error condition including the peripheral device 2, and the device identification of the peripheral device 41 and the corresponding normal operating conditions.
Step（B1）, the system management interrupt processing module 51 of the basic input output system 5 obtains a memory address data, and the memory address data are relevant to the address of the state storage block 61 in the internal memory 6.Specifically, the memory address data storage is in a memory mapping buffer (the memory mapped I/O of the peripheral device 41
Register, MMIO register) in (not shown), and the memory address data are in start, the address of the peripheral device 41 is distributed to using memory address image technology by the basic input output system, and the memory address data indicate the initial address and access range of the state storage block 61 of the internal memory 6.
Step（B2）, the system management interrupt processing module 51 of the basic input output system 5 is according to the memory address data, by the external DRAM (DRAM) of the processing unit 7（It is not shown）The status data of middle each kept in peripheral device (peripheral device 2, the peripheral device 41 in this example) copies to the state storage block 61 of the internal memory 6.Preferably, the basic input output system 5 judges the size of the status data, whether within the access range of the state storage block 61 indicated by the memory address data, if in access range, the state that the status data is then once stored in the internal memory 6 stores block 61, if it exceeds the access range, then be divided into and be repeatedly stored in state storage block 61, be the data volume that deposit meets the access range each time.
Then, in step（C）The system management interrupt processing module 51 of the basic input output system 5 sends a data and is ready for order, via the control chip group 3 to the baseboard management controller 42, the data are ready for order and indicate that the status data of each peripheral device 2 is had been written into the state storage block 61 of the internal memory 6.
Then, in step（D）The baseboard management controller 42 of the chipset 4 is ready for order according to the data, the status data of each peripheral device (peripheral device 2, the peripheral device 41 in this example) is accessed to be stored from the state of the internal memory 6 in block 61, and writes the system journal 45 of the non-voltile memory 44.It is preferred that the basic input output system 5 judges whether that the status data of each peripheral device (peripheral device 2, the peripheral device 41 in this example) has been completely copied to the state storage block 61 of the internal memory 6 according to the size of the status data.If the result judged is no, return to step（B2）The state that the status data not replicated is stored in the internal memory 6 stores block 61；If the result judged is yes, the status data of the peripheral device 2, the status register of the peripheral device 41 is removed.
From described above,The wrong storage method of the present invention,Can be when at least one peripheral device makes a mistake,The periphery wrong data is stored to the System Event Log 43 of the baseboard management controller 42 by the system management interrupt processing module 51 of the basic input output system 5,And the status data of each peripheral device is stored to the internal memory 6,And the baseboard management controller 42 stores the status data of each peripheral device to the system journal 45 of the non-voltile memory 44,Can be before the system management interrupt processing module 51 removes the status data of the status register of each peripheral device 2,The status data of the periphery wrong data and each peripheral device is preserved,With mistake occur when assisting user judge whether because other peripheral devices occur problem and trigger,So as to carry out more quickly except mistake,Therefore,Really it can reach the purpose of the present invention.
In summary, the various embodiments described above and diagram be only presently preferred embodiments of the present invention, but can not with restrictions the present invention implementation scope, i.e., the equivalent changes and modifications made generally according to claims of the present invention, should all remain within the scope of the patent.
Claims (10)
- A kind of 1. error condition storage method, performed by a server, the server include a processing unit, at least one peripheral device, a basic input output system, one electrically connect the basic input output system control chip group, one electrically connect the control chip group chipset, and one electrically connect the chipset internal memory, the chipset comprises at least a non-voltile memory and a baseboard management controller, characterized in that, the error condition storage method includes：（A）The processing unit produces a processing interrupt requests, the periphery erroneous trigger is that at least one of which for being relevant at least one peripheral device is in error condition according to a periphery erroneous trigger；（B）The status data of each of at least one peripheral device is stored into the internal memory according to the processing interrupt requests of the processing unit by the basic input output system, the status data report include a device identification and a pair should device identification state categories；（C）The basic input output system sends a data and is ready for baseboard management controller of the order via the control chip group to the chipset, and the data are ready for order and indicate that the status data of each of at least one peripheral device has been written into the internal memory；And（D）The baseboard management controller is ready for order according to the data, to access the status data of each of at least one peripheral device from the internal memory, and writes the non-voltile memory of the chipset.
- 2. error condition storage method according to claim 1, it is characterised in that also include：（E）The basic input output system also records a periphery wrong data according to the processing interrupt requests of the processing unit, the periphery wrong data report include a device identification and a pair should device identification error condition；And（F）The basic input output system sends the periphery wrong data, via the baseboard management controller of the control chip group to the chipset.
- 3. error condition storage method according to claim 2, it is characterised in that also include：（G）The baseboard management controller writes the periphery wrong data from the basic input output system one System Event Log of the non-voltile memory of the chipset（system event log）.
- 4. error condition storage method according to claim 1, it is characterised in that in the step（D）In, the baseboard management controller writes the status data of each of at least one peripheral device one system journal of the non-voltile memory of the chipset.
- 5. error condition storage method according to claim 1, it is characterized in that, the chipset of the server also includes a peripheral device, and the internal memory of the server has one to distribute to the peripheral device storage data of the chipset and can supply the state storage block of baseboard management controller access, wherein, the step（B）Including：（B0）The basic input output system records the status data of each of at least one peripheral device,（B1）The basic input output system obtains a memory address data, and the memory address data are relevant to the state storage block of the internal memory, and（B2）The basic input output system replicates the status data of each of at least one peripheral device in the state storage block of the internal memory according to the memory address data.
- 6. error condition storage method according to claim 1, it is characterised in that the processing unit includes a north bridge chips, wherein, in the step（A）In, the periphery erroneous trigger is as produced by the north bridge chips of the processing unit and the control chip group one of which.
- 7. error condition storage method according to claim 1, it is characterised in that in the step（A）In, the processing interrupt requests caused by the processing unit are a system management interrupt (System Management Interruption, SMI), and the processing unit enters a SMM (System Management Mode, SMM).
- 8. a kind of server, it is characterised in that include：At least one peripheral device；One basic input output system；One control chip group, electrically connects the basic input output system；One chipset, the control chip group is electrically connected, and comprise at least a non-voltile memory, and a baseboard management controller；One internal memory, electrically connect the chipset；AndOne processing unit, according to a periphery erroneous trigger, a processing interrupt requests are produced, the periphery erroneous trigger is that at least one of which for being relevant at least one peripheral device is in error condition；Wherein, the status data of each of at least one peripheral device is stored into the internal memory according to the processing interrupt requests of the processing unit by the basic input output system, the status data report include a device identification and a pair should device identification state categories；Wherein, the basic input output system sends a data and is ready for baseboard management controller of the order via the control chip group to the chipset, and the data are ready for order and indicate that the status data of each of at least one peripheral device has been written into the internal memory；Wherein, the baseboard management controller is ready for order according to the data, to access the status data of each of at least one peripheral device from the internal memory, and writes the non-voltile memory of the chipset.
- 9. server according to claim 8, it is characterised in that the non-voltile memory of the chipset of the server has a System Event Log；The basic input output system also records a periphery wrong data according to the processing interrupt requests of the processing unit, the periphery wrong data report include a device identification and a pair should device identification error condition；The basic input output system sends the periphery wrong data, via the baseboard management controller of the control chip group to the chipset；The baseboard management controller writes the periphery wrong data from the basic input output system System Event Log of the non-voltile memory of the chipset.
- 10. server according to claim 8, it is characterized in that, the chipset of the server also includes a peripheral device, and the internal memory of the server has one to distribute to the peripheral device storage data of the chipset and can supply the state storage block of baseboard management controller access, the non-voltile memory of the chipset of the server has a system journal；The basic input output system records the status data of each of at least one peripheral device, and the memory address data for being relevant to state storage block are obtained, the status data of each of at least one peripheral device is replicated according to this in the state storage block of the internal memory；The baseboard management controller writes the status data of each of at least one peripheral device the system journal of the non-voltile memory of the chipset.
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Application publication date: 20171208 |
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