JP2003006256A - High-level synthesis device and high-level synthesis method for logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten behavioral time and reduce a logic circuit size for the logic circuit in which behavioral description defined by an array variable is synthesized with a high-level. SOLUTION: From the array variable and its size to analyze a behavioral description 1 defined by the array variable, analysis data, which is assigned with a virtual name corresponding to an array name and each of its addresses, is generated and rewritten in order to be referred and substituted to the variable which replaces read or write of the array with the above virtual name. The logical circuit is generated by the high-level synthesis of the rewritten behavioral description.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a high-level synthesis apparatus and a high-level synthesis method for a logic circuit.

[0002]

2. Description of the Related Art In designing an integrated circuit, a high-level synthesis technique for automatically synthesizing a logic circuit that realizes this operation has been put into practical use. In this high-level synthesis, HDL (Hardware Description) is generally used.
n Language) or the like to describe the operation of the hardware.

On the other hand, the operation of the hardware can be described in a programming language such as C language or C ++ language. When the behavioral description is made in these programming languages, even a user who does not know the hardware can design the logic circuit. Further, if the description in the programming language is processed by the compiler according to the language system, the circuit operation can be verified, and unlike the description in HDL, the verification by the simulator can be unnecessary. Therefore, the behavioral description in the programming language makes the logic circuit design easier and faster than the behavioral description in the HDL or the like.

When a variable is read or written by a behavioral description in such a programming language, a behavioral description defining an array variable may be performed. When this behavioral description is high-level synthesized, the array defined above is stored in RAM.
It is generally assigned to a storage element such as (Random Access Memory) or a register file.

[0005]

However, when a variable is read or written by a behavioral description in a programming language as shown in FIG.
A storage element 300 such as a RAM is required as shown in FIG. As a result, there is a problem that the circuit scale becomes large.

Further, since it is necessary to write a variable into the memory element once and then to read out the variable written in the memory element, the operation time of the logic circuit increases with the clock input in each operation. There was also a problem.

Therefore, the present invention facilitates logic circuit design by reading or writing variables according to the definition of array variables during behavioral description in a programming language, and shortens the operation time of the logic circuit after high-level synthesis and The purpose is to reduce the circuit scale.

[0008]

Means for Solving the Problem The above problem is in a high-level synthesis apparatus that synthesizes a logic circuit based on a behavioral description.
An array variable analysis unit that analyzes the array variables in the input behavioral description and generates array variable analysis data with each virtual name corresponding to the array name and its address,
A variable rewriting unit for generating a rewritten behavioral description from the behavioral description based on the array variable analysis data, and performing a high-level synthesis of the logic circuit based on the rewritten behavioral description. Solve with a synthesizer.

By the above means, even if the high-level synthesis is performed on the behavioral description defining the array variable, the array is not allocated to the storage element, but the logic circuit including the multiplexer circuit or the demultiplexer circuit can be synthesized.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Regarding the embodiments of the present invention,
A detailed description will be given with reference to the drawings.

As shown in FIG. 1, the high-level synthesis apparatus according to this embodiment includes a syntax analysis unit 2, an array variable analysis unit 4, and
The variable rewriting unit 6, the data flow analysis unit 8, the state allocation unit 10, and the binding unit 11 are provided.

The syntax analysis unit 2 analyzes the syntax of the input hardware behavioral description 1 in the programming language and creates the first data flow-3.

The array variable analysis unit 4 obtains the array variable and its size in the behavioral description 1 from the first data flow-3, and outputs the array variable analysis data with the array name and the virtual name corresponding to each address. Create 5.

The variable rewriting unit 6 creates a second data flow 7 in which the writing or reading of the array is rewritten so as to refer to or substitute for the variable replaced with the virtual name.

The data flow analysis unit 8 analyzes the second data flow 7 and outputs an optimized data flow 9. The state allocation unit 10 analyzes the delay of the operator in the optimized data flow 9 and allocates the execution clock (delay information) to each operator. The binding unit 11 synthesizes the logic circuit 12 by assigning an arithmetic unit, which is hardware, to each state-assigned operator.

FIG. 2 is an example of the behavioral description 1 shown in FIG. 1 and describes a variable reading operation.

In the behavioral description of FIG. 2, the first data flow-3 analyzed by the syntax analysis unit 2 is analyzed by the array variable analysis unit 4 as the array name r and the size 3 as shown in FIG. Variables r # 0 and r # corresponding to the index of
Array variable analysis data 5 is created in which 1 and r # 2 are registered as virtual names.

Next, in the variable rewriting unit 6, the array r
[0], r [1], r [2] are the virtual names r # 0, r #, respectively.
Rewrite to 1, r # 2. Also, the array r [i] whose index is a variable is rewritten to the description using the switch statement, and the rewritten operation description as shown in FIG. 4 is output. The post-rewrite operation description corresponds to the second data flow 7 shown in FIG.

The post-rewrite operation description is subjected to high-level synthesis processing including a data flow analysis unit 8, a state allocation unit 10, and a binding unit 11, so that a logic circuit using a multiplexer circuit 100 as shown in FIG. Is synthesized. Therefore, it is apparent from FIG. 5 that the memory device 300 synthesized by the conventional technique and shown in FIG. 11 does not exist in the logic circuit which is high-level synthesized from the behavioral description of FIG.

When the logic circuit in which the storage element 300 is assigned to the array by the high-level synthesis of the prior art operates, the contents of the array variable are substituted into the address of the corresponding storage element, that is, r [0] in FIG. At least 4 clocks are required to write the array variables r [1] and r [2] in the storage element and read the stored array variables.

On the other hand, in the logic circuit which is high-level synthesized by the behavioral description by the array variable according to the present invention,
As shown in FIG. 5, since variable reading can be performed only by substituting the address corresponding to the virtual name to be read into the index, the variable reading can be performed in a time period of one clock, and comparison with a logic circuit using a storage element Therefore, the operating time can be obviously reduced.

The logic circuit of FIG. 5 can be easily replaced with an equivalent circuit like the logic circuit of FIG. 6, and the circuit scale can be further reduced.

In the case of writing variables, the operation description of FIG. 7 causes the syntax analysis unit 2 and the array variable analysis unit 4 to generate the array variable analysis data 5 shown in FIG. The array variable analysis data 5 shown in FIG. 8 is data including an array name, an address, and a virtual name corresponding to the address, as in FIG.

Next, as shown in FIG. 9, the variable rewriting unit 6 substitutes the input variable i1 into the virtual names r # 0, r # 1, r # 2 corresponding to each index in the description of the switch statement. After the rewriting, that is, the second data flow 7 shown in FIG. 1 is output.

The high-level synthesis process including the data flow analysis unit 8, the state allocation unit 10, and the binding unit 11 is applied to the post-rewriting operation description so that FIG.
Since it is automatically synthesized into the logic circuit using the demultiplexer circuit 200 as described above, the storage element is not assigned to the array variable.

In order to automatically synthesize a logic circuit using the multiplexer circuit 100 shown in FIG. 5 or 6 and the demultiplexer circuit 200 shown in FIG.
Although it is possible to manually describe the behavioral description of FIG. 9 and FIG. 9, the description of FIG. 4 and FIG. 9 is difficult to understand and becomes a long description, and it takes a very long time to complete an algorithm description that operates correctly. Will end up. On the other hand, according to the present invention, only the description of FIG. 2 or FIG. 7 is required, so the description amount is small and the description is easy to understand, so that description errors can be avoided.

[0027]

As described in detail above, according to the present invention,
By reading and writing variables according to the definition of array variables during operation description in a programming language, it is possible to facilitate the logic circuit design, and to reduce the operation time and the circuit scale of the logic circuit after high-level synthesis. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a functional configuration of a high-level synthesis device for a logic circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of an example of an operation description when reading a variable that defines an array variable.

FIG. 3 is array variable analysis data obtained by analyzing the behavioral description in the array variable analysis unit of the present invention.

FIG. 4 is a diagram showing a post-rewriting operation description in which the array variable analysis data is rewritten in the variable rewriting unit of the present invention.

FIG. 5 is a first logic circuit that is high-level synthesized according to the present invention.

FIG. 6 is a second logic circuit that is high-level synthesized according to the present invention.

FIG. 7 is a diagram of an example of an operation description when writing a variable that defines an array variable.

FIG. 8 is array variable analysis data obtained by analyzing the behavioral description in the array variable analysis unit of the present invention.

FIG. 9 is a diagram showing a post-rewriting operation description in which the array variable analysis data is rewritten in the variable rewriting unit of the present invention.

FIG. 10 is a third logic circuit that is high-level synthesized according to the present invention.

FIG. 11 is a diagram showing a logic circuit that is high-level synthesized by a conventional technique with respect to a behavioral description including array variables.

[Explanation of symbols]

1 ... Behavior description, 2 ... Syntax analysis unit, 3 ... First data flow, 4 ... Array variable analysis unit, 5 ... Array variable analysis data, 6
... variable rewriting unit, 7 ... second data flow (post-rewriting operation description), 8 ... data flow analysis unit, 9 ... optimized data flow, 10 ... state assignment unit, 11 ... binding unit, 12 ... logic circuit, 100 … Multiplexer,
200 ... Demultiplexer, 300 ... Storage element

Claims (6)

[Claims] 1. A high-level synthesis device for synthesizing a logic circuit based on a behavioral description, analyzes an array variable in an inputted behavioral description, and assigns a virtual name to each of the array name and its address. An array variable analysis unit for generating array variable analysis data and a variable rewriting unit for generating a post-rewriting operation description from the operation description based on the array variable analysis data, and a logic based on the post-rewriting operation description. A high-level synthesis apparatus for logic circuits, which is characterized by high-level synthesis of circuits. 2. A high-level synthesis method for synthesizing a logic circuit based on a behavioral description, wherein an array variable in an inputted behavioral description is analyzed to obtain an array name and respective virtual names corresponding to respective addresses. A step of generating attached array variable analysis data, a step of rewriting the behavioral description based on the array variable analysis data, and a step of performing high-level synthesis of a logic circuit based on the rewritten behavioral description. High-level synthesis method for logic circuits. 3. A high-level synthesis method for synthesizing a logic circuit including a multiplexer that reads data corresponding to an address of the array variable from an operation description including reading of the array variable. 4. A high-level synthesis method for synthesizing a logic circuit composed of a demultiplexer, which writes data corresponding to an address of an array variable to a behavioral description including writing of an array variable. 5. A high-level synthesis device for synthesizing a logic circuit including a multiplexer for selecting data corresponding to an address of the array variable with respect to a behavioral description including reading of the array variable. 6. A high-level synthesis apparatus for synthesizing an operation description including writing of an array variable with a logic circuit including a demultiplexer that selects a data path corresponding to the address of the array variable.