JP2002359474A - Surface-mounted multilayer circuit board - Google Patents

Surface-mounted multilayer circuit board

Info

Publication number
JP2002359474A
JP2002359474A JP2001163548A JP2001163548A JP2002359474A JP 2002359474 A JP2002359474 A JP 2002359474A JP 2001163548 A JP2001163548 A JP 2001163548A JP 2001163548 A JP2001163548 A JP 2001163548A JP 2002359474 A JP2002359474 A JP 2002359474A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer
multilayer circuit
multilayer substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001163548A
Other languages
Japanese (ja)
Inventor
Yoichi Makino
洋一 牧野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001163548A priority Critical patent/JP2002359474A/en
Publication of JP2002359474A publication Critical patent/JP2002359474A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized surface-mounted multilayer circuit board that can prevent the delamination of insulating layers, is improved in mountability on a mother board, and can be surface-mounted to high density. SOLUTION: On the surface of this multilayer circuit board, prescribed surface wiring layers 4 and circuit components 6 are arranged. On the rear surface of this circuit board which serves as the mounted surface of the board, recessed sections 15 which pass through the substrate 1, except for one uppermost insulation layer, are formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面実装型多層回
路基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type multilayer circuit board.

【0002】[0002]

【従来の技術】表面実装型多層基板は、各種電子部品素
子、半導体素子を搭載する実装基板として、また、各種
回路機能を形成した基板として広く実用されている。例
えば、アルミナなどのセラミックスは耐熱性、耐久性、
熱伝導性などに優れるため、この多層基板の材料として
適しており、高周波回路においては、所定誘電率のセラ
ミック材料からなる基板が使用されていた。
2. Description of the Related Art A surface mounting type multilayer substrate is widely used as a mounting substrate on which various electronic components and semiconductor elements are mounted, and as a substrate on which various circuit functions are formed. For example, ceramics such as alumina have heat resistance, durability,
Since it is excellent in thermal conductivity and the like, it is suitable as a material for this multilayer substrate. In high-frequency circuits, a substrate made of a ceramic material having a predetermined dielectric constant has been used.

【0003】この表面実装型多層回路基板は、製造工程
の簡略化のため、この表面実装型多層回路基板を複数抽
出できる大型多層基板を用いて、これらを分割または切
断していた。
[0003] In order to simplify the manufacturing process, this surface-mounted multilayer circuit board is divided or cut using a large-sized multilayer board from which a plurality of surface-mounted multilayer circuit boards can be extracted.

【0004】具体的な製造工程は、まず、低温焼成ガラ
スセラミック材料などからなるグリーンシートに、表面
配線層、端子電極、内部配線層、ビアホール導体となる
導体ペーストをスクリーン印刷する。次に、複数のグリ
ーンシートを積層・熱圧着により一体化して、大型表面
実装型多層回路基板を形成する。なおこのとき、必要に
応じて金型を用いて分割溝を形成する。次に、未焼成状
の大型表面実装型多層回路基板を焼成する。次に、大型
表面実装型多層回路基板上に回路構成部品を半田、フリ
ップチップ実装、ワイヤボンディングなどで接合・実装
を行う。次に、必要に応じて、回路構成部品を外部環境
から保護するために、回路構成部品が実装された多層基
板の部品実装面全面を樹脂などの封止部材で被覆するこ
とにより、大型表面実装型多層回路基板が得られる。最
後に、上述の分割溝でもって分割処理することにより、
最終製品としての表面実装型多層回路基板が得られる。
なお、分割溝及び分割処理をせずに、大型多層基板をダ
イシングソーなどを用いて切断しても構わない(以下、
分割・切断を含めて、分離という)。
In a specific manufacturing process, first, a conductor paste to be a surface wiring layer, a terminal electrode, an internal wiring layer, and a via hole conductor is screen-printed on a green sheet made of a low-temperature fired glass ceramic material or the like. Next, a plurality of green sheets are integrated by lamination and thermocompression bonding to form a large surface-mounted multilayer circuit board. At this time, if necessary, a mold is used to form a dividing groove. Next, the unfired large-sized surface-mounted multilayer circuit board is fired. Next, circuit components are joined and mounted on a large surface-mount type multilayer circuit board by soldering, flip-chip mounting, wire bonding, or the like. Next, if necessary, in order to protect the circuit components from the external environment, the entire surface of the component mounting surface of the multilayer board on which the circuit components are mounted is covered with a sealing member such as a resin, so that the large surface mounting is performed. A multi-layer circuit board is obtained. Finally, by performing the dividing process with the above-mentioned dividing groove,
A surface-mounted multilayer circuit board as a final product is obtained.
Note that a large multilayer substrate may be cut using a dicing saw or the like without performing the dividing groove and the dividing process (hereinafter, referred to as a dicing saw).
Separation, including division and cutting).

【0005】上記製造方法において、グリーンシートの
積層圧着時、グリーンシート間に空気が巻き込まれる
と、この空気が逃げきれず、焼成時にこの空気がデラミ
ネーションの原因となるという問題点があった。
In the above-mentioned manufacturing method, there is a problem that if air is trapped between the green sheets during the lamination and compression of the green sheets, the air cannot escape and this air causes delamination during firing.

【0006】そこで、図7に示すように、絶縁層1a〜
1eとなるグリーンシートにあらかじめ貫通孔19(1
9a〜19e)を形成しておき、積層時にこの貫通孔1
9a〜19eを介して、グリーンシート間の空気が抜け
出すようにしていた。
[0006] Therefore, as shown in FIG.
The through-hole 19 (1
9a to 19e) are formed in advance, and this through hole 1
The air between the green sheets escapes through 9a to 19e.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、図7に
示すように、多層基板1上に封止部材7を塗布した時、
この封止部材7が貫通孔19に侵入して、多層基板1の
実装面側に回り込んでしまう。その結果、回り込んだ封
止部材7が、多層基板1の実装面側の端子電極5に付着
したり、実装面が凹凸になりマザーボードへの実装が不
能となる問題を有していた。
However, as shown in FIG. 7, when the sealing member 7 is applied on the multilayer substrate 1,
The sealing member 7 penetrates into the through hole 19 and goes around the mounting surface side of the multilayer substrate 1. As a result, there has been a problem that the enclosing sealing member 7 adheres to the terminal electrode 5 on the mounting surface side of the multilayer substrate 1 or the mounting surface becomes uneven, and mounting on the motherboard becomes impossible.

【0008】また、貫通孔19が形成された部分は、表
面実装型多層回路基板10において、デッドスペースと
なるため、表面配線層4や回路構成部品6を実装するに
あたり、小形・高密度実装について大きな障害となって
いた。
Further, since the portion where the through hole 19 is formed becomes a dead space in the surface mount type multilayer circuit board 10, when mounting the surface wiring layer 4 and the circuit component 6, small and high-density mounting is required. It was a major obstacle.

【0009】大型表面実装型多層回路基板10から分割
処理を行う場合、この貫通孔19に封止部材7が従弟さ
れていると分割処理がしにくくなるという問題点があっ
た。
When the dividing process is performed from the large-sized surface-mount type multilayer circuit board 10, if the sealing member 7 is subordinate to the through hole 19, there is a problem that the dividing process becomes difficult.

【0010】本発明は、上述の課題に鑑みて案出された
ものであり、その目的は、絶縁層間のデラミネーション
を防止し、マザーボード上への実装性を向上こせ、さら
に、小形・表面高密度実装が可能な表面実装型多層回路
基板を提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to prevent delamination between insulating layers, improve mountability on a motherboard, and reduce the size and surface height. An object of the present invention is to provide a surface mounting type multilayer circuit board capable of density mounting.

【0011】[0011]

【課題を解決するための手段】本発明の表面実装型多層
回路基板は、複数の絶縁層が積層された多層基板の表面
に、表面配線層及び回路構成部品を配置するとともに、
該表面配線層及び回路構成部品を封止部材で被覆して成
り、且つ前記多層基板の裏面に端子電極を形成した表面
実装型多層基板において、前記多層基板の裏面に、窪み
部が形成しており、該窪み部は最上層の絶縁層を除く各
絶縁層に設けた貫通孔で形成されていることを特徴とす
る表面実装型多層回路基板である。
According to the surface mounting type multilayer circuit board of the present invention, a surface wiring layer and circuit components are arranged on a surface of a multilayer board on which a plurality of insulating layers are laminated.
The surface wiring layer and the circuit component are covered with a sealing member, and a surface mounting type multilayer substrate in which terminal electrodes are formed on the back surface of the multilayer substrate, wherein a recess is formed on the back surface of the multilayer substrate. The recess is formed by a through hole provided in each insulating layer except for the uppermost insulating layer.

【0012】好ましくは、前記窪み部は、前記多層基板
の周縁部に形成されている。
[0012] Preferably, the depression is formed at a peripheral edge of the multilayer substrate.

【0013】なお、ここで窪み部とは、基板の実装面か
ら積層方向に凹になっている形状のことを言い、多層基
板の端面部分においては、窪み部の形状が2分割され、
または角部分においては、窪み部の形状が4分割されて
いる。尚、その窪み部の開口形状は、円形、概略円形
状、多角形状であってもよい。
[0013] Here, the concave portion refers to a shape that is concave in the laminating direction from the mounting surface of the substrate. At the end surface portion of the multilayer substrate, the shape of the concave portion is divided into two parts.
Alternatively, in the corner portion, the shape of the depression is divided into four. The shape of the opening of the depression may be circular, roughly circular, or polygonal.

【0014】[0014]

【発明の実施の形態】以下、本発明の表面実装型多層回
路基板を図面に基づいて説明する。尚、図において、従
来と同じ部位は同一符号を付す。また、各符号は製造工
程上、焼成の前後で区別しないことにする。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a surface mount type multilayer circuit board according to the present invention. In the drawings, the same parts as those in the related art are denoted by the same reference numerals. In addition, each code is not distinguished before and after firing in the manufacturing process.

【0015】図1は、本発明の表面実装型多層回路基板
の断面図である。図2は、図1の多層基板が抽出される
大型多層基板の部分断面図である。図3は、図2の大型
多層基板の実装面に形成された窪み部を示す平面図であ
る。
FIG. 1 is a sectional view of a surface mount type multilayer circuit board according to the present invention. FIG. 2 is a partial cross-sectional view of a large multilayer substrate from which the multilayer substrate of FIG. 1 is extracted. FIG. 3 is a plan view showing a depression formed on the mounting surface of the large-sized multilayer substrate of FIG.

【0016】図において、11は表面実装型多層回路基
板、1は多層基板、1a〜1eは絶縁層、2は多層基板
1の内部に形成された内部配線層、3は多層基板1の内
部に形成されたビアホール導体、4は多層基板1の表面
に形成された表面配線層、5は多層基板1の実装面側に
形成された端子電極、6は表面配線層4上に搭載された
回路構成部品、7は回路構成部品を被覆している封止部
材である。
In the drawing, reference numeral 11 denotes a surface-mounted multilayer circuit board, 1 denotes a multilayer board, 1a to 1e denote insulating layers, 2 denotes an internal wiring layer formed inside the multilayer board 1, and 3 denotes an internal wiring layer. The formed via-hole conductor, 4 is a surface wiring layer formed on the surface of the multilayer substrate 1, 5 is a terminal electrode formed on the mounting surface side of the multilayer substrate 1, and 6 is a circuit configuration mounted on the surface wiring layer 4. The component 7 is a sealing member that covers the circuit component.

【0017】また、10は大型表面実装型多層回路基
板、8は表面実装型多層回路基板11を各多層基板1に
分離するためのスナップライン(分割溝)や、切断予定
線などの分離線である。15は窪み部である。
Reference numeral 10 denotes a large-sized surface-mount type multilayer circuit board; 8 denotes a separation line such as a snap line (division groove) for separating the surface-mount type multilayer circuit board 11 into each multilayer substrate 1; is there. Reference numeral 15 denotes a depression.

【0018】多層基板1は、1層あたり例えば、50〜
300μm程度の厚みを有する絶縁層1a〜1eが積層
して構成されている。絶縁層1a〜1eは、セラミック
材料、低温焼成化が可能なガラス−セラミック材料など
からなる。例えばガラス−セラミック材料では、セラミ
ック材料として、例えば、Al23、BaO−TiO 2
系、CaO−TiO2系、MgO−TiO2系などが、ま
た、低温焼成化が可能な酸化物としては、例えば、Bi
VO4、CuO、Li2O、B23などが選ばれる。
The multilayer substrate 1 has, for example, 50 to
Insulating layers 1a to 1e having a thickness of about 300 μm are laminated
It is configured. The insulating layers 1a to 1e are made of ceramic.
Materials, glass-ceramic materials that can be fired at low temperatures, etc.
Consists of For example, in glass-ceramic materials, ceramic
As a material for the lock, for example, AlTwoOThree, BaO-TiO Two
System, CaO-TiOTwoSystem, MgO-TiOTwoSystem
Examples of oxides that can be fired at low temperatures include, for example, Bi.
VOFour, CuO, LiTwoO, BTwoOThreeAnd so on.

【0019】絶縁層1a〜1eの各層の厚み方向に貫く
ビアホール導体3が形成されている。また、絶縁層1a
〜1eの層間には、所定配線網の他に、容量を形成する
容量電極、インダクタンス成分を形成する導体、ストリ
ップ線路を形成する導体などを含む内部配線層2が形成
されている。また、絶縁層1aの表面には、回路構成部
品6を搭載するための電極パッドを含む表面配線層4が
形成されている。さらに、絶縁層1eの裏面(表面実装
型多層回路基板の実装面)には、多層基板1をマザーボ
ードに接続するための端子電極5やグランド電位となる
裏面導体層が形成されている。
A via-hole conductor 3 is formed penetrating in the thickness direction of each of the insulating layers 1a to 1e. Also, the insulating layer 1a
In addition to the predetermined wiring network, an internal wiring layer 2 including a capacitor electrode forming a capacitor, a conductor forming an inductance component, a conductor forming a strip line, and the like is formed between the layers 1 to 1e. On the surface of the insulating layer 1a, a surface wiring layer 4 including an electrode pad for mounting the circuit component 6 is formed. Further, on the back surface of the insulating layer 1e (the mounting surface of the surface mount type multilayer circuit board), a terminal electrode 5 for connecting the multilayer substrate 1 to a motherboard and a back surface conductor layer serving as a ground potential are formed.

【0020】そして、表面配線層4、ビアホール導体
3、内部配線層2、端子電極5は、所定回路網を構成す
べく、互いに接続されている。また、これらの導体は、
Ag系(Ag単体又はAg−Pd、Ag−PtなどのA
g合金)や、Cu系(Cu単体又はCu合金)を主成分
とする導体膜(導体)が用いられる。
The surface wiring layer 4, via-hole conductor 3, internal wiring layer 2, and terminal electrode 5 are connected to each other to form a predetermined circuit network. Also, these conductors
Ag-based (Ag alone or Ag-Pd, Ag-Pt, etc.
g alloy) or a conductive film (conductor) mainly composed of Cu (Cu simple substance or Cu alloy).

【0021】回路構成部品6は、積層セラミックコンデ
ンサ、チップ抵抗器、SAW素子、チップ状インダクタ
ンス素子、半導体素子など各種電子部品が例示され、半
田、フリップチップ実装、ワイヤボンディングなどによ
り、表面配線層4上に実装される。
The circuit component 6 is exemplified by various electronic components such as a multilayer ceramic capacitor, a chip resistor, a SAW element, a chip-shaped inductance element, and a semiconductor element. The surface wiring layer 4 is formed by soldering, flip-chip mounting, wire bonding, or the like. Implemented above.

【0022】回路構成部品6の表面には、外部環境から
保護するために、多層基板1表面の全面を覆うように封
止部材7が被覆されている。封止部材7は、エポキシ系
樹脂、フェノール系樹脂、シリコン系樹脂などの熱硬化
性樹脂、紫外線硬化樹脂などが例示できる。このよう
に、多層基板1に回路構成部品6、封止部材7を形成し
て、表面実装型多層回路基板11が構成される。
The surface of the circuit component 6 is covered with a sealing member 7 so as to cover the entire surface of the multilayer substrate 1 in order to protect it from the external environment. Examples of the sealing member 7 include a thermosetting resin such as an epoxy resin, a phenol resin, and a silicon resin, and an ultraviolet curing resin. In this way, the circuit component 6 and the sealing member 7 are formed on the multilayer board 1 to form the surface-mounted multilayer circuit board 11.

【0023】本発明の表面実装型多層回路基板11の特
徴的なことは、多層基板1の実装面に窪み部15を形成
されている。
A feature of the surface mount type multilayer circuit board 11 of the present invention is that a recess 15 is formed on the mounting surface of the multilayer board 1.

【0024】具体的な窪み部15の形成される位置は、
例えば、図1に示す大型表面実装型多層回路基板10で
示すように、隣接しあう多層基板1の境界部分に跨がっ
て形成されている。即ち、表面実装型多層回路基板11
においては、端面、また角部に形成されている。表面実
装型多層回路基板11が複数抽出できる大型表面実装型
多層回路基板10においては、分離線に跨がるように窪
み部15が形成されている。その結果、多層基板1の実
装面側の周縁部に位置さている。窪み部15となる貫通
孔15b〜15eは、絶縁層1b〜1eのみだけであ
り、絶縁層1aは、貫通孔15b〜15eを閉塞して、
凹部状の窪み部15を形成している。この絶縁層1b〜
1eの貫通孔15b〜15eは、積層時互いに重なりあ
うように、同一箇所に形成されている。
The specific position where the concave portion 15 is formed is as follows.
For example, as shown by a large-sized surface-mount type multilayer circuit board 10 shown in FIG. 1, it is formed so as to straddle a boundary portion between adjacent multilayer boards 1. That is, the surface mount type multilayer circuit board 11
Is formed at the end face and at the corners. In the large-sized surface-mounted multilayer circuit board 10 from which a plurality of surface-mounted multilayer circuit boards 11 can be extracted, a recess 15 is formed so as to straddle a separation line. As a result, it is located at the peripheral portion on the mounting surface side of the multilayer substrate 1. The through holes 15b to 15e serving as the depressions 15 are only the insulating layers 1b to 1e, and the insulating layer 1a closes the through holes 15b to 15e.
A concave portion 15 having a concave shape is formed. This insulating layer 1b ~
The through-holes 15b to 15e of 1e are formed at the same location so as to overlap each other during lamination.

【0025】また、表面実装型多層回路基板11の表面
には、表面配線層4が、さらに、表面配線層4上に回路
構成部品6が実装され、これら表面配線層4及び回路構
成部品6を覆うように、多層基板1の全面には封止部材
7が被覆されている。
A surface wiring layer 4 is mounted on the surface of the surface mount type multilayer circuit board 11, and a circuit component 6 is mounted on the surface wiring layer 4. The surface wiring layer 4 and the circuit component 6 are mounted on the surface wiring layer 4. The sealing member 7 is coated on the entire surface of the multilayer substrate 1 so as to cover it.

【0026】この窪み部15は、図3に示すように、大
型表面実装型多層回路基板10の実装面側においては、
分離線8の交点にあたる部分に形成されている。
As shown in FIG. 3, the recess 15 is formed on the mounting surface side of the large-sized surface-mount type multilayer circuit board 10.
It is formed at a portion corresponding to the intersection of the separation lines 8.

【0027】次に本発明における表面実装型多層回路基
板11の製造方法を説明する。
Next, a method of manufacturing the surface mount type multilayer circuit board 11 according to the present invention will be described.

【0028】まず、絶縁層1a〜1eは、例えばCaO
−Al23−SiO2−B23系のガラス粉末とアルミ
ナ粉末とを混合したガラス−セラミック材料からなる。
そして、絶縁層1a〜1eとなるグリーンシートは、こ
のようなガラス−セラミック材料のスラリーをドクター
ブレード法によって厚み0.2mmのテープ成形し、さ
らに所定大きさに切断されてシート状に形成することに
より、グリーンシートなる。
First, the insulating layers 1a to 1e are made of, for example, CaO
-Al 2 O 3 -SiO 2 -B 2 O 3 based glass powder and alumina powder and glass were mixed for - a ceramic material.
The green sheets to be the insulating layers 1a to 1e are formed by forming a slurry of such a glass-ceramic material into a tape having a thickness of 0.2 mm by a doctor blade method, and further cutting into a predetermined size to form a sheet. As a result, a green sheet is obtained.

【0029】このようなグリーンシートは、各絶縁層1
a〜1eのビアホール導体3に応じて打ち抜きやパンチ
ングマシーンなどを用いて、複数の所定位置に、例えば
0.2mmφのビアホール用貫通孔を形成する。また、
各グリーンシートの貫通孔には、Ag、Ag−Pd、A
u、Cuなどの導体ペーストを充填し、同時に内部配線
層2となる導体や表面配線層4、端子電極5となる導体
膜をスクリーン印刷により形成する。
Such a green sheet is formed on each of the insulating layers 1
Via holes for punching, for example, 0.2 mmφ are formed at a plurality of predetermined positions using a punching machine, a punching machine, or the like according to the via hole conductors 3a to 1e. Also,
Ag, Ag-Pd, A
A conductor paste such as u, Cu or the like is filled, and at the same time, a conductor serving as the internal wiring layer 2, a surface wiring layer 4, and a conductor film serving as the terminal electrode 5 are formed by screen printing.

【0030】このとき、絶縁層1a〜1dとなるグリー
ンシートには、積層方向に重なる同一箇所に貫通孔15
b〜15eを形成する。そして、最上層に位置する絶縁
層1aとなるグリーンシートには窪み部15となる貫通
孔を形成しない。
At this time, the green sheets serving as the insulating layers 1a to 1d are provided with the through holes 15 at the same positions overlapping in the laminating direction.
b to 15e are formed. Then, no through hole serving as the recess 15 is formed in the green sheet serving as the insulating layer 1a located at the uppermost layer.

【0031】そして、このような絶縁層1a〜1eとな
るグリーンシートを積層し、例えば80〜150℃、5
00〜2500N/cm2の条件で熱圧着して一体化す
る。これにより未焼成状態の大型多層基板となる。
Then, green sheets to be used as the insulating layers 1a to 1e are laminated, for example, at 80 to 150.degree.
It is integrated by thermocompression bonding under the condition of 00 to 2500 N / cm 2 . As a result, a large multilayer substrate in an unfired state is obtained.

【0032】次に、必要に応じて、図3に示すように、
未焼成状態の大型多層基板の表裏両面に分離線8とし
て、分割溝を成形する。
Next, if necessary, as shown in FIG.
Separation grooves are formed as separation lines 8 on both the front and back surfaces of the unfired large multilayer substrate.

【0033】次に、未焼成状態の大型多層基板を、電気
式連続ベルト炉を使用して、例えば、空気中で900
℃、20分の保持条件で焼成する。なお、導体ペースト
がNi、Cuの場合は還元または中性雰囲気で焼成す
る。
Next, a large-sized multilayer substrate in an unfired state is placed in an air-type continuous belt furnace, for example, in air at 900.degree.
It is baked at 20 ° C. for 20 minutes. When the conductive paste is Ni or Cu, the paste is reduced or fired in a neutral atmosphere.

【0034】次に、電気テストが行われ、通電状態が検
査され、合格した大型多層基板については、表面処理が
行われる。例えば、表面配線層4に厚膜の抵抗膜を焼き
付けたり、絶縁保護膜を被覆したりする。
Next, an electrical test is performed to check the energization state, and the surface treatment is performed on the large multi-layer substrate that has passed. For example, a thick resistive film is baked on the surface wiring layer 4 or an insulating protective film is coated.

【0035】次に、大型多層基板上に回路構成部品6を
半田、フリップチップ実装、ワイヤボンディングなどで
接合・実装を行う。
Next, the circuit components 6 are joined and mounted on the large-sized multilayer board by soldering, flip-chip mounting, wire bonding, or the like.

【0036】次に、大型多層基板の表面全面に、樹脂な
どの封止部材7で被覆する。なお、封止の方法は、液状
封止材を用いて注型法により封止する方法、あるいは常
温では固形の封止材を用いて、トランスファーモールド
法により封止する方式を用いることができる。これによ
り、大型表面実装型多層回路基板10となる。
Next, the entire surface of the large multilayer substrate is covered with a sealing member 7 such as a resin. Note that as a sealing method, a method of sealing by a casting method using a liquid sealing material, or a method of sealing by a transfer molding method using a solid sealing material at normal temperature can be used. As a result, a large surface-mounted multilayer circuit board 10 is obtained.

【0037】このようにして得られた大型表面実装型多
層回路基板10を分離線8に沿って、分割処理すること
により、図1に示す表面実装型多層回路基板11が形成
される。尚、分割処理以外に、例えば切断処理により大
型表面実装型多層回路基板10から表面実装型多層回路
基板11に分離しても構わない。
The large surface mounted multilayer circuit board 10 thus obtained is divided along the separation line 8 to form the surface mounted multilayer circuit board 11 shown in FIG. Note that, other than the division processing, the large-sized surface-mounted multilayer circuit board 10 may be separated into the surface-mounted multilayer circuit board 11 by, for example, cutting processing.

【0038】このようにして製造された本発明の表面実
装型多層回路基板11によれば、多層基板1の裏面であ
る実装面には、絶縁層の表面側の1層、即ち、絶縁層1
aが閉塞する窪み部15が形成されている。すなわち、
この窪み部15は、絶縁層1b〜1eに形成した貫通孔
15b〜15eにより形成されている。これにより、上
述の製造方法において、絶縁層1aとなるグリーンシー
トと絶縁層1bとなるグリーンシートとの間、同じく絶
縁層1bと絶縁層1cとの間、絶縁層1cと絶縁層1d
との間、絶縁層1dと絶縁層1eとの間に巻き込まれる
空気は、熱圧着時に、この貫通孔15b〜15eからな
る窪み部15から、多層基板1の実装面側から抜け出す
ことにより、絶縁層1a〜1e間に発生するデラミネー
ションを有効に防止できる。
According to the surface-mounted multilayer circuit board 11 of the present invention manufactured as described above, the mounting surface, which is the back surface of the multilayer board 1, has one layer on the front side of the insulating layer,
The recessed portion 15 for closing a is formed. That is,
The depression 15 is formed by through holes 15b to 15e formed in the insulating layers 1b to 1e. Thereby, in the above-described manufacturing method, between the green sheet serving as the insulating layer 1a and the green sheet serving as the insulating layer 1b, similarly between the insulating layer 1b and the insulating layer 1c, and between the insulating layer 1c and the insulating layer 1d.
During the thermocompression bonding, the air trapped between the insulating layer 1d and the insulating layer 1e escapes from the mounting surface side of the multilayer substrate 1 through the recessed portion 15 formed by the through holes 15b to 15e. Delamination occurring between the layers 1a to 1e can be effectively prevented.

【0039】また、絶縁層1aには、窪み部15が形成
されておらず、従来のように貫通孔を形成していないた
め、多層基板1の表面側の封止部材7が、実装面側に到
達することが一切ない。このため、多層基板1の実装面
側の電極パッドに付着したり、実装面が凹凸になり、そ
の結果、マザーボードへの実装が不能となるといった問
題は一切ない。
Since the insulating layer 1a does not have the recessed portion 15 and does not have a through hole as in the prior art, the sealing member 7 on the front surface side of the multilayer substrate 1 is mounted on the mounting surface side. Never reach. For this reason, there is no problem that it adheres to the electrode pad on the mounting surface side of the multilayer substrate 1 or the mounting surface becomes uneven, and as a result, mounting on the motherboard becomes impossible.

【0040】また、絶縁層1aには、上述の窪み部15
を形成する貫通孔が形成されておらず、絶縁層1aの表
面全体が、表面実装型多層回路基板11の表面となるた
め、表面配線層4の形成に制約事項がなくなり、また、
回路構成部品6の高密度実装もかのとなる。即ち、小形
で、且つ高密度実装化できる表面実装型多層回路基板1
1となる。
The insulating layer 1a has the recess 15
Is not formed, and the entire surface of the insulating layer 1a becomes the surface of the surface mount type multilayer circuit board 11, so that there are no restrictions on the formation of the surface wiring layer 4, and
High-density mounting of the circuit component 6 is also possible. That is, a surface-mounted multilayer circuit board 1 that is small and can be mounted at high density.
It becomes 1.

【0041】また、窪み部15は、多層基板1の周縁部
に形成されているため、多層基板1の内部配線層2にお
いてデッドスペースを少なくなる。また、大型表面実装
型多層回路基板10における窪み部15内に封止部材7
が充填されていないため、分割を行いやすくなるという
効果がある。
Further, since the recess 15 is formed at the peripheral edge of the multilayer substrate 1, the dead space in the internal wiring layer 2 of the multilayer substrate 1 is reduced. The sealing member 7 is provided in the recess 15 of the large-sized surface-mount type multilayer circuit board 10.
Is not filled, there is an effect that division becomes easy.

【0042】窪み部15が、例えば開口形状が円形の場
合、直径は小さいと積層圧着時につぶれてしまうため、
焼成後に0.3mm以上、好ましくは0.4mm以上で
あることが望ましい。窪み部15の直径の上限は、特に
制限はないが、大型多層基板10の内部配線層2の高密
度実装のために、焼成後に4mm以下であることが望ま
しい。
When the recess 15 has a circular opening, for example, if the diameter is small, it will be crushed during lamination and compression.
It is desirable that the thickness after firing is 0.3 mm or more, preferably 0.4 mm or more. The upper limit of the diameter of the recess 15 is not particularly limited, but is preferably 4 mm or less after firing for high-density mounting of the internal wiring layer 2 of the large multilayer substrate 10.

【0043】図4は、本発明の他の実施例の多層基板の
断面図である。このように、必要に応じて、窪み部15
は多層基板1の周縁部から離した基板の内側に位置に形
成しても良い。
FIG. 4 is a sectional view of a multilayer substrate according to another embodiment of the present invention. Thus, if necessary, the depression 15
May be formed at a position inside the substrate away from the peripheral portion of the multilayer substrate 1.

【0044】図5は、本発明の窪み部15の形成位置を
示す平面図である。図5(a)では、窪み部15を各多
層基板形成領域の4つの角部、すなわち分離線8の交差
部分に形成されている。図5(b)では、窪み部15を
各多層基板形成領域の境界線部、すなわち分離線8上に
形成されている。図5(c)では、窪み部15を分離線
8から離れた位置に形成されている。ここで、図5
(a)、(b)の断面図は図1のようになり、図5
(c)の断面図は、図4のようになる。
FIG. 5 is a plan view showing the formation position of the depression 15 of the present invention. In FIG. 5A, the depressions 15 are formed at the four corners of each multilayer substrate formation region, that is, at the intersections of the separation lines 8. In FIG. 5B, the depressions 15 are formed on the boundaries between the multilayer substrate formation regions, that is, on the separation lines 8. In FIG. 5C, the depression 15 is formed at a position away from the separation line 8. Here, FIG.
The sectional views of FIGS. 5A and 5B are as shown in FIG.
FIG. 4 is a sectional view of FIG.

【0045】また、図6に示すように、窪み部15の真
上の絶縁層1aに、熱放出を行うなサーマルビアホール
13を形成し、窪み部15上の絶縁層1aの領域にIC
チップ16を実装している。このようにすれば、ICチ
ップ16が発生する熱がサーマルビアホール13を通っ
て実装面側の窪み部15に放出され、多層基板1を広い
領域に熱影響を少なくすることができる。このことによ
り、窪み部15の形成部分を有効活用できるとともに、
サーマルビアホール13の長さが短くて済むため、放熱
性も向上する。
As shown in FIG. 6, a thermal via hole 13 for releasing heat is formed in the insulating layer 1a immediately above the depression 15, and an IC is formed in the region of the insulating layer 1a on the depression 15.
The chip 16 is mounted. In this way, the heat generated by the IC chip 16 is released to the recessed portion 15 on the mounting surface side through the thermal via hole 13, so that the thermal effect of the multilayer substrate 1 over a wide area can be reduced. Thereby, while the formation part of the recessed part 15 can be utilized effectively,
Since the length of the thermal via hole 13 can be reduced, the heat dissipation is also improved.

【0046】上述の実施例では、ガラス-セラミック材
料の多層基板を例にした表面実装型多層回路基板で説明
したが、ガラスエポキシ材、変成ポリイミド材などの有
機材料の多層基板であってもよい。
In the above-described embodiment, the surface mount type multi-layer circuit board has been described as an example of a multi-layer board made of a glass-ceramic material. However, a multi-layer board made of an organic material such as a glass epoxy material or a modified polyimide material may be used. .

【0047】また、これらの窪み部15の内壁面に導体
膜に形成して、例えば、多層基板1の内部配線層2や端
子電極5と電気的に接続するようにしても構わない。
Further, a conductive film may be formed on the inner wall surfaces of these recesses 15 so as to be electrically connected to, for example, the internal wiring layer 2 and the terminal electrodes 5 of the multilayer substrate 1.

【0048】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良などは何ら差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

【0049】[0049]

【発明の効果】本発明の表面実装型多層回路基板によれ
ば、多層基板の実装面には、絶縁層の表面側の1層の絶
縁層を除いて貫く貫通孔による窪み部が形成されてい
る。すなわち、この窪み部によって、製造工程中、絶縁
層間に巻き込まれる空気を、多層基板の領域から実装面
外部に逃がすることができ、その結果、絶縁層間のデラ
ミネーションの少ない表面実装型多層回路基板となる。
According to the surface mounting type multilayer circuit board of the present invention, the mounting surface of the multilayer board is formed with a recess formed by a through hole excluding one insulating layer on the surface side of the insulating layer. I have. That is, the recess allows the air trapped between the insulating layers to escape from the region of the multilayer substrate to the outside of the mounting surface during the manufacturing process, and as a result, the surface mounting type multilayer circuit with less delamination between the insulating layers. It becomes a substrate.

【0050】また、最上層の絶縁層には、この窪み部を
構成する貫通孔が形成されていないため、多層基板の表
面におけるデッドスペースがなくなり、小形化、高密実
装が可能となる。
Further, since the uppermost insulating layer is not provided with a through-hole forming the depression, there is no dead space on the surface of the multilayer substrate, and the device can be reduced in size and mounted with high density.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の表面実装型多層回路基板の断面図であ
る。
FIG. 1 is a sectional view of a surface mount type multilayer circuit board according to the present invention.

【図2】図1の表面実装型多層回路基板が抽出される大
型表面実装型多層回路基板の断面図である。
FIG. 2 is a cross-sectional view of a large-sized surface-mounted multilayer circuit board from which the surface-mounted multilayer circuit board of FIG. 1 is extracted.

【図3】図2の大型表面実装型多層回路基板の実装面側
の平面図である。
FIG. 3 is a plan view of the mounting surface side of the large-sized surface-mount type multilayer circuit board of FIG. 2;

【図4】本発明の表面実装型多層回路基板の他の実施例
の断面図である。
FIG. 4 is a sectional view of another embodiment of the surface mount type multilayer circuit board of the present invention.

【図5】本発明の大型表面実装型多層回路基板における
窪み部の形成位置を示す平面図である。
FIG. 5 is a plan view showing a formation position of a concave portion in the large-sized surface mounting type multilayer circuit board of the present invention.

【図6】本発明の表面実装型多層回路基板の他の実施例
であり、窪み部部分の断面図である。
FIG. 6 is a cross-sectional view of a recessed portion according to another embodiment of the surface mount type multilayer circuit board of the present invention.

【図7】従来の大型表面実装型多層回路基板の断面図で
ある。
FIG. 7 is a cross-sectional view of a conventional large-sized surface-mount type multilayer circuit board.

【符号の説明】[Explanation of symbols]

1 多層基板 15 窪み部 10 大型表面実装型多層回路基板 11 表面実装型多層回路基板 1a〜1e 絶縁層 2 内部配線層 3 ビアホール導体 4 表面配線層 5 端子電極 6 回路構成部品 7 封止部材 8 分離線 15b〜15e 窪み部を構成する貫通孔 DESCRIPTION OF SYMBOLS 1 Multilayer board 15 Depression 10 Large surface mount type multilayer circuit board 11 Surface mount type multilayer circuit board 1a-1e Insulating layer 2 Internal wiring layer 3 Via hole conductor 4 Surface wiring layer 5 Terminal electrode 6 Circuit component 7 Sealing member 8 minutes Wires 15b to 15e Through-holes forming recesses

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の絶縁層が積層された多層基板の表
面に、表面配線層及び回路構成部品を配置するととも
に、該表面配線層及び回路構成部品を封止部材で被覆し
て成り、且つ前記多層基板の裏面に端子電極を形成した
表面実装型多層基板において、 前記多層基板の裏面に、窪み部が形成しており、該窪み
部は最上層の絶縁層を除く各絶縁層に設けた貫通孔で形
成されていることを特徴とする表面実装型多層回路基
板。
1. A surface wiring layer and a circuit component are arranged on a surface of a multilayer substrate on which a plurality of insulating layers are stacked, and the surface wiring layer and the circuit component are covered with a sealing member. In the surface-mount type multilayer substrate in which terminal electrodes are formed on the rear surface of the multilayer substrate, a depression is formed on the rear surface of the multilayer substrate, and the depression is provided on each of the insulating layers except the uppermost insulating layer. A surface mount type multilayer circuit board characterized by being formed with a through hole.
【請求項2】 前記窪み部は、前記多層基板の周縁部に
形成されていることを特徴とする請求項1記載の表面実
装型多層回路基板。
2. The surface-mounted multilayer circuit board according to claim 1, wherein the recess is formed at a peripheral edge of the multilayer board.
JP2001163548A 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board Pending JP2002359474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001163548A JP2002359474A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001163548A JP2002359474A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Publications (1)

Publication Number Publication Date
JP2002359474A true JP2002359474A (en) 2002-12-13

Family

ID=19006495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001163548A Pending JP2002359474A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Country Status (1)

Country Link
JP (1) JP2002359474A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041242A (en) * 2004-07-28 2006-02-09 Kyocera Corp Ceramic wiring board
JPWO2005071745A1 (en) * 2004-01-27 2007-07-26 株式会社村田製作所 Multilayer electronic component and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005071745A1 (en) * 2004-01-27 2007-07-26 株式会社村田製作所 Multilayer electronic component and manufacturing method thereof
JP2006041242A (en) * 2004-07-28 2006-02-09 Kyocera Corp Ceramic wiring board
JP4535801B2 (en) * 2004-07-28 2010-09-01 京セラ株式会社 Ceramic wiring board

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