JP2002311905A - Liquid crystal display device and image display applied equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve display quality by suppressing lateral stripes generated on a display part in the case of changing over a display mode of a liquid crystal display panel with split screens. SOLUTION: A liquid crystal display device is constituted of a liquid crystal display panel 5A provided with a source driver and a gate driver, an image display signal control circuit 11, a timing signal oscillation circuit 12A, a partial display control circuit 19 for controlling the timing signal oscillation, and a change-over circuit 17 for sending a display mode signal to the partial display control circuit 19. When driving a non-display part in the case of changing over the display mode in the dual image display, the timing for controlling the output current capability of the source driver is delayed by controlling the image display signal control circuit and the timing signal oscillation circuit, and an operation start point of a counter voltage control signal VCC is also delayed. In such a manner, it is possible to eliminate generation of the lateral stripes on the display part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying information used in a notebook type personal computer or a small information terminal and for displaying an image on a television monitor and the like and an image display application device using the same. .

[0002]

2. Description of the Related Art In recent years, as information terminals such as personal computers and portable telephones and video display monitors, devices equipped with a liquid crystal display panel having a light, thin and small size are increasing. The driving of the liquid crystal display panel will be briefly described.

FIG. 5 shows a configuration diagram of this conventional active matrix type liquid crystal display panel. Each display pixel 1 of the liquid crystal display panel is formed by elements surrounded by a broken line composed of one thin film transistor (hereinafter abbreviated as TFT) 2, a liquid crystal display element 3 and a storage capacitor 4. A matrix-type liquid crystal display panel 5 is configured. The image signal electrode lines (S1 to Sm) 6 are electrode lines for supplying a voltage corresponding to the display data signal to the pixels, and the scanning signal electrode lines (X1 to Xn) 7 are for selecting scanning signals for performing line sequential scanning. This is the electrode wire to be supplied. TF
T2 is a switching element controlled by a selection scanning signal from the scanning signal electrode line 7, the liquid crystal display element 3 is a display material having a pixel electrode, and the storage capacitor 4 reduces the image voltage charged in the liquid crystal display element 3. It is for suppressing. Further, a counter electrode 8 for supplying a reference voltage to the liquid crystal display element 3 with the liquid crystal layer of the display panel interposed therebetween is formed. The source driver 9 is a driver that supplies an image signal voltage to each image signal electrode line 6, and the gate driver 10 is a driver that supplies a selection scanning signal for performing line sequential scanning to each scanning signal electrode line 7. A timing control signal for performing timing control and an image display signal are input to the logic circuit of the source driver 9. Gate driver 1
Similarly, a timing control signal for performing timing control is input to the logic circuit 0.

The image signal electrode lines 6 and the scanning signal electrode lines 7 are arranged in a matrix. On the other hand, the source terminal of the TFT 2 is connected to the image signal electrode line 6, the gate terminal is connected to the scanning signal electrode line 7, and the drain terminal is connected to the pixel electrode of the liquid crystal display element 3 and one electrode of the storage capacitor 4. Storage capacity 4
The other electrode is commonly connected to the counter electrode 8. The opposing electrode 8 is supplied with an opposing signal voltage Vcom. The counter signal voltage Vcom uses a DC voltage or a voltage whose polarity is inverted every horizontal synchronization period (1H) depending on the type of driving method of the image signal voltage from the source driver 9.

In order to display an image, an image signal voltage corresponding to a display data signal is supplied from a source driver 9 to a source terminal (S) of each TFT 2 via each image signal electrode line 6 and is supplied to the source terminal 9. Synchronously, a selected scanning signal is supplied to the gate terminal (G) of each TFT 2 via the scanning signal electrode line 7 selected by the gate driver 10. This allows
The TFTs 2 on the selected scanning signal electrode line are simultaneously turned on, and the image signal voltage corresponding to the display data signal supplied from the drain terminal (D) and the counter signal voltage Vcom supplied to the counter electrode 8. The potential difference between the liquid crystal display element 3 and each storage capacitor 4 is the image display voltage of the final image information.
Is accumulated in This voltage is maintained for one field period during which the next information is written, even after the TFT 2 is turned off. The liquid crystal display element 3 changes the twist angle of liquid crystal molecules corresponding to the amount of accumulated voltage, thereby controlling the amount of transmission of light that has been given directionality by a polarizing plate, thereby providing a high-contrast, high-quality image. Can be displayed.

The liquid crystal display device includes a liquid crystal display panel and a driving circuit for driving the liquid crystal display panel, and this is shown in a block circuit of FIG. Here, a case will be described in which a two-screen mode display is divided into two in the vertical direction. In the figure, an image display signal control circuit 11 is a liquid crystal display panel 5
A timing signal generating circuit 12 for supplying a signal for controlling a drive timing to a logic circuit of the source driver 9 and a gate driver 10 of the liquid crystal display panel 5; The display signal source 13 is a signal source necessary for driving the liquid crystal display panel 5. Further, the liquid crystal display device includes a power supply 14 for supplying power to each unit, a voltage conversion circuit 15 for converting the power supply 14 to a required voltage level, and a power supply switch circuit 1 for controlling on / off of an output voltage supply from the voltage conversion circuit 15.
6, a switching circuit 17 for switching the display mode in the two-screen display control, and an opposing signal voltage generating circuit 18 for supplying an opposing signal voltage to the opposing signal electrode are provided.
The opposite signal voltage may be either a voltage that is inverted every horizontal synchronization period or a DC voltage. Here, it is assumed that the opposite signal voltage is inverted every horizontal synchronization period.

A signal from the liquid crystal display signal source 13 is supplied to an image display signal control circuit 11 and a timing signal generation circuit 12, and from each of them, an image signal voltage and a timing control signal necessary for the display operation of the liquid crystal display panel 5 are generated. Can be Various voltages required for display driving are supplied to the liquid crystal display panel 5 from a voltage conversion circuit 15, an image signal voltage is supplied from an image display signal control circuit 11 to a source driver 9, a timing signal generation circuit 12 is supplied with a source driver 9 and a gate driver 10. Is supplied with a timing control signal. Normally, the voltage conversion circuit 15 is driven by the ON control of the power switch circuit 16,
The display of the liquid crystal display panel 5 is performed by supplying a voltage to each control circuit and the liquid crystal display panel. The display operation on the liquid crystal display panel 5 is terminated by stopping the voltage conversion circuit 15 by turning off the power switch circuit 16 and stopping the voltage supply.

The two-screen display is a display method in which the liquid crystal display panel 5 is divided into a display section A and a display section B in the vertical scanning direction as shown in FIG. Taking mobile phone display as an example,
The display unit A is a partial display unit for displaying simple information such as character symbols and reception status display symbols, and the display unit B is a detailed information display as a main display or an image display unit such as a TV phone. As a display method, only the display section A is displayed when displaying general information in a standby state or the like, and the display section A is displayed when displaying general information.
And the display section B are displayed. The display mode changeover switch circuit 17 is a circuit for generating a control signal for switching the display state, and is either a partial display mode for the display section A alone or a full screen display mode for both the display sections A and B. This is for selecting a display mode. In particular, since low power consumption is emphasized in a portable device, it is preferable that the display unit B be in the non-display state in the partial display mode so that the driving power is reduced as much as possible. Therefore, for example, by stopping the gate selection scanning signal voltage supplied from the gate driver 10 and keeping the TFT 2 in the off state, the liquid crystal display element 3 is not charged with the image signal voltage, and the display unit B is reset. Make it invisible.

FIG. 8 is a timing chart of the display mode switching control. When the partial display mode change-over switch circuit 17 at time t ₁ in the figure, the display switching signal V
M becomes high (Hi), and the image display signal control circuit 11,
It is applied to the timing signal generation circuit 12. The image display signal control circuit 11 changes the image display signal VS to only a partial display signal corresponding to the period of the display section A from the timing synchronized with the vertical synchronization signal VD. The timing signal generation circuit 12 changes the gate selection signal voltage from the gate driver 10 to low (Lo) except for the period during which partial display is performed by the gate selection stop signal GSC and changes the gate selection signal voltage normally supplied to the gate terminal of the TFT 2. I'm stopping. In the partial display mode, the supply of the gate selection signal voltage from the gate driver 10 to the display unit B is stopped, and the TFT 2 is always turned off to charge the liquid crystal display element 3 with the image signal voltage. In this case, the power consumption can be reduced by non-display of the display unit B and by stopping the line-sequential scanning drive during this period. Note that the image display signal V for the display section B
S is a regular signal VS1 for displaying information or displaying an image in the full screen display period, but may be any signal VS2 not particularly limited in the non-display period in the partial display mode.

[0010]

In a case where a part of the control operation is stopped for the non-display period other than the partial display period and the low-power driving is performed, the display quality is reduced as shown in FIG. As shown in the figure, a phenomenon occurs in which uneven streaks occur when the display is switched from the full screen display to the partial display of only the display unit A. There are two types of the stripes, one is a horizontal stripe L1 generated in the display unit A and seen as a luminance difference for each scanning electrode line, and the other is a vertical stripe L2 generated in the display unit B in which display is not performed. is there.

First, the horizontal streak is a write driving stop operation for controlling the power consumption of the non-display display section B as described above, and the display section A in the non-display period is compared with the display section B in the non-display period. For a long time, the AC driving balance of the liquid crystal display element 3 of the display unit A is broken, and it is considered that a luminance difference occurs between the lines. The vertical streak changes in accordance with the image signal level of the last line in the display section A, and tends to be darker in white display. Therefore, an image signal such as a gray scale signal or a lamp signal that changes from black to white or a black and white image signal is displayed. In the case of displaying a vertical stripe signal, the display portion B particularly has a remarkable vertical stripe shape under the white display portion. If the operation in this state continues for a long time, a vertical stripe-shaped pattern is burned. Since this phenomenon appears for a relatively long time of several tens to several hundreds of milliseconds from the time of switching the display mode, the image signal voltage written to the floating capacitance of the image signal electrode line 6 of the liquid crystal panel 5 is reduced. It is presumed that a leak current flows into the liquid crystal element of the display section B, which is not displayed due to being held in the accumulated state, and potential accumulation occurs. This phenomenon does not occur in normal scan driving because writing is performed every field (16.7 milliseconds at 60 Hz).

Here, the horizontal unevenness is caused by the fact that the display portion B of the non-display period continues for a long time with respect to the display portion A of the partial display period, so that the AC driving balance of the liquid crystal display element 3 of the display portion A is lost and the luminance between the lines is reduced. It is considered that a difference occurs. As a measure to solve this, it is necessary to suppress the influence of the voltage change on the liquid crystal display element 3 of the display unit A as much as possible when the display unit A enters the display unit B during the non-display period from the display unit A during the partial display period.

The present invention has been made in view of the above points, and has as its object to suppress uneven streaks that occur in an image display unit at the time of non-display, and in particular, to suppress horizontal streaks.

[0014]

According to a first aspect of the present invention, there is provided a matrix-like electrode comprising an image signal electrode and a scanning signal electrode, and a function of controlling an output current capability in response to an external signal. A source driver for supplying an image signal voltage to a signal electrode, a gate driver for supplying a scanning selection voltage to the scanning signal electrode, and an image provided in an area of each matrix electrode controlled by the image signal voltage and the scanning selection voltage A liquid crystal display panel including a display element group and a counter electrode commonly connected to one of the liquid crystal display elements; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; and driving of the liquid crystal display panel A timing signal generating circuit for controlling a timing signal, and dividing a vertical synchronization period into a plurality of image display periods to display only a part of the screen of the liquid crystal display panel. Switch circuit for switching between a partial display mode to be displayed and a full-screen display mode for displaying an entire screen; a counter signal voltage obtained by inverting the polarity of a voltage supplied to the counter electrode every one horizontal cycle period; and an external control signal. A counter signal voltage generation circuit that outputs a counter voltage as a DC voltage based on the control signal, and controls the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display switching signal from the changeover switch circuit. A control signal from the timing signal generation circuit by the partial display control circuit that detects the display switching signal when switching the switching switch circuit from the full screen display mode to the partial display mode. Stopping supply of a scanning selection voltage from the gate driver for a driving period of a non-display image display area, The counter voltage is stopped at a part of the non-display image display area, the counter voltage is stopped, and only the DC voltage component is supplied. The image output from the source driver during a part of the non-display image display area is also provided. It is characterized in that the output current capability of the signal voltage is suppressed.

According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, the timing signal generating circuit receives the counter voltage from the counter signal voltage generating circuit from a driving start point of a non-display image display area. After the delay of the delay period α, the counter voltage amplitude is stopped to supply only the DC voltage component, and the delay period β
After the delay, the output current capability of the image signal voltage output from the source driver is controlled to be suppressed.

According to a third aspect of the present invention, in the liquid crystal display device of the second aspect, the delay periods α and β are set in units of a horizontal synchronization period, and the relationship is α <β.

According to a fourth aspect of the present invention, in the liquid crystal display device according to the second aspect, when the number of display lines on the display side image display unit is an even number when the liquid crystal display panel is divided and displayed, the delay period α , β are set in units of horizontal synchronization periods (H), and when the relationship is α ≧ β, β = 1, 3, 5H,.
··· It is characterized by an odd period of ≦ α.

According to a fifth aspect of the present invention, in the liquid crystal display device of the second aspect, when the number of display lines of the image display unit on the display side is odd when the liquid crystal display panel is divided and displayed, the delay period α , β are set in units of the horizontal synchronization period (H), and when the relationship is α ≧ β, β = 2, 4, 6H,.
··· It is characterized by an even period of ≦ α.

According to a sixth aspect of the present invention, in the liquid crystal display device of the third aspect, each of the delay periods α and β is in a range of 3H to 10H, where H is a horizontal synchronization period.

According to a seventh aspect of the present invention, there is provided the liquid crystal display device according to any one of the first to sixth aspects.

The present invention thus provides a liquid crystal display device,
When non-display of the image display unit B is performed in the display mode of only the image display unit A, it is possible to suppress the occurrence of the horizontal streak in the image display unit A.

[0022]

FIG. 1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention. In this embodiment, a partial display control circuit 19 for detecting the state of the changeover switch circuit 17 and controlling the image display signal control circuit 11 and the timing signal generation circuit 12A is provided. The partial display circuit 19 converts the display switching signal (VM) into a display switching signal (VMC) synchronized with the vertical synchronizing signal. The timing signal generating circuit 12A outputs a power save control signal P which becomes H level only in the non-display section based on the display switching control signal VMC.
SC, a counter voltage control signal VCC, and a gate selection control signal GSC at L level. When switching from the partial display period to the non-display period of each field, the timing signal generation circuit 12A delays the counter voltage control signal VCC by a fixed delay period α and delays the power control signal PSC by a fixed delay period β. Further, a period in which the output current is suppressed from the source driver based on the delayed power control signal is delayed. The liquid crystal display panel 5A has substantially the same configuration as that of the liquid crystal display panel described above, as shown in FIG. 2, but differs in the configuration of the source driver 9A. The source driver 9A has a current capability control function that can receive a power save signal and control the output current of the image signal voltage. A buffer circuit composed of an operational amplifier is provided on the output side of the source driver 9A, and is configured so that its output current can be cut off based on a control signal. The output current is controlled based on the power control signal PSC.

FIG. 3 is a timing chart showing the main control signals. The detailed operation will be described below. The display mode is switched from the changeover switch circuit 17 for selecting the display mode to the low (L) state when both screens of the image display sections A and B are displayed.
o) In the partial display mode of only the image display section A, the display switching signal VM which becomes high (Hi) is output. Here, it is assumed that switched to the partial display mode from the full-screen mode at time t ₁ by the change-over switch circuit 17. When receiving the high (Hi) signal of the display switching signal VM from the changeover switch circuit 17, the partial display control circuit 19 switches to the state shown in FIG.
From the time t ₂ of the timing synchronized with one field (1F) period of the vertical synchronizing signal VD as shown in, and sends a display switching control signal VMC to the image display signal control circuit 11 and a timing signal generating circuit 12A. When the image display signal control circuit 11 receives the display switching control signal VMC, the image display signal of the display section B in the non-display period of t _{3 to} t ₄ , t _{5 to} t _6. It has a function of switching VS2 to a specific signal. This signal VS2 may be any signal that is not particularly limited. Display period t ₂ ~t _3, t
In ₄ ~t ₅ · · · outputting a partial display signals to be displayed on the image display unit A. On the other hand, when the timing signal generation circuit 12A receives the display switching control signal VMC, the power save control signal PS for changing the output current capability of the source driver 9A.
C and a gate selection stop signal GS of the gate driver 10A.
Output C. The power save control signal PSC is at time t ₃
~t _4, t ₅ ~t ₆ to rise to the non-display period of ... and allowed to slightly delay as described below is high (Hi), a high impedance source driver 9 as much as possible without the output current capability in response thereto State. Gate selection stop signal GSC
Is also set to low (Lo) during the non-display period, and the gate driver 10
By stopping the supply of the gate selection signal voltage from the TFT, the TFT 2 is always turned off so that the liquid crystal display element 3 is not charged with the image signal voltage.

By performing such a control operation, the liquid crystal panel 5A in the non-display period is output by the output of the source driver 9A.
Image signal electrode line 6 is in a high impedance state.
Accordingly, the image signal voltage is not supplied, and the energy of the stored charge written in the floating capacitance of the image signal electrode line 6 becomes extremely small. Therefore, almost no leak current occurs in the liquid crystal element of the display section B. Therefore, it is possible to suppress the occurrence of vertical stripes in the non-display portion.

Next, a method of supplying a potential for suppressing horizontal streak will be described. In order to reduce the power consumption in the partial display mode, the power save control signal PSC mainly related to the source driver 9A, the gate selection stop signal GSC related to the gate driver 10, It controls three types of the counter voltage control signal VCC related to the counter voltage generation circuit 18A. In the present embodiment, as shown in FIG. 4, control for delaying the stop of the output of the counter voltage and control for delaying the suppression of the output current of the source driver 9 are performed. The schematic timing of FIG. 3 is almost the same as that of the conventional example of FIG. FIG. 4 is a detailed timing chart of the main control signal near the boundary between the partial display period (display unit A) and the non-display period (display unit B) in the partial display mode in the cycle (1H) of the horizontal synchronization signal HD. It shows the state.

In this embodiment, as shown in FIG. 4, the operation start point for the counter voltage control signal VCC is delayed, and the operation start point for the power save control signal PSC is delayed. Thus, the display section A
The effect of suppressing horizontal streaks can be obtained. Looking at the state of the opposing voltage and the image signal voltage during the non-display period in the conventional driving method, (1) the opposing voltage is a center bias DC voltage in which the supply of the opposing voltage amplitude that is inverted every horizontal period is stopped,
(2) The image signal voltage supplied from the source driver 9 to the pixel signal electrode 6 is not supplied due to high impedance. Since (1) and (2) occur at the same time, the potential change immediately after the start of the non-display period becomes extremely unstable, so that the potential of the liquid crystal display element of the display unit A is pulled in one direction. Therefore, it is considered that a horizontal streak occurs.

As a means for solving this problem, the counter voltage control signal VC is supplied while the gate selection signal voltage in the non-display period is stopped.
Delay period α delaying the operation start point for C From t ₁₀ the H level. It has been found that by performing such control, an opposing voltage is supplied even in the early part of the non-display period, thereby acting on the liquid crystal display element 3 of the display unit A to mitigate a sudden change in potential. Likewise some power-save control signal PSC, the operation start point delay period β delaying From t ₁₁ the H level. By performing this control, the image signal voltage of the last line in the partial display period is supplied again from the source driver 9 to the image signal electrode line 6 at the beginning of the non-display period, so that the potential change to the liquid crystal display element 3 is reduced. It also works.

During these non-display periods, the counter voltage control signal VC
The delay control of the opposing voltage by C (delay period α) and the delay control of the re-supply of the image signal voltage by the power save control signal PSC (delay period β) can alleviate the horizontal stripes to some extent by themselves. Is performed at the same time, thereby further improving the horizontal streak improvement effect.

By the way, in the case of simultaneous control of both, the best condition exists in each delay control period. First, when delay control is performed simultaneously and continuously from the beginning of the non-display period, basically, the delay control of the common voltage by the common voltage control signal VCC (delay period α) is performed by re-supply of the image signal voltage by the power save control signal PSC. It must be shorter than the delay control (delay period β). That is, if the relationship of the delay period α <the delay period β is set, there is no problem unconditionally. For example, when the delay period is performed in units of one horizontal synchronization period (1H), the delay period α is 3
In the case of H, the delay period β is preferably set to 4H or more. In addition, depending on the number of display lines in the partial display period (display unit A), the same improvement can be made even when the relationship of delay period α ≧ delay period β is satisfied. Regardless of the delay period α of the counter voltage, the delay period β when the number of display lines in the partial display period is an even number is odd horizontal synchronization periods (1H, 3H,...: FIG. 4).
,...), And the delay period β when the number of display lines in the partial display period is an odd number corresponds to an even number of horizontal synchronization periods (2H, 4H,. ) Gave good results. Note that the delay periods α and β
The longer the effect, the better the effect, but the drive power increases accordingly. Therefore, it is desirable that the required minimum period is 3H to 10H from the viewpoint of margin, in view of the balance between the horizontal stripe suppression improvement effect and the power reduction.

In the description so far, the delay periods α and β are not displayed.
Start point of time period (display section B) (time t ₈)
However, the same applies to any position, such as during the non-display period.
The same effects can be obtained. In extreme cases, the delay period α is delayed.
As long as they are set before the extension period β,
There was no problem.

A variety of image display application devices having a plurality of display areas, such as a mobile phone, using the above-described liquid crystal display device and displaying only a partial display area at all times and displaying the entire screen as needed. Can be realized.

[0032]

According to the liquid crystal driving device of the present invention, the control of stopping the output current capability of the source driver is delayed by reducing the horizontal streak generated in the partial display portion when the display mode is switched by dividing the screen. Can be suppressed by delaying the inversion control of. As a result, it is possible to achieve both improvement in display quality and reduction in power consumption of the liquid crystal panel, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a display panel of this embodiment.

FIG. 3 is a timing chart of the liquid crystal display device according to the present embodiment.

FIG. 4 is an enlarged view of a timing chart in a time axis direction.

FIG. 5 is a configuration diagram of a general active type liquid crystal display panel using amorphous TFTs.

FIG. 6 is an example of a block circuit diagram in a conventional active-type liquid crystal display panel driving device.

FIG. 7 is an example of a configuration diagram of a liquid crystal display panel divided into two screens.

8 is a timing chart of main control signals in the divided display of the liquid crystal display device of FIG.

FIG. 9 is an explanatory diagram illustrating horizontal stripes on a display unit and vertical stripes on a non-display unit when partial display is performed in a two-screen split display of a liquid crystal display panel.

[Explanation of symbols]

 5, 5A Liquid crystal display panel 9, 9A Source driver 10 Gate driver 11 Image display signal control circuit 12, 12A Timing signal generation circuit 17 Changeover switch circuit 18 Counter signal voltage generation circuit 19 Partial display control circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623D 624 624E 624 642A (72) Inventor Hideki Mine Okadoma, Kadoma-shi, Osaka 1006 Matsushita Electric Industrial Co., Ltd.F-term (reference)

Claims (7)

[Claims] A source driver for supplying an image signal voltage to said image signal electrode, said electrode driver having a matrix-shaped electrode comprising an image signal electrode and a scanning signal electrode, and having an output current capability control function in response to an external signal; A gate driver for supplying a scan selection voltage to a scan signal electrode, a common image display element group provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage, and one of the liquid crystal display elements A liquid crystal display panel including a connected counter electrode; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; a timing signal generation circuit for controlling a drive timing signal of the liquid crystal display panel; A partial display mode in which a period is divided into a plurality of image display periods and only a part of the screen of the liquid crystal display panel is displayed, and a full screen is displayed A changeover switch circuit for switching between a full-screen display mode, an opposing signal voltage obtained by inverting the polarity of a voltage supplied to the opposing electrode every one horizontal cycle period, and an opposing voltage which is a DC voltage based on an external control signal. And a partial display control circuit that controls the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display switching signal from the changeover switch circuit. The control signal from the timing signal generating circuit by the partial display control circuit which has detected the display switching signal when the changeover switch circuit is switched from the full screen display mode to the partial display mode includes a non-display image display area. During the driving period, the supply of the scan selection voltage from the gate driver is stopped, and the counter voltage is set to the non-display image display area. And stopping the counter voltage to supply only the DC voltage component, and suppressing the output current capability of the image signal voltage output from the source driver during a part of the non-display image display area. Liquid crystal display device. 2. The timing signal generating circuit according to claim 1, wherein the counter voltage from the counter signal voltage generating circuit is delayed by a delay period α from a drive start point of a non-display image display area, and then the counter voltage amplitude is stopped. While supplying only the ingredients,
2. The liquid crystal display device according to claim 1, wherein the output current capability of the image signal voltage output from the source driver is controlled to be suppressed after a delay period β from the drive start point of the non-display image display area. . 3. The liquid crystal display device according to claim 2, wherein the delay periods α and β are set in units of horizontal synchronization periods, and the relationship is α <β. 4. When the number of display lines of an image display unit on the display side is an even number when the liquid crystal display panel is divided and displayed, the delay periods α and β are set in units of a horizontal synchronization period (H);
When the relationship is α ≧ β, β = 1, 3, 5H,.
3. The liquid crystal display device according to claim 2, wherein an odd period of α is set. 5. When the number of display lines of the image display unit on the display side is odd when the liquid crystal display panel is divided and displayed, the delay periods α and β are set in units of a horizontal synchronization period (H);
When the relationship is α ≧ β, β = 2, 4, 6H,.
3. The liquid crystal display device according to claim 2, wherein α is an even period. 6. The liquid crystal display device according to claim 3, wherein each of the delay periods α and β ranges from 3H to 10H, where H is a horizontal synchronization period. 7. An image display application device using the liquid crystal display device according to claim 1. Description: