JP2002299561A - Semiconductor integrated circuit device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm correct writing of additional information for enhancing traceability easily and surely in a short time even if the volume of the additional information is increased. SOLUTION: The semiconductor integrated circuit device comprises parity check logic circuits 10a-10d, and fuse circuits 20-27 for writing additional information. The fuse circuits 20-27 are provided at a redundancy fuse repairing section 12 and written, as additional information, with a format code, the start year of wiring, a month code of wiring lot, the wiring lot number, the wiring lot number suffix, the wafer number, the chip address, and the trimming information. A parity bit is written in the least significant bit of the additional information and, at the time of shipment, the parity check logic circuits 10a-10d perform parity check of the additional information and only a semiconductor integrated circuit device 1 written with correct additional information is shipped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving traceability in a semiconductor integrated circuit device.
The present invention relates to a technique effective when applied to shorten the test time of additional information written to improve traceability.

[0002]

2. Description of the Related Art In general, a semiconductor device such as a semiconductor integrated circuit device is provided with a relatively simple display such as a product type name by a marking method such as an ink printing method or a laser marking method. Such an indication may include abbreviated product manufacturing time information or product lot information.

For some types of semiconductor integrated circuit devices,
In order to enable more precise product management, specific information having a larger amount of information or additional information is added. That is, the specific information or the additional information of that kind makes it possible, for example, to clarify the details of the product manufacturing history according to the amount of the information. Accordingly, the analysis including the history trace when a failure occurs in the semiconductor integrated circuit device is facilitated. Such specific information or additional information is within the scope of technology for ensuring traceability of the semiconductor integrated circuit device.

The specific information or additional information is written on a semiconductor chip or the like so as to be electrically readable.

As a technique for recording additional information and the like on a semiconductor chip, as shown in Japanese Patent Application Laid-Open No. H04-111438, a plurality of fuses are formed on the semiconductor chip, and an additional fuse is cut by cutting an arbitrary fuse. As disclosed in JP-A-07-307257, there is a type in which a recording area including nonvolatile memory cells is formed in a semiconductor chip and additional information is stored in those memory cells.

[0006]

After the specific information as described above has been written, it is necessary to check whether the writing has been performed optimally. Note that such a check may be performed independently, but it is more preferable that the check be performed at the time of a so-called function test for checking whether the semiconductor integrated circuit device operates according to a predetermined function. That is, the tests or checks can use the same function test under the same test stage.

However, the present inventor has found that the above-described specific information confirmation technology in the semiconductor integrated circuit device has the following problems.

For example, when the code of the month when the semiconductor wafer was manufactured is written on the semiconductor chip as one of the specific information, the tester checks each month from January to December to test the semiconductor chip. This means that 12 types of expected value patterns or function test programs are required for each code. As a result, costs,
In addition, there is a problem that the man-hour and the like are increased.

In the above-described test, if semiconductor chips having different manufacturing months are mixed, a test program must be changed for each semiconductor chip having a different manufacturing month. There is a risk that a program change error or the like may occur.

Further, when the number of bits of the specific information is increased in order to increase the traceability, the above-mentioned expected value pattern also increases, the test time becomes longer, and the manufacturing efficiency of the semiconductor integrated circuit device decreases. There is a problem of doing it.

An object of the present invention is to provide a semiconductor integrated circuit capable of easily and reliably confirming whether or not additional information is written correctly in a short time even if the amount of specific information for improving traceability is large. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor integrated circuit device according to the present invention comprises: an information storage unit for storing specific information and error detection information enabling detection of an error in the specific information; and the specific information stored in the information storage unit. And an information checking unit for checking specific information by referring to the error detection information.

The specific information stored in the information storage unit is:
Preferably digital data consisting of a plurality of bits,
The error detection information is a parity bit added to the specific information, and the information check unit is configured by a parity check circuit that inputs the specific information and the error detection information.

Further, the information storage section is constituted by a nonvolatile memory.

Further, the nonvolatile memory comprises a fuse. In the case where the semiconductor integrated circuit device has a configuration including a semiconductor memory and a redundant circuit for relieving defects, in other words, when a specific circuit and a setting circuit for the specific circuit are provided, a nonvolatile memory for the information storage unit is provided. And the setting element for the setting circuit preferably has substantially the same structure. Specifically, when the setting element in the redundant circuit for the semiconductor memory is constituted by a defect relief fuse, the nonvolatile memory is also constituted by a fuse. More preferably, the specific information fuse circuit is provided in the rescue fuse.

Preferably, the specific information fuses are linearly arranged in the same row as the rescue fuses.

The parity check circuit is formed near the rescue fuse circuit.

Further, the specific information comprising a plurality of bits is formed into a plurality of groups for each bit unit, and each group is provided with a parity bit.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, an information storage unit for storing specific information and error detection information enabling detection of an error of the specific information, and an information storage unit for storing the specific information. A semiconductor integrated circuit device provided with an information inspection unit for inspecting the specific information by referring to the specified information and the error detection information, the method comprising the steps of: (B) a step in which the information inspection unit inspects the content of the specific information from the specific information and the error detection information stored in the information storage unit.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a defective fuse is replaced with a redundant bit by setting or performing a fuse process on a rescue fuse, and the rescue fuse circuit of the redundant circuit is set with the fuse. An information storage unit for storing the specific information to be detected and a parity bit enabling detection of an error in the specific information; and performing a parity check from the specific information and the parity bit stored in the information storage unit to check the specific information. A manufacturing method including the following steps in a semiconductor integrated circuit device in which an information inspection unit is provided, and the rescue fuse circuit and the information storage unit are arranged in substantially the same region.
(A) A test is performed on a memory circuit, and if the memory circuit has a defect, the repair fuse of the repair fuse circuit is subjected to a fuse process to perform redundancy repair, and a specific information fuse is set by fuse setting. A step of writing information and a parity bit; and (b) a step of the information checking unit performing a parity check of the specific information and the parity bit written in the information storage unit, and checking the specific information.

As described above, it is possible to quickly and accurately test whether or not the specific information stored in the information storage unit is correct, thereby reducing the test cost of the semiconductor integrated circuit device.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a layout diagram of main parts in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
FIG. 3 is a layout explanatory view of a redundant fuse rescue section provided in the semiconductor integrated circuit device of FIG. 1; FIG. 3 is a plan view of a fuse provided in an additional information fuse circuit of the redundant fuse rescue section of FIG. 2; AB sectional view of the fuse of FIG. 3,
5 is an explanatory diagram of additional information written in the semiconductor integrated circuit device of FIG. 1, FIG. 6 is an explanatory diagram showing an example of a write layout of the additional information of FIG. 5, and FIG. FIG. 8 is an explanatory diagram of the parity check of the written additional information, and FIG. 8 is a flowchart illustrating an inspection process in the semiconductor integrated circuit device of FIG.

In the present embodiment, the semiconductor integrated circuit device 1 has a large number of I / Os (Input / Output), that is, a so-called logic embedded DRAM (Dynam).
icRandom Access Memory).

The semiconductor integrated circuit device 1 has DRAM macros 2 to 9 laid out as shown in FIG. 1 and a parity check logic unit (information check unit, parity check logic circuit).
10 and a logic circuit.

Each of the DRAM macros 2 to 9 has a DR
This is a circuit block that functions as an AM. The parity check logic unit 10 is a logic circuit that performs a parity check on the additional information (specific information) VB, which is information for improving the traceability of the semiconductor integrated circuit device 1, and includes, for example, an exclusive OR circuit (EOR). Have been.

The logic circuit includes a logic control unit such as a microprocessor that controls all controls in the semiconductor integrated circuit device 1 and a memory unit 11 for temporarily storing input / output data.

The layout configuration of the semiconductor chip CH in the semiconductor integrated circuit device 1 will be further described below.

In the semiconductor chip CH, for example, a semiconductor element is formed on a semiconductor substrate such as single crystal silicon. As shown in FIG. 1, four DRAM macros 2 to 5 are provided above the semiconductor chip CH. Are formed. Further, below the semiconductor chip CH, four DRAM macros 6 to 9 are formed.

Further, at predetermined positions of the DRAM macros 2 to 9, a redundancy fuse rescue section (repair fuse circuit) is provided.
12 to 19 are formed. Redundant fuse rescue unit 1
2 and 13 are formed adjacent to the lower portions of the DRAM macros 2 and 3, respectively. Similarly, the redundancy fuse rescue units 14 and 15 are formed below and adjacent to the DRAM macros 4 and 5, respectively.

Further, the redundant fuse rescue units 16, 17,
The redundant fuse rescue sections 18 and 19 are formed above the DRAM macros 6 and 7 and the DRAM macros 8 and 9 so as to be adjacent to each other.

The redundancy fuse rescue sections 12 to 19 are provided with a plurality of rescue fuses. A memory cell or a line which becomes defective due to a defect is replaced with a spare line to rescue the defective cell. Is used as programming means for allocating the address corresponding to the spare part to the spare part.

Further, redundancy fuse rescue units 12 to 19
Are provided with additional information fuse circuits (information storage units) 20 to 27 in which additional information VB is stored.

Near the center of the semiconductor chip CH, DR
An I / O unit 28 provided in each of the AM macros 2 to 5 and an I / O unit 29 provided in each of the DRAM macros 6 to 9 are provided.

The memory section 11 is composed of, for example, nine memories 11a to 11i, and these memories 11a to 11h are provided with an SRAM (Static Lando).
mAccess Memory).

The memory 11a is provided between the I / O unit 28 and the I / O unit 29 at the center of the semiconductor chip CH, and the memories 11b to 11e are adjacent to the I / O unit 28. They are formed near the DRAM macros 2 to 5, respectively. The memories 11f to 11i are formed adjacent to the I / O unit 29 and in the vicinity of the DRAM macros 6 to 9, respectively.

The parity check logic section 10 is composed of four parity check logic circuits 10a to 10d, and these parity check logic circuits 10a to 10d
Performs an exclusive OR operation on the digital data of the additional information VB written in the additional information fuse circuits 20 to 27, and
Output as bit check data.

Here, the layout of the redundancy fuse rescue section 12 provided in the DRAM macro 2 will be described.

As shown in FIG. 2, the redundant fuse rescue section 12 includes six resilient fuse circuits 12 _{1 to} 12 at the top.
₆ is formed, to lower, six relief fuse circuit 12 _{7-12 12} is formed.

The rescue fuse circuits 12 _{1 to} 12 ₃ , 12
_5, 12 ₆ are provided respectively thirty relief fuse, to repair fuse circuit 12 _{7-12 12,} 22 present relief fuses are provided, respectively.

[0043] and, 3 is also in relief for the fuse circuit 12 ₄
Although 0 fuses are provided, 23 of these 30 fuses are rescue fuses, and the remaining 7 fuses are provided.
The fuse F (FIG. 3) forms an additional information fuse circuit 20. Therefore, 7-bit additional information VB is written in the additional information fuse circuit 20.

These rescue fuse circuits 12 ₁ to ₁ 1
Relief fuse in 2 _6, 12 ₇ to 12 _12, FIG. 2
Are formed in a line in the vertical direction. Further, the fuse F in seven relief fuse circuit 12 ₄ is likewise 2
It is formed so as to be in the same column as the three rescue fuses.

Thus, in the step of performing the fuse process on the rescue fuse, the fuse F of the additional information fuse circuit 20 can be subjected to the fuse process, and the alignment of the laser beam or the like at the time of the fuse process can be easily performed.

In FIG. 2, the redundant fuse rescue section 12 provided in the DRAM macro 2 has been described.
The redundancy fuse rescue units 13 to 19 provided in the RAM macros 3 to 9 have the same configuration, and the additional information fuse circuits 21 to 27 are provided with seven fuses F, respectively.

Therefore, the additional information fuse circuits 20 to 27
, It is possible to write additional information VB for a total of 56 bits. Of the additional information VB of 56 bits, the lower one bit is a parity bit (error detection information) P.
Written as B.

As described above, the configuration in which the additional information VB is dispersedly arranged in the redundant fuse rescue sections 12 to 19 of the DRAM macros 2 to 9 makes it possible to appropriately use the fuse rescue section area. This distributed arrangement does not require a significant change in the layout of a plurality of DRAM macros and logic circuits, unlike the case where fuses for additional information VB are centrally arranged at one specific location. This feature, for example,
It is advantageous that a subtle change in the operation timing of each DRAM macro can be avoided.

The additional information fuse circuit 20 (to 2)
The fuse F used in 7) will be described.

The fuse F is not particularly limited, but is a fusing type fuse. Fusing of a fusing type fuse is performed by fusing energy such as a laser beam. As shown in FIGS. 3 and 4, the fuse F has a semiconductor device, a wiring layer, and the like formed thereon. An insulating film Z1 made of silicon nitride (Si—N) and an insulating film Z2 made of polyimide and the like are formed thereon. It is formed on the uppermost wiring layer H of the formed semiconductor substrate.

The uppermost wiring layer includes a gold (Au) wiring H1, a nickel (Ni) wiring H2,
It consists of a chrome (Cr) wiring H3.

A power supply line to which a power supply voltage formed in the lower aluminum wiring layer is supplied is connected to one connection portion of fuse F through a contact hole C1 made of, for example, tungsten or the like. The other connecting portion of the fuse F is connected to a predetermined signal wiring formed on the aluminum wiring layer via a contact hole C2.

The fuse F is connected to a chrome wiring H3.
Only the wiring H1 of gold and the wiring H2 of nickel are not formed. Thus, the fuse F can be easily cut.

Next, the inspection process of the semiconductor integrated circuit device 1 according to the present embodiment will be described with reference to FIGS. 1 and 2 and FIGS. Illustration of parity check of additional information, and FIG.
This will be described with reference to the flowchart of FIG.

First, a logic test for measuring a logic function such as a microprocessor provided in a logic circuit in the semiconductor integrated circuit device 1 and electrical characteristics is performed using a logic tester or the like (step S10).
1) It is determined whether or not there is a defect (step S10)
2) The semiconductor integrated circuit device 1 is sorted into a defective product and a good product.

Thereafter, an SRAM memory test in the memory section 11 is performed using a memory tester or the like (step S103), and it is determined whether or not the memory section 11 has a defect (step S104). The semiconductor integrated circuit device 1 is sorted.

Thereafter, the non-defective semiconductor integrated circuit device 1
DRA in memory devices of DRAM macros 2 to 9
An M memory test is performed by the memory tester (Step S105).

If there is a defect in the memory device, any relief fuse provided in the redundancy fuse relief sections 12 to 19 is cut by, for example, a laser beam to perform redundancy relief (step S106).

At the time of the redundancy repair, the fuses F of the additional information fuse circuits 20 to 27 are cut at the same time, and arbitrary additional information VB is written. This eliminates the need for a new step of writing the additional information VB, and allows the additional information VB to be written efficiently.

Here, the additional information VB will be described.

As shown in FIG. 5, the additional information VB includes, for example, a format code, a wiring start year, a wiring lot month code, a wiring lot number, a wiring lot number suffix, a wafer number, a chip address (X), and a chip address ( Y), and timing trimming.

The format code is a code defining the writing order of the items written as the additional information VB, and is assigned two bits. The wiring start year is a code indicating the start year of the wiring lot by the last digit of the Christian era, and three bits are assigned. Also,
In the information on the wiring start year, not only the start year but also the number of allocated bits may be increased to indicate the start date of the wiring lot.

The wiring lot month code is a code indicating the month lot of the semiconductor wafer, and is assigned 4 bits. The wiring lot number is, for example, a code indicating a lot of semiconductor wafers composed of a four-digit decimal lot number, and is assigned with 14 bits.

The wiring lot number suffix is DRAM
This code indicates the number of times the memory tests of the macros 2 to 9 have been performed, and 5 bits are allocated. The wafer number is a number assigned to the semiconductor wafer in each lot, and is assigned 5 bits.

Further, the chip address (X) and the chip address (Y) are position data indicating the X coordinate and the Y coordinate of each semiconductor chip CH on the semiconductor wafer, and 4 bits are assigned to each.

Therefore, among the 56 bits provided in the additional information fuse circuits 20 to 27, 4
Nine bits are used, and the other one bit is used as a parity bit PB.

FIG. 6 shows an example of writing the additional information VB.

From the left side to the right side of FIG.
7 shows seven fuses F for writing the additional information VB provided in the additional information fuse circuits 20 to 27 of the AM macros 2 to 9, respectively, and 7 bits of Bit0 to Bit6 are written as the additional information VB.

Trimming information in which the clock phase of the DRAM clock is adjusted is written in Bit 4 and Bit 5 of the additional information fuse circuit 20 in the DRAM macro 2. Trimming information obtained by adjusting the local clock is written in Bit 6 of the additional information fuse circuit 20 and Bit 0 of the additional information fuse circuit 21.

Bits 1 and 2 of the additional information fuse circuit 21 in the DRAM macro 3 have a DRAM
Trimming information in which the clock phase of the macro has been adjusted is written, and Bit3, Bit3,
In Bit 4, trimming information obtained by adjusting the clock phase of the SRAM pulse is written.

Bits 5 and B of additional information fuse circuit 21
In it6, a format code is written, and DRA
Bit of additional information fuse circuit 22 in M macro 4
In 0 to Bit2, a wiring construction year is written.

Further, Bi of the additional information fuse circuit 22
The wiring lot month code is written in t3 to Bit6. Bit0 to Bit6 of the additional information fuse circuit 23 in the DRAM macro 5, and the DRAM macro 6
Bit0 to Bit of the additional information fuse circuit 24 at
6, a wiring lot number is written.

A wiring lot number suffix is written in Bit 0 to Bit 4 of the additional information fuse circuit 25 in the DRAM macro 7, and Bit 5 and Bit 6 of the additional information fuse circuit 25 and the additional information fuse circuit 26 in the DRAM macro 8 are written. Bit0-Bi
At t2, the wafer number is written.

Bits 3 to B of additional information fuse circuit 26
In it6, the chip address of the X coordinate is written,
B of the additional information fuse circuit 27 in the RAM macro 9
A chip address of the Y coordinate is written in it0 to Bit3. Bit 4 of the additional information fuse circuit 27 has a parity bit PB for performing a parity check.
Is written.

When the redundancy repair in the process of step S106 is completed, it is determined whether or not the DRAM macros 2 to 9 are defective (step S107), and the semiconductor integrated circuit device 1 is selected.

Thereafter, a function test of the semiconductor integrated circuit device 1 is performed (step S108), and it is determined whether or not the semiconductor integrated circuit device 1 has a defect (step S109).

This function test is a test for confirming whether or not the semiconductor integrated circuit device 1 operates according to a predetermined function. A test pattern is sequentially applied to input terminals, and a pattern appearing at an output terminal is an expected value. A comparison check is made to see if it is.

Thereafter, the parity check of the additional information VB is performed (step S110), and it is checked whether or not the additional information VB is correctly written (step S11).
1). In this case, the additional information V
Since it is confirmed whether B is correctly written, even the additional information VB having a large number of bits can be efficiently and easily confirmed in a short time.

Here, a confirmation test technique in the parity check of the additional information VB will be described.

In the semiconductor integrated circuit device 1, as shown in FIG. 7, the latches L are respectively connected to the fuses F of the additional information fuse circuits 20 to 27 provided in the DRAM macros 2 to 9.

When the fuse F is blown, "1" (high level) is written into these latches L.
If the fuse F is not blown, "0" (low level) is written.

The latch L is connected to a parity check logic unit 10 for performing a parity check via the latch LP. The parity check logic unit 10 performs an exclusive OR operation on the input additional information VB and the parity bit PB to perform a parity check.

When the parity check by the parity check logic unit 10 is completed, a 1-bit check signal after the parity check is output to the tester TE via the output buffer B1, and it is determined whether the additional information VB is correct. Done.

The latch LP is a boundary scan latch, and performs a shift register operation at the time of failure analysis or the like, and can read the additional information VB via the buffer B2.

Then, in step S110,
The non-defective semiconductor integrated circuit device 1 determined to have the additional information VB correctly written by the parity check is shipped (step S112).

Thus, in the present embodiment, additional information fuse circuits 20 to 27 of semiconductor integrated circuit device 1 are provided.
By checking the additional information VB written in the additional information by parity check, the test time of the additional information VB can be significantly reduced.

Further, since the additional information VB having a large number of bits can be tested in a short time, the information amount of the additional information VB can be increased, and the traceability of the semiconductor integrated circuit device 1 can be further improved. Analysis can be performed easily and in a short time.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the parity bit PB is added to the least significant bit of the additional information. Even in this embodiment, a sufficient check can be performed according to the level of the fuse programming technique. However, it is determined that the parity check is normal despite the presence of an error such as a two-bit error. When it is necessary to avoid being done,
As shown in FIG. 9, the additional information VB may be divided for each certain bit, and a parity bit PB may be provided for each of the divided bits.

As a result, even when the number of bits of the additional information VB is greatly increased in order to improve traceability, it is possible to confirm writing of the additional information VB with high accuracy only by parity check.

The fuse may be changed from a substantially cut off state to a connected state by a fuse process called an anti-fuse instead of a blown type fuse.

According to the above embodiment, the additional information and the parity bit are written in the additional information fuse circuit provided in the rescue fuse circuit. However, the writing of the additional information and the parity bit is performed. May be other than a fuse. For example, an additional information storage unit composed of a nonvolatile semiconductor memory may be provided, and the additional information and the parity bit may be stored in the additional information storage unit.

Further, in the above-described embodiment, the parity bit is added to the written additional information to perform a parity check. However, information having the same content as the additional information or inversion information complementary to the additional information is used as the error detection information. When checking the additional information, the additional information and the error detection information may be read, and the additional information or its inverted information and the error detection information may be compared.

[0094]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) Whether the additional information stored in the additional information storage section is correct can be tested in a short time and with high accuracy, and the test cost can be reduced.

(2) Additional information to be entered for improving traceability can be increased, and failure analysis of a semiconductor integrated circuit device can be easily performed.

(3) According to the above (1) and (2), the reliability of the semiconductor integrated circuit device can be improved, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a main part in a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is an explanatory diagram of a layout of a redundancy fuse rescue unit provided in the semiconductor integrated circuit device of FIG. 1;

FIG. 3 is a plan view of a fuse provided in an additional information fuse circuit of the redundancy fuse rescue section of FIG. 2;

FIG. 4 is a cross-sectional view taken along a line AB of the fuse of FIG. 3;

FIG. 5 is an explanatory diagram of additional information written in the semiconductor integrated circuit device of FIG. 1;

FIG. 6 is an explanatory diagram showing an example of a write layout of additional information in FIG. 5;

7 is an explanatory diagram of a parity check of additional information written in the semiconductor integrated circuit device of FIG. 1;

FIG. 8 is a flowchart illustrating an inspection process in the semiconductor integrated circuit device of FIG. 1;

FIG. 9 is an explanatory diagram showing another example of additional information written in a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2-9 DRAM macro 10 Parity check logic part (information check part, parity check circuit) 10a-10d Parity check logic circuit 11 Memory part 11a-11i Memory 12 Redundant fuse rescue part (Rescue fuse circuit) 12 _{1 to} 12 ₆ Fuse circuit for rescue 12 _{7 to} 12 ₁₂ Fuse circuit for rescue 13 to 19 Redundant fuse rescue section (Rescue fuse circuit) 20 to 27 Additional information fuse circuit (Information storage section) 28, 29 I / O Part VB Additional information (specific information) CH Semiconductor chip F Fuse Z1 Insulating film Z2 Insulating film H Upper wiring layer C1, C2 Contact hole L Latch LP latch B1 Buffer B2 Buffer TE Tester

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/02 G11C 11/34 371A 21/82 371D H01L 21/82 RT (72) Inventor Takashi Tsubaki Tokyo 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ultra-SII Systems Co., Ltd. (72) Inventor Nobuaki Kitamura 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. (72) Inventor Michiaki Nakayama 3-16, Shinmachi, Ome-shi, Tokyo 3 Inside Device Development Center, Hitachi, Ltd. (72) Inventor Shuichi Miyaoka 6-chome, Shinmachi, Ome-shi, Tokyo F-term (reference) at Hitachi Ltd. Device Development Center at 16-3 2G132 AA08 AA09 AB01 AC05 AE19 AL02 AL09 5F038 AV03 AV10 AV15 DF04 DF05 DF11 DT06 DT13 DT15 DT19 EZ20 5F064 BB02 BB04 BB09 BB14 DD47 FF01 FF02 FF27 FF32 FF33 FF42 5L106 AA01 AA08 AA10 BB02 CC04 CC08 CC09 CC13 CC21 CC32 DD12 DD24 DD25 EG05 MM05 BB05 PP10

Claims (11)

[Claims] 1. A semiconductor integrated circuit device in which specific information is set therein and the specific information can be externally referred to in a predetermined operation, wherein the specific information and an error of the specific information are detected. A semiconductor integrated circuit device, comprising: an information storage unit that stores error detection information to be enabled; and an information inspection unit that inspects the specific information by referring to the specific information and the error detection information. 2. The semiconductor integrated circuit device according to claim 1, wherein the specific information in the information storage unit is digital data composed of a plurality of bits, and the error detection information is a parity bit for the specific information. A semiconductor integrated circuit device, wherein the information checking unit comprises a parity check circuit that receives the specific information and the error detection information as inputs. 3. The semiconductor integrated circuit device according to claim 1, wherein said information storage unit comprises a nonvolatile memory. 4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device further includes a setting circuit having a setting element, and setting a circuit operation by the setting element. Is a semiconductor integrated circuit device comprising elements that can be written by the same writing method. 5. The semiconductor integrated circuit device according to claim 4, wherein said setting circuit comprises a redundant circuit for a semiconductor memory, and wherein said setting element and said nonvolatile memory comprise a fuse element. Semiconductor integrated circuit device. 6. The semiconductor integrated circuit according to claim 4, wherein the fuse element for the information storage unit is formed in a straight line in the same row as the fuse element for the redundant circuit. Circuit device. 7. The semiconductor integrated circuit device according to claim 5, wherein said parity check circuit is formed near said redundant circuit fuse element. 8. The semiconductor integrated circuit device according to claim 2, wherein the specific information of the plurality of bits is divided into a plurality of groups for each bit unit, and the parity bits are set for each group. A semiconductor integrated circuit device comprising: 9. A semiconductor integrated circuit device having a plurality of bits of product-specific information therein, wherein the plurality of bits of product-specific information are checked, and a check output having a smaller number of bits than the plurality of bits is formed. A semiconductor integrated circuit device, comprising: a plurality of bits; and an external output of the plurality of bits of the product-specific information and an external output of the check output. 10. An information storage unit for storing specific information and error detection information enabling error detection of the specific information, and by referring to the specific information and the error detection information stored in the information storage unit. A method for manufacturing a semiconductor integrated circuit device, comprising: an information inspection unit that inspects the specific information, wherein the specific information and the error detection information are stored in the information storage unit; Inspecting the content of the specific information from the specific information stored in the information storage unit and the error detection information. 11. A redundant circuit having a memory circuit, a rescue fuse, and replacing a defective bit of the memory circuit with a redundant bit by a program of the rescue fuse, and a fuse. A semiconductor integrated circuit device comprising: an information storage unit that holds a parity bit for information; and an information inspection unit that performs a parity check from the information in the information storage unit and the parity bit and inspects the content of the specific information. A manufacturing method for testing the memory circuit, and when the memory circuit has a defect, performing a redundancy remedy by using a rescue fuse program of the rescue fuse circuit and programming a fuse of the information storage unit. Writing the specific information and the parity bit by Specific information written in the information storage unit, and a parity check of the parity bit is performed is the information checking unit,
Inspecting the content of the specific information.