JPH1064300A - Semiconductor memory and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately understand whether a faulty address has been rescued appropriately or not. SOLUTION: A recognition bit part 19 has a storage part for outputting '0' when a specific row of a regular memory cell array 11 is accessed. Similarly, a recognition bit part 20 has a storage part for outputting '1' when the specific row of a preliminary memory cell array 13 is accessed. When an address signal for specifying a faulty address is supplied in a shipment test, it is judged that the faulty address has not been rescued properly if no '0' is outputted from the recognition bit part 19 and it is judged that the faulty address is rescued appropriately if '1' is outputted from a recognition bit part 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory having a redundancy circuit, and is used for determining whether or not a part of normal memory cells has been correctly switched to a spare memory cell.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional semiconductor memory.

In order to simplify the following description, this semiconductor memory has 128 addresses (00 to 7F), that is, 32 addresses.
Row address (R0 to R31) and four column addresses (C0 to C3), and one address includes a 1024-bit normal memory cell array 11 corresponding to 8-bit data. Assume that

[0004] Semiconductor memories include DRAMs, SRAs.
M or a volatile semiconductor memory such as a mask R
A nonvolatile semiconductor memory such as an OM, an EPROM, and an EEPROM may be used.

At the end of the normal memory cell array 11 in the row direction (the direction in which the word lines R0 to R31 extend), a row decoder 12 is arranged. The row decoder 12 is
One row is selected based on a row address signal, and a high potential is supplied to the selected row.

A spare memory cell array 13 is arranged at the end of the normal memory cell array 11 in the column direction (the direction in which the data lines extend).

The spare memory cell array 13 includes, for example, 1
6 addresses (00 to 0F), that is, four row addresses (r0 to r3) and four column addresses (C0 to C3)
It is assumed that one address is composed of 128 bits corresponding to 8-bit data.

[0008] The selection circuits 14 a to 14 d are arranged between the spare memory cell array 13 and the read circuit 16. The column decoder 15 selects one selection circuit, that is, one column, based on the column address, and guides data of the selected column to the reading circuit 16.

The address register 17 divides an address signal supplied from outside or inside an LSI chip on which the semiconductor memory is formed into a row address signal and a column address signal.

The memory cell switching circuit 18 has a storage unit for storing a defective row address of the normal memory cell array 11. This storage unit is composed of, for example, a plurality of fuses.
This is performed by cutting a predetermined fuse of the plurality of fuses with a laser.

When a row address is stored in the storage section of the memory cell switching circuit 18 and the row address output from the address register 17 matches the row address of the storage section of the memory cell switching circuit 18, The switching circuit 18 includes the row decoder 12.
(Inhibition) is output.

At the same time, the memory cell switching circuit 18
One row of the spare memory cell array 13 is selected, and a high potential is supplied to the selected row. As a result, the defective row of the normal memory cell array 11 is switched to a predetermined row of the spare memory cell array.

In a semiconductor memory provided with the above-mentioned redundancy circuit (part of the spare memory cell array 13 and the memory cell switching circuit 18), after the operation test of the semiconductor memory is completed, a defective row exists in the normal memory cell array 11. If there is, the storage section of the memory cell switching circuit 18 stores the address of the defective row.

After storing the defective row address,
Before shipping the product, a shipping test is performed to check whether the defective row of the normal memory cell array 11 has been properly switched to a predetermined row of the spare memory cell array.

Conventionally, this shipping test has been performed as follows.

In the case of a volatile semiconductor memory, the defective row of the normal memory cell array 11 is replaced with the spare memory cell array 13.
The same operation test as before the switching to the predetermined row is performed to confirm whether the normal operation is performed or not. If the normal operation is performed, the defective row of the normal memory cell array 11 It is determined that the row has been properly switched.

In the case of a non-volatile semiconductor memory, the following two shipping tests have been considered, utilizing the characteristics of the non-volatile semiconductor memory that does not lose data even when the power is turned off.

A. First, specific data ("1" data) is written to all memory cells of the normal memory cell array 11. Next, the defective row of the normal memory cell array 11 is switched to a predetermined row of the spare memory cell array 13. Here, the data of all the memory cells of the spare memory cell array 13 is
The data is set to an initial state ("0" data). Thereafter, the data is read, and it is confirmed whether or not the data read from the memory cell of the switched row is "0".

Also, specific data is written into the memory cell of the row where the switching has been performed, and the specific data is written from the memory cell.
By reading the data, it is determined whether or not the defective row of the normal memory cell array 11 has been properly switched to a predetermined row of the spare memory cell array 13.

B. First, specific data ("0" data) is written to all the memory cells of the normal memory cell array 11. Next, specific data ("1" data) that can be distinguished from the data of the memory cells of the normal memory cell array 11 is written to all the memory cells of the spare memory cell array 13. Next, the defective row of the normal memory cell array 11 is switched to a predetermined row of the spare memory cell array 13.

Thereafter, the data is read, and the data read from the memory cell of the switched row is convinced, and the data is specified data ("1" data). , The defective row is assigned to the spare memory cell array 13.
Is determined to have been properly switched to the predetermined row.

[0022]

In the semiconductor memory, whether or not a defective row of the normal memory cell array 11 and a predetermined row of the spare memory cell array 13 are switched is determined by confirming the operation.

Therefore, if the operation is normal, the defective row of the normal memory cell array 11
Even if it has not actually been switched to the third predetermined row, it is determined that it has been switched.

For example, even though there is a row in the normal memory cell array 11 which is determined to be defective due to lack of margin for determining the "1" (or "0") level of the memory cell, any mistake may cause the error. Even if the defective row is not properly switched to the predetermined row of the spare memory cell array 13, if it operates normally in the shipping test, it is determined that the switching has been performed.

Problems of Nonvolatile Semiconductor Memory (Test a.
Will be described in consideration of the actual test process.

First, in the first die sort test, C
(Checker) pattern, D pattern (a pattern in which writing is not performed on diagonal memory cells)
Data write and read to detect a defective address.

It is determined whether or not all the defective addresses can be rescued by the redundancy circuit. If the resiliency can be remedied, the fuse is blown off (storage of the defective addresses) using a fuse blower or the like.

Next, in the second die sort test, data writing and reading are executed for the memory cell of the defective address (after switching), and the memory cell of the defective address in the normal memory cell array 11 is replaced with the spare memory cell array. It is determined whether the memory cells have been properly switched to the thirteenth memory cells.

At the same time, aging of the memory cell such as leaving it at a high temperature is performed with the data of the D pattern written in the normal memory cell array 11 and the spare memory cell array 13. Then, in the third die sort test, the data of the D pattern is read, and the holding characteristics are determined.

In such a test process, specific data is written to the spare memory cell array 13 for the first time in the second die sort test. Such an approach,
This is effective for determining whether or not a defective row of the normal memory cell array 11 has been properly switched to a predetermined row of the spare memory cell array 13.

However, in this method, after the D pattern is completed, it is left in a high temperature state, so that the third die cutting is performed.
Test is required.

If there is no switching of the memory cells, the D pattern is completed in the first die sort test, and after holding at high temperature, the determination of the holding characteristics is completed in the second die sort test.

That is, in this method, when the memory cells are switched by the redundancy circuit, there is a disadvantage that the number of the die sort tests is increased by one time as compared with the case where the memory cells are not switched.

A method has been devised to solve this drawback.

In the first die sort test, a defective address of the normal memory cell array 11 is detected, and the pattern of the write data of the memory cell of the defective address in the spare memory cell array 13 is previously determined. Is written in advance.

In this way, after the fuse has been cut (fault address storage) by a fuse blower or the like and subjected to aging such as leaving at a high temperature, the second die saw is performed.
In the test, the already completed D pattern can be read.

Therefore, by two die sort tests,
It is possible to check whether the memory cell of the defective address of the normal memory cell has been correctly switched to the memory cell of the spare memory cell array.

However, even if such a method is used, there are still the following problems.

First, although there is a row in the normal memory cell array 11 which is determined to be defective due to lack of margin for determining the "1" (or "0") level of the memory cell, some mistake ( Fuse uncut, etc.)
Even if the defective row is not properly switched to a predetermined row of the spare memory cell array 13, if it operates normally,
It is determined that the switching has been performed (incomplete switching).

Second, for example, if the fuse is cut off halfway and is switched to the row of the spare memory cell array 13, but the row is not the desired row but another row, the shipment is performed. If the same data as that of the desired row is accidentally written in another row during the test, a defect cannot be found (duplicate address access).

In this case, when the same data as the write data is stored in the memory cell of the other row, the defective row has been properly switched to the predetermined row of the spare memory cell array 13. Even if not, it is determined that the switching has been correctly performed.

Third, a case where a defective row is not properly switched to a predetermined row of the spare memory cell array 13 due to some mistake, and another row different from the defective row of the normal memory cell is accessed. (Incomplete switching + duplicate address access).

In this case, if the same data as the write data is stored in the memory cell of the other row, it is determined that the switching has been correctly performed.

The present invention has been made in order to solve the above-described drawbacks. An object of the present invention is to provide a semiconductor memory having a redundancy circuit, in which after storing a defective address, a memory cell having a defective address in a normal memory cell array is used. To accurately and reliably determine whether or not the memory cell has been properly switched to the spare memory cell array,
And to grasp the address of the switched row of the spare memory cell array.

[0045]

In order to achieve the above object, a semiconductor memory according to the present invention comprises: a normal memory cell array; a spare memory cell array additionally provided to the normal memory cell array; A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address of the normal memory cell array when specifying a defective address of the normal memory cell array; And outputting first recognition bit data indicating that a predetermined address of the normal memory cell array has been accessed. When the predetermined address of the spare memory cell array is actually accessed, the predetermined address of the spare memory cell array is accessed. Second recognition bit indicating that the - a recognition bit unit for outputting data, the first output from the recognition bit portion or the second
A bit data reading circuit for reading the recognition bit data.

The semiconductor memory according to the present invention comprises a normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and the normal memory cell array when an address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address of the spare memory cell array; and an address bit data indicating a predetermined address of the spare memory cell array when the predetermined address of the spare memory cell array is actually accessed. An address bit section for outputting data, and a bit data reading circuit for reading the address bit data output from the address bit section.

The semiconductor memory of the present invention comprises a normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and the normal memory cell array when an address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address, and a predetermined address of the normal memory cell array being accessed when a predetermined address of the normal memory cell array is actually accessed. And outputs second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed. The recognition bit portion to be When a predetermined address of the memory cell array is actually accessed, an address bit portion for outputting address bit data indicating a predetermined address of the spare memory cell array, and the first or second output from the recognition bit portion. A bit data reading circuit for reading out the recognition bit data and the address bit data output from the address bit section, respectively.

The spare memory cell array is arranged at one of two ends in the column direction of the normal memory cell array, and the recognition bit portion is located at two ends of the normal memory cell array and the spare memory cell array in the row direction. At one of the two ends.

The recognition bit section has a first storage section for storing the first recognition bit data and a second storage section for storing the second recognition bit data. Is actually accessed,
The first recognition bit data is output from the first storage unit, and when a predetermined row of the spare memory cell array is actually accessed, the second recognition bit data is output from the second storage unit. You.

In the first storage section, a source is connected to a first power supply terminal, a gate is connected to a predetermined row of the normal memory cell array, and a drain is connected to the bit data read circuit. The second storage unit includes a plurality of MOS transistors, the source of which is connected to a second power supply terminal, the gate of which is connected to a predetermined row of the spare memory cell array, and the drain of which is the bit data readout. It is composed of a plurality of MOS transistors connected to the circuit.

The first storage section comprises a resistor connected between the bit data read circuit and a first power supply terminal, and the second storage section has a source connected to a second power supply terminal. The gate is connected to a predetermined row of the spare memory cell array, and the drain is composed of a plurality of MOS transistors connected to the bit data read circuit.

The spare memory cell array is disposed at one of two ends of the normal memory cell array in the column direction, and the address bit portion is provided at one of two ends of the spare memory cell array in the row direction. Are arranged in one of them.

The address bit section has a storage section for storing address bit data indicating an address of each row of the spare memory cell array. When a predetermined row of the spare memory cell array is actually accessed. Address bit data indicating an address corresponding to the predetermined row is output from the storage unit.

In the storage section, a source is connected to the first power supply terminal or the second power supply terminal, a gate is connected to a predetermined row of the spare memory cell array, and a drain is connected to the bit data read circuit. It is composed of a plurality of connected MOS transistors.

The storage section has a resistor connected between the bit data read circuit and the first power supply terminal, a source connected to the second power supply terminal, and a gate connected to the spare memory cell array. A plurality of MOS transistors connected to a predetermined row and having a drain connected to the bit data read circuit.

The spare memory cell array is arranged at one of two ends in the row direction of the normal memory cell array. The spare memory cell array is disposed at one of two ends in the column direction of the normal memory cell array, and a first selection circuit for selecting a column of the normal memory cell array; and a column of the spare memory cell array. A second selection circuit disposed at one of the two ends in the direction and selecting a column of the spare memory cell array. The recognition bit unit is configured to include the first and second
It is arranged adjacent to the selection circuit.

The recognition bit section has a first storage section for storing the first recognition bit data and a second storage section for storing the second recognition bit data. When the first column is actually selected, the first recognition bit data is output from the first storage unit, and when a predetermined column of the spare memory cell array is actually selected, the plurality of second recognition bits are output. The second from the storage unit
Recognition bit data is output.

The first storage section includes a plurality of MOS transistors each having a source connected to a first power supply terminal, a gate connected to the first selection circuit, and a drain connected to the bit data read circuit. The second storage unit includes a plurality of transistors each having a source connected to a second power supply terminal, a gate connected to the second selection circuit, and a drain connected to the bit data read circuit. MOS transistors.

The first storage section comprises a resistor connected between the bit data read circuit and a first power supply terminal, and the second storage section has a source connected to a second power supply terminal. The gate is connected to the second selection circuit, and the drain is composed of a plurality of MOS transistors connected to the bit data read circuit.

The spare memory cell array is arranged at one of two ends in the row direction of the normal memory cell array. The spare memory cell array is disposed at one of two ends in the column direction of the normal memory cell array, and a first selection circuit for selecting a column of the normal memory cell array; and a column of the spare memory cell array. A second selection circuit disposed at one of the two ends in the direction and selecting a column of the spare memory cell array. The address bit section is arranged adjacent to the first and second selection circuits.

The address bit section has a storage section for storing address bit data indicating an address of each column of the spare memory cell array. When a predetermined column of the spare memory cell array is actually accessed. Then, address bit data indicating an address corresponding to the predetermined column is output from the storage unit.

In the storage section, a source is connected to the first power supply terminal or the second power supply terminal, a gate is connected to the second selection circuit, and a drain is connected to the bit data read circuit. It is composed of a plurality of MOS transistors.

The storage section has a resistor connected between the bit data readout circuit and the first power supply terminal, a source connected to the second power supply terminal, and a gate connected to the second selection circuit. And a plurality of MOS transistors whose drains are connected to the bit data read circuit.

A semiconductor memory according to the present invention includes a normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a memory cell array when the address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address, and a predetermined address of the normal memory cell array being accessed when a predetermined address of the normal memory cell array is actually accessed. And outputs second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed. Means.

The semiconductor memory according to the present invention includes a normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a memory cell array when the address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address of the spare memory cell array; and an address bit data indicating a predetermined address of the spare memory cell array when the predetermined address of the spare memory cell array is actually accessed. Means for outputting data.

The semiconductor memory according to the present invention includes a normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a memory cell array when the address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array in place of the defective address, and a predetermined address of the normal memory cell array being accessed when a predetermined address of the normal memory cell array is actually accessed. And outputs second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed. Means to
Means for outputting address bit data indicating a predetermined address of the spare memory cell array when a predetermined address of the spare memory cell array is actually accessed.

A semiconductor memory test method according to the present invention is characterized in that when an address signal specifies a defective address of a normal memory cell array, a redundancy circuit for specifying a predetermined address of a spare memory cell array instead of the defective address of the normal memory cell array. The first recognition bit data is output when a predetermined address of the normal memory cell array is accessed, and the second recognition bit data is output when a predetermined address of the spare memory cell array is accessed. When the first recognition bit data is output when an address signal designating a defective address of the normal memory cell array is supplied and the defective address of the normal memory cell array is Correct switching to the specified address in the spare memory cell array If the second recognition bit data is output, it is determined that the defective address of the normal memory cell array has been correctly switched to the predetermined address of the spare memory cell array. is there.

A semiconductor memory test method according to the present invention is characterized in that when an address signal specifies a defective address of a normal memory cell array, a redundancy circuit for specifying a predetermined address of a spare memory cell array instead of the defective address of the normal memory cell array. When a predetermined address of the spare memory cell array is accessed, address bit data indicating the predetermined address is set to be output, and a defective address of the normal memory cell array is designated. When an address signal is supplied, a predetermined address of the spare memory cell array is recognized by detecting the address bit data.

A semiconductor memory test method according to the present invention is characterized in that, when an address signal specifies a defective address of a normal memory cell array, a redundancy circuit for specifying a predetermined address of a spare memory cell array instead of the defective address of the normal memory cell array. The first recognition bit data is output when a predetermined address of the normal memory cell array is accessed, and the second recognition bit data is output when a predetermined address of the spare memory cell array is accessed. And setting the address bit data indicating the predetermined address to be output and outputting the first recognition bit data when an address signal designating a defective address of the normal memory cell array is supplied. Indicates that the defective address of the normal memory cell array is When it is determined that the address has not been properly switched to the predetermined address of the memory cell array, and the second recognition bit data is output, the defective address of the normal memory cell array has been correctly switched to the predetermined address of the spare memory cell array. And a predetermined address of the spare memory cell array is recognized by detecting the address bit data.
That is.

[0070]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a semiconductor memory according to the first embodiment of the present invention.

This semiconductor memory has 128 addresses (00 to 7F), that is, 32 row addresses (R0 to R3).
1) and four column addresses (C0 to C3),
One address corresponds to 8-bit data.
It is assumed that the normal memory cell array 11 of 24 bits is provided.

It is assumed that spare memory cell array 13 is arranged at the end of normal memory cell array 11 in the column direction (the direction in which the data lines extend).

The semiconductor memory is a DRAM, SRA
M or a volatile semiconductor memory such as a mask R
A nonvolatile semiconductor memory such as an OM, an EPROM, and an EEPROM may be used.

A row decoder 12 is arranged at one of two ends of the normal memory cell array 11 in the row direction (the direction in which the word lines R0 to R31 extend). The row decoder 12 selects one row based on a row address signal, and supplies a high potential to the selected row.

A spare memory cell array 13 is arranged at one of two ends of the normal memory cell array 11 in the column direction (the direction in which the data lines extend).

The spare memory cell array 13 includes, for example, 1
6 addresses (00 to 0F), that is, four row addresses (r0 to r3) and four column addresses (C0 to C3)
It is assumed that one address consists of 128 bits corresponding to 8-bit data.

The selection circuits 14 a to 14 d are arranged between the spare memory cell array 13 and the read circuit 16. The column decoder 15 selects one selection circuit, that is, one column, based on the column address, and guides data of the selected column to the reading circuit 16.

The address register 17 divides an address signal supplied from outside or inside the LSI chip on which the semiconductor memory is formed into a row address signal and a column address signal.

The memory cell switching circuit 18 has a storage unit for storing a defective row address of the normal memory cell array 11. This storage unit is composed of, for example, a plurality of fuses.
This is performed by cutting a predetermined fuse of the plurality of fuses with a laser.

When a row address is stored in the storage unit of the memory cell switching circuit 18 and the row address output from the address register 17 matches the row address of the storage unit of the memory cell switching circuit 18, The switching circuit 18 includes the row decoder 12.
(Inhibition) is output.

At the same time, the memory cell switching circuit 18
One row of the spare memory cell array 13 is selected, and a high potential is supplied to the selected row. As a result, the defective row of the normal memory cell array 11 is switched to a predetermined row of the spare memory cell array.

In the normal memory cell array 11,
The other one of the two ends is provided with a recognition bit unit 19. The recognition bit unit 19 has one storage unit that can store 1-bit data (“0” or “1”) corresponding to one row R0 to R31 of the normal memory cell array 11.

For example, data "0" is stored in each storage unit. When a high potential is supplied to a predetermined row (word line) R0 to R31 of the normal memory cell array 11, data "0" is stored in a storage unit corresponding to the predetermined row.
Is output.

This storage section can be composed of a MOS transistor, a nonvolatile semiconductor memory or the like.

2 in the row direction of spare memory cell array 13
Of the two ends, the recognition bit section 20 is disposed at the end on the same side as the side where the recognition bit section 19 is provided.
The recognition bit section 20 stores 1-bit data ("0") corresponding to one row r0 to r3 of the spare memory cell array 13.
Or "1").

For example, data "1" (data opposite to the data in the storage unit of the recognition bit unit 19) is stored in each storage unit. When a high potential is supplied to predetermined rows (word lines) r0 to r3 of the spare memory cell array 13, data "1" is output from the storage unit corresponding to the predetermined row.

This storage section can be composed of a MOS transistor, a nonvolatile semiconductor memory, or the like.

The data read from the recognition bit sections 19 and 20 is output by a bit data read circuit 22 to the outside of the LSI chip on which the semiconductor memory of the present invention is formed.

2 in the row direction of spare memory cell array 13
Of the two ends, an address bit section 21 is arranged at the end on the same side as the side where the recognition bit section 20 is provided. The address bit unit 21 is used for the spare memory cell array 1
There is one storage unit that can store 2-bit data (“00”, “01”, “10”, or “11”) corresponding to one of the three rows r0 to r3.

When the number of rows in the spare memory cell array is 2 ⁿ , the number of bits in the storage section of the address bit section 21 is n.

Each storage unit stores different data. When a high potential is supplied to predetermined rows (word lines) r0 to r3 of the spare memory cell array 13,
The predetermined data "00", "01", "10" or "1" corresponding to the row from the storage unit corresponding to the predetermined row.
1 "is output.

This storage unit can be composed of a MOS transistor, a nonvolatile semiconductor memory, or the like.

The data read from the address bit section 21 is output by a bit data read circuit 22 to the outside of the LSI chip on which the semiconductor memory of the present invention is formed.

FIG. 2 shows the recognition bit units 19 and 20 of FIG.
Address bit section 21 and bit data read circuit 2
2 shows an example of the configuration of FIG.

The source of the recognition bit section 19 is the power supply terminal 3.
It is composed of 32 N-channel type MOS transistors T0 to T31 connected to 1. The high potential VDD is applied to the power supply terminal 31. The gates of the MOS transistors T0 to T31 are connected to the normal memory cell array 1
It is connected to one predetermined word line R0 to R31. The drains of the MOS transistors T0 to T31 are connected to the inverter I0 of the bit data read circuit 22.

The source of the recognition bit section 20 is
2 comprises four N-channel MOS transistors Q0 to Q3. The low potential VSS is applied to the power supply terminal 32. Each MOS transistor Q
The gates 0 to Q3 are connected to one predetermined word line r0 to r3 of the spare memory cell array 13. MOS
The drains of the transistors Q0 to Q3 are connected to the inverter I0 of the bit data read circuit 22.

The address bit section 21 includes an N-channel MOS transistor Q whose source is connected to the power supply terminal 31.
00, Q01, Q10, Q21 and the source is the power supply terminal 3.
N-channel MOS transistor Q1 connected to
1, Q20, Q30 and Q31.

Gate of MOS transistors Q00 and Q01
Is connected to a predetermined word line r0 of the spare memory cell array 13, and MOS transistors Q10, Q11
Is connected to a predetermined word line r1 of the spare memory cell array 13, and the MOS transistors Q20,
The gate of Q21 is connected to a predetermined one word line r2 of the spare memory cell array 13, and the MOS transistor Q
Gates 30 and Q31 are connected to one predetermined word line r3 of the spare memory cell array 13.

MOS transistors Q00, Q10, Q2
The drains of 0 and Q30 are the bit data read circuit 2
2 inverter I1 and the MOS transistor Q
The drains of 01, Q11, Q21 and Q31 are connected to the inverter I2 of the bit data read circuit 22.

FIG. 3 shows the recognition bit units 19 and 20 of FIG.
Address bit section 21 and bit data read circuit 2
13 shows another example of the configuration of FIG.

In this embodiment, the input terminals of the inverters I0 to I2 of the bit data read circuit 22 and the power supply terminal 3
By arranging the resistors RE0 to RE2 between the MOS transistors 1, the N-channel MOS transistors of FIG. 2 whose source is connected to the power supply terminal 31 are omitted.

In this case, the recognition bit section 19 comprises a resistor RE0 connected between the input terminal of the inverter I0 of the bit data read circuit 22 and the power supply terminal 31.

The address bit section 21 includes a resistor RE1 connected between the input terminal of the inverter I1 of the bit data read circuit 22 and the power supply terminal 31, and an inverter I2 of the bit data read circuit 22. Input terminal and power terminal 3
1 and an N-channel MOS transistor Q whose source is connected to the power supply terminal 32.
An N-channel MOS transistor composed of 11, Q20, Q30, and Q31 and having a source connected to the power supply terminal 31 is omitted.

The gate of MOS transistor Q11 is connected to word line r1 of spare memory cell array 13, and
The gate of the OS transistor Q20 is connected to the word line r2 of the spare memory cell array 13, and the gate of the MOS transistors Q30 and Q31 is connected to the spare memory cell array 1.
3 is connected to the third word line r3.

The drains of the MOS transistors Q20 and Q30 are connected to the inverter I of the bit data read circuit 22.
1 and the drains of the MOS transistors Q11 and Q31 are connected to the inverter I2 of the bit data read circuit 22.

The configuration of the recognition bit unit 20 is not different from that of FIG.

That is, the recognition bit section 20 is composed of four N-channel MOS transistors Q0 to Q3 whose sources are connected to the power supply terminal 32. The low potential VSS is applied to the power supply terminal 32.

The gates of the MOS transistors Q0 to Q3 are connected to one predetermined word line r0 to r3 of the spare memory cell array 13. MOS transistor Q0
The drains of .about.Q3 are connected to the inverter I0 of the bit data read circuit 22.

When all the MOS transistors of the recognition bit section 20 are off, a high potential is input to the inverter I0, and the inverter I0 outputs recognition bit data "0". When at least one MOS transistor of the recognition bit unit 20 is on, the inverter I
Since a low potential is input to 0, the inverter I0 is
The recognition bit data "1" is output.

Similarly, for example, when all the MOS transistors of the address bit section 21 are off (row r0
Is selected), a high potential is input to the inverters I1 and I2, so that the inverters I1 and I2 output address bit data "0".

In a semiconductor memory provided with the above-mentioned redundancy circuit (part of the spare memory cell array 13 and the memory cell switching circuit 18), after the operation test of the semiconductor memory is completed, a defective row exists in the normal memory cell array 11. If there is, the storage section of the memory cell switching circuit 18 stores the address of the defective row.

After storing the defective row address,
Before shipment of the product, a shipment test is performed to check whether the defective row of the normal memory cell array 11 has been properly switched to a predetermined row of the spare memory cell array 13.

This shipping test is performed as follows.

As a precondition, as shown in Table 1, a defect exists in the memory cells at addresses 1C to 1F of the normal memory cell array 11, and the memory cells at addresses 1C to 1F are replaced with the address 00 of the spare memory cell array. ~ 0
3 memory cells.

That is, it is assumed that defective addresses 1C to 1F are stored in the storage section of the memory cell switching circuit 18.

[0117]

[Table 1]

First, for example, when the address 00 is supplied, the row decoder 12 selects the row (word line) R0 of the normal memory cell array 11, and supplies a high potential to this row R0. When a high potential is supplied to the row R0 of the normal memory cell array 11, data "0" (attention: high potential VDD) is output from the recognition bit section 19, and the bit data read circuit 22 recognizes the data. Bit data "0"
(Low potential VSS).

That is, the recognition bit data "0" is set to LS
By recognizing with a tester outside the I chip, it can be grasped that a predetermined row of the normal memory cell array 11 has been selected.

Next, for example, when the address 1C is supplied, the memory cell switching circuit 18 makes the row decoder 12
Is deactivated, and the row (word) of the spare memory cell array 13 is deactivated.
Line r0), and a high potential is supplied to the row r0. When a high potential is supplied to the row r0 of the spare memory cell array 13, data "1" (attention: low potential VSS) is output from the recognition bit unit 20, so that the bit data read circuit 22 recognizes the data. Bit data "1" (high potential V
DD).

That is, this recognition bit data "1" is
By recognizing with a tester outside the I chip, it can be understood that the defective row of the normal memory cell array 11 is properly switched to a predetermined row of the spare memory cell array 13.

If the bit data read circuit 22 outputs the recognized bit data "0" at this time, the defective row of the normal memory cell array 11 is properly switched to the predetermined row of the spare memory cell array 13. Can understand that it is not.

When the address 1C is supplied, a high potential is supplied to the row r0 of the spare memory cell array 13, so that the data "00" is supplied from the address bit section 21.
Is output. This address bit data "00" is
The data is output to the outside of the LSI chip by the bit data read circuit 22.

That is, the address bit data "0"
By recognizing “0” by a tester outside the LSI chip, it is possible to know which row of the spare memory cell array 13 has been replaced with the defective row of the normal memory cell array 11.

FIG. 4 shows a semiconductor memory according to the second embodiment of the present invention.

This semiconductor memory has 128 addresses (00 to 7F), that is, 32 row addresses (R0 to R3).
1) and four column addresses (C0 to C3),
One address corresponds to 8-bit data.
It is assumed that the normal memory cell array 11 of 24 bits is provided.

The spare memory cell array 23 is arranged at the end of the normal memory cell array 11 in the row direction (the direction in which the word line extends).

The semiconductor memory is a DRAM, SRA
M or a volatile semiconductor memory such as a mask R
A nonvolatile semiconductor memory such as an OM, an EPROM, and an EEPROM may be used.

A row decoder 12 is arranged at one of the two ends of the normal memory cell array 11 in the row direction (the direction in which the word lines R0 to R31 extend). The row decoder 12 selects one row based on a row address signal, and supplies a high potential to the selected row.

2 in the row direction of the normal memory cell array 11
A spare memory cell array 23 is arranged at the other one of the ends.

The spare memory cell array 23 includes, for example, 6
4 addresses (00-3F), that is, 32 row addresses (R0-R31) and two column addresses (c0, c
1), and one address is composed of 512 bits corresponding to 8-bit data.

The selection circuits 14a to 14f are arranged at one of two ends of the normal memory cell array 11 and the spare memory cell array 13. Column decoder 15
Are selected based on the column address.
d, one of the selection circuits, that is, one column is selected, and the data of the selected column is read out by the read circuit 16.
Lead to.

The address register 17 divides an address signal supplied from outside or inside the LSI chip on which the semiconductor memory is formed into a row address signal and a column address signal.

The memory cell switching circuit 18 has a storage unit for storing a defective column address of the normal memory cell array 11. This storage unit, for example,
It is composed of a plurality of fuses, and the storage of the column address is performed by cutting a predetermined fuse out of the plurality of fuses with a laser.

When a column address is stored in the storage unit of the memory cell switching circuit 18 and the column address output from the address register 17 matches the column address of the storage unit of the memory cell switching circuit 18, The switching circuit 18 is a column deco
A signal INH (inhibitio) for inactivating the
n) is output.

At the same time, the memory cell switching circuit 18
One column of the spare memory cell array 23, that is, one of the selection circuits 14e and 14f is selected, and the data of the selected column is led to the read circuit 16. As a result, the defective column of the normal memory cell array 11 is switched to a predetermined column of the spare memory cell array 23.

Selection circuit 14 of normal memory cell array 11
Recognition bit units 19 are arranged corresponding to a to 14d. The recognition bit section 19 is provided for the normal memory cell array 11.
Has one storage unit capable of storing 1-bit data ("0" or "1") corresponding to one column C0 to C3.

For example, data “0” is stored in each storage unit. When a predetermined column C0 to C3 of the normal memory cell array 11 is selected, data "0" is output from the storage unit corresponding to the predetermined column.

This storage section can be composed of a MOS transistor, a nonvolatile semiconductor memory or the like.

Selection circuit 14 of spare memory cell array 23
Recognition bit units 20 are arranged corresponding to e and 14f. The recognition bit section 20 includes a spare memory cell array 23
One column c0, c1 has one storage unit capable of storing 1-bit data ("0" or "1").

For example, data "1" (data opposite to the data in the storage unit of the recognition bit unit 19) is stored in each storage unit. When a predetermined column c0, c1 of the spare memory cell array 23 is selected, data "1" is output from the storage section corresponding to the predetermined column.

This storage section can be composed of a MOS transistor, a nonvolatile semiconductor memory, or the like.

The data read from the recognition bit units 19 and 20 are output by a bit data read circuit 22 to the outside of the LSI chip on which the semiconductor memory of the present invention is formed.

Selection circuit 14 of spare memory cell array 23
Address bit portions 21 are arranged corresponding to e and 14f. The address bit unit 21 has one storage unit that can store 1-bit data (“0” or “1”) corresponding to one column c0, c1 of the spare memory cell array 23.

When the number of columns in the spare memory cell array is 2 ⁿ , the number of bits in the storage section of the address bit section 21 is n.

Each storage unit stores different data. When a predetermined column c0, c1 of the spare memory cell array 23 is selected, predetermined data "0" or "1" corresponding to the column is output from the storage unit corresponding to the predetermined column. .

This storage section can be composed of a MOS transistor, a nonvolatile semiconductor memory or the like.

Data read from the address bit section 21 is output by a bit data read circuit 22 to the outside of the LSI chip on which the semiconductor memory of the present invention is formed.

FIG. 5 shows the recognition bit units 19 and 20 of FIG.
Address bit section 21 and bit data read circuit 2
2 shows an example of the configuration of FIG.

The source of the recognition bit section 19 is the power supply terminal 3.
It is composed of four N-channel type MOS transistors TC0 to TC3 connected to 1. The high potential VDD is applied to the power supply terminal 31. The gates of the MOS transistors TC0 to TC3 are connected to column selection lines C0 to C3 for selecting a predetermined column of the normal memory cell array 11.
It is connected to the. MOS transistors TC0 to TC3
Is connected to the inverter I0 of the bit data read circuit 22.

The source of the recognition bit section 20 is the power supply terminal 3.
2 is composed of two N-channel type MOS transistors QC0 and QC1. The low potential VSS is applied to the power supply terminal 32. The gates of the MOS transistors QC0 and QC1 are connected to column selection lines c0 and c1 for selecting a predetermined column of the spare memory cell array 23.
It is connected to the. MOS transistors QC0, QC1
Is connected to the inverter I0 of the bit data read circuit 22.

The address bit portion 21 includes an N-channel MOS transistor Q having a source connected to the power supply terminal 31.
C00 and an N-channel MOS transistor QC11 whose source is connected to the power supply terminal 32.

The gate of the MOS transistor QC00 is
The MOS transistor QC11 is connected to a column selection line c0 for selecting the column c0 of the spare memory cell array 23.
Are connected to a column selection line c1 for selecting a column c1 of the spare memory cell array 23.

The drains of the MOS transistors Q00 and Q11 are connected to the inverter I of the bit data read circuit 22.
1 connected.

FIG. 6 shows the recognition bit units 19 and 20 of FIG.
Address bit section 21 and bit data read circuit 2
13 shows another example of the configuration of FIG.

In this embodiment, the input terminals of the inverters I0 and I1 of the bit data read circuit 22 and the power supply terminal 3
By arranging the resistors RE0 and RE1 between the power supply terminals 1, the N-channel MOS transistors of FIG. 5 whose source is connected to the power supply terminal 31 are omitted.

In this case, the recognition bit section 19 comprises a resistor RE0 connected between the input terminal of the inverter I0 of the bit data read circuit 22 and the power supply terminal 31.

The address bit section 21 has a resistor RE1 connected between the input terminal of the inverter I1 of the bit data read circuit 22 and the power supply terminal 31, and a source connected to the power supply terminal 32. An N-channel MOS transistor composed of an N-channel MOS transistor QC11 and having a source connected to the power supply terminal 31 is omitted.

The gate of the MOS transistor QC11 is
It is connected to a column selection line c1 for selecting a column c1 of the spare memory cell array 23. MOS transistor QC1
The drain of 1 is connected to the inverter I1 of the bit data read circuit 22.

The configuration of the recognition bit unit 20 is not different from that of FIG.

That is, the recognition bit section 20 is composed of two N-channel MOS transistors QC0 and QC1 whose sources are connected to the power supply terminal 32. Power terminal 3
2, a low potential VSS is applied.

The gates of the MOS transistors QC0 and QC1 are connected to column selection lines c0 and c1 for selecting one predetermined column of the spare memory cell array 23. The drains of the MOS transistors QC0 and QC1
It is connected to the inverter I0 of the bit data read circuit 22.

When all the MOS transistors of the recognition bit section 20 are off, a high potential is input to the inverter I0, and the inverter I0 outputs recognition bit data "0". When at least one MOS transistor of the recognition bit unit 20 is on, the inverter I
Since a low potential is input to 0, the inverter I0 is
The recognition bit data "1" is output.

Similarly, for example, when the MOS transistor QC11 of the address bit section 21 is off (when the column c0 is selected), a high potential is input to the inverter I1. Outputs address bit data "0".

In the semiconductor memory provided with the redundancy circuit (part of the spare memory cell array 23 and the memory cell switching circuit 18), after the operation test of the semiconductor memory is completed, a defective column exists in the normal memory cell array 11. If there is, the storage section of the memory cell switching circuit 18 stores the address of the defective column.

After storing the defective column address, before shipment of the product, the shipment for checking whether the defective column of the normal memory cell array 11 has been properly switched to the predetermined column of the spare memory cell array 23 or not. A test is performed.

The shipping test is performed as follows.

As a precondition, as shown in Table 2, addresses 01, 05,
It is assumed that there is a defect in the memory cells in the columns 09,... 7D, and the memory cells in this column are switched to the memory cells in the columns of addresses 00, 02, 03,.

That is, in the storage section of the memory cell switching circuit 18, defective column addresses 01, 05, 09,...
It is assumed that D is stored.

[0170]

[Table 2]

First, for example, when the address 00 is supplied, the column decoder 15 starts the normal memory cell array 11
And a high potential is supplied to the column selection line C0. Column select line C0 of normal memory cell array 11
Is supplied with a high potential, the recognition bit unit 19 outputs data.
Since the data "0" (attention: high potential VDD) is output, the bit data read circuit 22 outputs the recognition bit data "0" (low potential VSS).

That is, this recognition bit data "0" is
By recognizing with a tester outside the I chip, it is possible to know that a predetermined column of the normal memory cell array 11 has been selected.

Next, for example, when the address 01 is supplied, the memory cell switching circuit 18 makes the column decoder 1
5 is deactivated, and the column c of the spare memory cell array 23 is deactivated.
0 is selected, and a high potential is supplied to the column selection line c0 of this column. Column select line c of spare memory cell array 23
When a high potential is supplied to 0, data "1" (attention: low potential VSS) is output from the recognition bit unit 20.
The bit data read circuit 22 outputs recognition bit data "1" (high potential VDD).

That is, this recognition bit data "1" is
By recognizing with a tester outside the I chip, it can be understood that a defective column of the normal memory cell array 11 is properly switched to a predetermined column of the spare memory cell array 23.

At this time, if the bit data read circuit 22 outputs the recognized bit data "0", the defective column of the normal memory cell array 11 is properly switched to the predetermined column of the spare memory cell array 23. Can understand that it is not.

When the address 01 is supplied, since a high potential is supplied to the column selection line c0 of the spare memory cell array 23, data "0" is output from the address bit portion 21 (note: high potential VDD). ) Is output. The bit data read circuit 22 outputs the address bit data "0".
(Low potential VSS) is output outside the LSI chip.

That is, this address bit data "0"
Is recognized by a tester outside the LSI chip, it is possible to know which column of the spare memory cell array 23 the defective column of the normal memory cell array 11 has been switched to.

[0178]

As described above, according to the semiconductor memory of the present invention, the following effects can be obtained.

When a row redundancy circuit is provided for repairing memory cells in the row direction (the direction in which word lines extend), a recognition bit portion indicating that a predetermined row of the normal memory cell array has been selected, and a spare memory Providing a recognition bit portion indicating that a predetermined row of the cell array is selected,
Further, there is provided a reading circuit for outputting data output from these recognition bit portions.

Therefore, after performing the repair of the memory cell by the redundancy circuit, the normal operation test is performed at the time of the shipping test, whereby the defective row of the normal memory cell array is properly switched to the predetermined row of the spare memory cell array. Can be easily inspected.

When a predetermined row of the spare memory cell array is selected, an address bit portion for outputting an address specific to the row is provided for each row of the spare memory cell array.

Therefore, when a predetermined row of the spare memory cell array is selected, it is possible to easily know which row has been selected.

Even when a row redundancy circuit is provided for repairing memory cells in the column direction (the direction in which the data lines extend), a recognition bit portion indicating that a predetermined column of the normal memory cell array has been selected, Recognition bit sections each indicating that a predetermined column of the spare memory cell array has been selected are provided, and a readout circuit for outputting data output from these recognition bit sections is provided.

Therefore, after performing the repair of the memory cells by the redundancy circuit, the normal operation test is performed at the time of the shipping test, whereby the defective column of the normal memory cell array is properly switched to the predetermined column of the spare memory cell array. Can be easily inspected.

When a predetermined column of the spare memory cell array is selected, an address bit section for outputting an address unique to the column is provided for each column of the spare memory cell array.

Therefore, when a predetermined column of the spare memory cell array is selected, it can be easily grasped which column has been selected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a recognition bit section, an address bit section, and a read circuit of FIG. 1;

FIG. 3 is a diagram showing a configuration of a recognition bit unit, an address bit unit, and a read circuit of FIG. 1;

FIG. 4 is a diagram showing a semiconductor memory according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a recognition bit unit, an address bit unit, and a read circuit of FIG. 4;

FIG. 6 is a diagram showing a configuration of a recognition bit unit, an address bit unit, and a read circuit of FIG. 4;

FIG. 7 is a diagram showing a conventional semiconductor memory.

[Explanation of symbols]

11: normal memory cell array, 12: row decoder, 13, 23: spare memory cell array, 14a to 14f: selection circuit, 15: column decoder, 16: read circuit, 17: address register, 18: memory cell switching circuit, 19, 20: recognition bit portion, 21: address bit portion, 22: bit data read circuit, 31, 32: power supply terminal, T0 to T31, Q0 to Q3, Q00, Q01, Q10,
Q11, Q20, Q21, Q30, Q31, TC0-T
C3, QC0, QC1, QC00, QC11: N-channel MOS transistors, I0 to I2: inverters, RE0 to RE2: resistors, R0 to R31, r0 to r3: rows (word lines), C0 to C3 c0, c1: columns (column selection lines).

Claims (25)

[Claims] 1. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a substitute for a defective address of the normal memory cell array when an address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for specifying a predetermined address of the spare memory cell array, and a first recognition indicating that the predetermined address of the normal memory cell array has been accessed when the predetermined address of the normal memory cell array is actually accessed. A recognition bit section for outputting bit data and outputting second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed; Before output from the recognition bit portion A bit data reading circuit for reading the first or second recognition bit data. 2. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a substitute for a defective address of the normal memory cell array when an address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array, and outputting address bit data indicating a predetermined address of the spare memory cell array when the predetermined address of the spare memory cell array is actually accessed. A semiconductor memory comprising: an address bit portion; and a bit data read circuit for reading the address bit data output from the address bit portion. 3. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and a replacement of the normal memory cell array with a defective address when an address signal specifies a defective address of the normal memory cell array. A memory cell switching circuit for specifying a predetermined address of the spare memory cell array, and a first recognition indicating that the predetermined address of the normal memory cell array has been accessed when the predetermined address of the normal memory cell array is actually accessed. A recognition bit section for outputting bit data and outputting second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed; A predetermined address of the spare memory cell array. An address bit section for outputting address bit data indicating a predetermined address of the spare memory cell array when the address is actually accessed; and the first or second recognition bit data output from the recognition bit section. And bit data for reading the address bit data output from the address bit portion.
A semiconductor memory comprising a data read circuit. 4. The spare memory cell array includes one of two ends in a column direction of the normal memory cell array.
And the recognition bit portion is provided in the row direction of the normal memory cell array and the spare memory cell array.
4. The semiconductor memory according to claim 1, wherein the semiconductor memory is arranged at one of the two ends. 5. The normal memory cell array, wherein the recognition bit unit has a first storage unit for storing the first recognition bit data and a second storage unit for storing the second recognition bit data. When the predetermined row is actually accessed, the first recognition bit data is output from the first storage unit, and when the predetermined row of the spare memory cell array is actually accessed, the second recognition bit data is output. 5. The semiconductor memory according to claim 4, wherein said second recognition bit data is output from a storage unit. 6. The first storage section has a source connected to a first power supply terminal, a gate connected to a predetermined row of the normal memory cell array, and a drain connected to the test mode read circuit. The second storage unit has a source connected to a second power supply terminal,
6. The semiconductor memory according to claim 5, wherein a gate is connected to a predetermined row of said spare memory cell array, and a drain comprises a plurality of MOS transistors connected to said bit data read circuit. 7. The first storage section comprises a resistor connected between the test mode readout circuit and a first power supply terminal. The second storage section has a source connected to a second power supply terminal. Connected to
6. The semiconductor memory according to claim 5, wherein a gate is connected to a predetermined row of said spare memory cell array, and a drain comprises a plurality of MOS transistors connected to said bit data read circuit. 8. The spare memory cell array includes one of two ends in a column direction of the normal memory cell array.
4. The semiconductor memory according to claim 2, wherein the address bit portion is disposed at one of two ends in a row direction of the spare memory cell array. 5. 9. The address bit section has a storage section for storing address bit data indicating an address of each row of the spare memory cell array, and a predetermined row of the spare memory cell array is actually accessed. 9. The semiconductor memory according to claim 8, wherein in the case, address bit data indicating an address corresponding to the predetermined row is output from the storage unit. 10. The storage section has a source connected to a first power supply terminal or a second power supply terminal, a gate connected to a predetermined row of the spare memory cell array, and a drain connected to the bit data readout. 10. The semiconductor memory according to claim 9, comprising a plurality of MOS transistors connected to a circuit. 11. The storage unit includes a resistor connected between the test mode readout circuit and a first power supply terminal, a source connected to a second power supply terminal, and a gate connected to the spare memory. 10. A plurality of MOS transistors connected to a predetermined row of the cell array and having a drain connected to the bit data read circuit.
The semiconductor memory according to any one of the preceding claims. 12. The spare memory cell array includes one of two ends of the normal memory cell array in a row direction.
A first selection circuit disposed at one of two ends of the normal memory cell array in the column direction for selecting a column of the normal memory cell array; And a second selection circuit for selecting a column of the spare memory cell array, wherein the recognition bit unit is disposed adjacent to the first and second selection circuits. The semiconductor memory according to claim 1, wherein: 13. The normal memory cell array, wherein the recognition bit section has a first storage section for storing the first recognition bit data and a second storage section for storing the second recognition bit data. When the predetermined column is actually selected, the first recognition bit data is output from the first storage unit, and when the predetermined column of the spare memory cell array is actually selected, the second recognition bit data is output. 13. The semiconductor memory according to claim 12, wherein said second recognition bit data is output from a storage unit. 14. The first storage section, wherein a source is connected to a first power supply terminal, a gate is connected to the first selection circuit, and a drain is connected to the test mode readout circuit. Wherein the second storage unit has a source connected to a second power supply terminal,
14. The gate of claim 13, wherein the gate is connected to the second selection circuit, and the drain is composed of a plurality of MOS transistors connected to the bit data read circuit.
The semiconductor memory according to any one of the preceding claims. 15. The first storage section comprises a resistor connected between the bit data read circuit and a first power supply terminal. The second storage section has a source connected to a second power supply terminal. Connected to
14. The gate of claim 13, wherein the gate is connected to the second selection circuit, and the drain is composed of a plurality of MOS transistors connected to the bit data read circuit.
The semiconductor memory according to any one of the preceding claims. 16. The spare memory cell array includes one of two ends of the normal memory cell array in a row direction.
A first selection circuit disposed at one of two ends of the normal memory cell array in the column direction for selecting a column of the normal memory cell array; And a second selection circuit for selecting a column of the spare memory cell array, wherein the address bit section is disposed adjacent to the second selection circuit. 4. The semiconductor memory according to claim 2, wherein: 17. The address bit section has a storage section for storing address bit data indicating an address of each column of the spare memory cell array, and a predetermined column of the spare memory cell array is actually accessed. 17. The semiconductor memory according to claim 16, wherein in the case, address bit data indicating an address corresponding to the predetermined column is output from the storage unit. 18. The storage section, wherein a source is connected to a first power supply terminal or a second power supply terminal, a gate is connected to the second selection circuit, and a drain is connected to the bit data read circuit. 18. The semiconductor memory according to claim 17, comprising a plurality of MOS transistors. 19. The storage section, wherein a resistor connected between the bit data read circuit and a first power supply terminal, a source is connected to a second power supply terminal, and a gate is connected to the second power supply terminal. 18. The semiconductor memory according to claim 17, further comprising a plurality of MOS transistors connected to the selection circuit and having a drain connected to the bit data read circuit. 20. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and, when an address signal specifies a defective address of the normal memory cell array, replacing the defective address of the normal memory cell array. A memory cell switching circuit for specifying a predetermined address of the spare memory cell array, and a first recognition indicating that the predetermined address of the normal memory cell array has been accessed when the predetermined address of the normal memory cell array is actually accessed. Means for outputting bit data and outputting second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed. A semiconductor memory characterized in that: 21. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and, when an address signal specifies a defective address of the normal memory cell array, replacing the defective address of the normal memory cell array. A memory cell switching circuit for designating a predetermined address of the spare memory cell array, and outputting address bit data indicating a predetermined address of the spare memory cell array when the predetermined address of the spare memory cell array is actually accessed. Semiconductor memory comprising: 22. A normal memory cell array, a spare memory cell array additionally provided to the normal memory cell array, and, when an address signal specifies a defective address of the normal memory cell array, replacing the defective address of the normal memory cell array. A memory cell switching circuit for specifying a predetermined address of the spare memory cell array, and a first recognition indicating that the predetermined address of the normal memory cell array has been accessed when the predetermined address of the normal memory cell array is actually accessed. Means for outputting bit data and outputting second recognition bit data indicating that a predetermined address of the spare memory cell array has been accessed when a predetermined address of the spare memory cell array is actually accessed; Predetermined address of spare memory cell array Means for outputting address bit data indicating a predetermined address of the spare memory cell array when the memory cell is actually accessed. 23. A method for testing a semiconductor memory comprising a redundancy circuit for designating a predetermined address of a spare memory cell array in place of the defective address of the normal memory cell array when the address signal specifies a defective address of the normal memory cell array. The first recognition bit data is output when a predetermined address of the normal memory cell array is accessed, and the second recognition bit data is output when a predetermined address of the spare memory cell array is accessed. When the first recognition bit data is output when an address signal designating a defective address of the normal memory cell array is supplied, the defective address of the normal memory cell array is replaced with a predetermined address of the spare memory cell array. It is determined that the And a step of determining that the defective address of the normal memory cell array has been correctly switched to a predetermined address of the spare memory cell array when the second recognition bit data is output. Method. 24. A method for testing a semiconductor memory comprising a redundancy circuit for designating a predetermined address of a spare memory cell array in place of a defective address of a normal memory cell array when an address signal specifies a defective address of the normal memory cell array. When a predetermined address of the spare memory cell array is accessed, address bit data indicating the predetermined address is set to be output, and an address signal specifying a defective address of the normal memory cell array is supplied. The address bit data
A test method for a semiconductor memory, wherein a predetermined address of the spare memory cell array is recognized by detecting data. 25. A test method for a semiconductor memory comprising a redundancy circuit for designating a predetermined address of a spare memory cell array in place of the defective address of the normal memory cell array when the address signal specifies a defective address of the normal memory cell array. When a predetermined address of the normal memory cell array is accessed, first recognition bit data is output, and when a predetermined address of the spare memory cell array is accessed, second recognition bit data and an address indicating the predetermined address. When the bit data is set to be output and an address signal designating a defective address of the normal memory cell array is supplied, and when the first recognition bit data is output, the normal memory cell array is output. If the defective address is in the spare memory cell array, When it is determined that the address has not been properly switched to the fixed address, and when the second recognition bit data is output, it is determined that the defective address of the normal memory cell array has been correctly switched to the predetermined address of the spare memory cell array. A semiconductor memory test method for recognizing a predetermined address of the spare memory cell array by detecting the address bit data.