JP2002288049A - Separation method of pci bus failure position and program thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a continuous operability of a system by starting up the system by logically separating an abnormal PCI device/PCI function on a PCI bus. SOLUTION: When a PCI configuration cycle execution part 1 is successively configured, PCI device number/device number/function number at an access side are successively stored in an access address storage area 2. When an abnormality exists during the execution of the configuration, a WDT circuit 4 counts up to wake up-reset all PCI device/PCI function. The PCI configuration cycle execution part 1 cuts off the abnormal PCI device/PCI function in reference to a table 3, a configuration is executed for the remained PCI device/PCI function and the system is started if an abnormality does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of isolating a defective portion of a PCI bus conforming to a PCI bus specification, and particularly to a method of adding a PCI bus to a PCI bus without adding H / W.
The system is started up by logically separating the defective device / function on the CI bus to improve the continuous operation of the system.

[0002]

2. Description of the Related Art FIG.
FIG. 3 is a configuration diagram illustrating a PCI bus processing device disclosed in Japanese Patent Publication No. 3 (JP-A) No. 3; In the figure, reference numeral 20 denotes a PCI bus processing device,
Reference numeral 21 denotes a transaction start detection circuit for detecting the start of a transaction on the PCI bus, and inputs a FRAME # of a PCI bus signal. Reference numeral 22 denotes a holding register for holding information on an address / data line and a command / byte enable line on the PCI bus, reference numeral 23 denotes an abnormality detection circuit for detecting an abnormality on the PCI bus, and reference numeral 24 denotes whether or not it is valid. A storage register which has a valid bit and stores an address and command information when an error occurs. A PCI bus interface 25 inputs all PCI bus signals.

Next, the operation will be described. (1) When a bus master on the PCI bus starts a transaction on the PCI bus, a transaction start detection circuit in the PCI bus processing device 20 detects the start of the transaction and notifies the holding register 22 that the address / address Stores command information. (2) Next, the abnormality detection circuit 23 monitors the transaction on the PCI bus, and when an abnormality is detected, the holding register 22
Is stored in the storage register 24 and
Enable dbit.

(3) Then, the host CPU (not shown) receiving the report of the abnormality on the PCI bus,
The storage register 24 in 0 is read via the PCI bus. (4) The PCI bus interface 25 in the PCI bus processing device 20 receives the PCI read transaction from the host CPU, and returns the value of the storage register 24 to the host CPU only when validbit is valid. On the other hand, v
"FFFFFFFFh" when the valid bit is invalid
return it.

[0005] Therefore, the address and command information at the time of occurrence of an error are configured to be output on the PCI bus by the PCI bus interface. Therefore, when an error occurs, the host CPU identifies an abnormal PCI function and an abnormal PCI device based on the error occurrence address. Identify and isolate the location where the error occurred.

[0006]

Since the location of an abnormality is identified by the conventional PCI bus processing device as described above, it is necessary to add a special H / W circuit for analyzing a PCI transaction. Was.

In order to connect a circuit on a PCI bus,
There has been a problem that the electrical load on the PCI bus occupies one expansion slot of the PCI bus.

When a PCI configuration cycle is executed for an abnormal PCI device / function from the beginning, a retry indicating incomplete initialization is repeated endlessly from the PCI device / function. Since the PCI bus itself is normal as a PCI transaction, it cannot be detected by a conventional PCI bus processing device, and there is a problem that an abnormal part cannot be specified even as a host CPU.

[0009]

According to a first aspect of the present invention, there is provided a method of isolating a defective portion of a PCI bus, comprising a host CPU function and a PCI function having a built-in PCI function.
If an error occurs when the PCI function or the PCI device is configured in a system in which the device is connected via the PCI bus, the PCI function or the PCI device that is the target of the error is separated from the system. The method includes the steps of:
A first step of sequentially executing a configuration for each function or each PCI device, and a second step of resetting all PCI functions or PCI devices if an abnormality occurs during the configuration.
And a third step of separating the PCI function or the PCI device in which the abnormality has occurred after the reset and sequentially executing the configuration for each of the remaining PCI functions or the respective PCI devices. This is performed using

(2) PCI according to the second aspect of the present invention
The method of isolating a defective bus portion according to claim 1 is the method of isolating a defective portion of a PCI bus according to claim 1, wherein after resetting in the second step, the method returns to the first step and returns to the first step again.
The program includes a fourth step in which the first and second steps are repeated at least once so as to configure the function or the PCI device, and if the abnormality is not eliminated, the process proceeds to the third step.

(3) The PCI according to the third aspect of the present invention.
Claim 1 or Claim 2 is a method of isolating a defective bus portion.
In the method for isolating the defective portion of the PCI bus, if the abnormality is not resolved even if the configuration is executed in the third step, the process returns to the second step and returns to all the PCI buses.
In order to reset the function or the PCI function, the program includes a fifth step of repeating the second and third steps a predetermined number of times or until the abnormality is resolved, and includes a plurality of abnormal PCI functions or PCI devices. It can be separated from the system.

(4) PCI according to the fourth aspect of the invention
The method of isolating a defective bus portion according to any one of claims 1 to 3, wherein
If the abnormality is not resolved even after performing the step, or if the abnormality is not resolved after a desired time after performing the third step, or any one of the first to third steps cannot be performed. If the host CPU
The sixth step for determining that the function is abnormal is included in the program.

(5) The PCI according to the fifth aspect of the present invention.
The program for executing the method of isolating a defective bus portion is a program for executing the method of isolating a defective portion of a PCI bus according to any one of claims 1 to 4.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram of a system having a PCI bus, 10 is a PCI bus, and a host CPU card 11.
And the add-in cards 12, 13, 14 are connected. The host CPU card 11 incorporates a host CPU 11a and various computer functions (not shown) such as a memory and an interface to form a host CPU function. Also, various necessary S / Ws 11b are built in, and software for the method of separating defective PCI bus portions according to the present invention is also built in. The add-in cards 12, 13 and 14 include, for example, PCI devices 12a,
13a and 14a are provided, and in these PCI devices, PCI functions 12b and
12c, 13b, 14b, and 14c are incorporated.

FIG. 2 shows a PC according to the first embodiment of the present invention.
FIG. 3 is a block diagram for realizing a method of isolating an I bus defective portion, in which 1 is a host C connected to a PCI bus;
A PCI configuration cycle execution unit that operates on a PU card and executes a PCI configuration cycle, and an access address (a combination of a PCI bus number / device number / function number) for executing a PCI configuration cycle from now on
3 is a function management table (see FIG. 6) for managing the logical separation of all functions. 4 is the host CP
A WDT circuit 5 for monitoring the normal operation of the CPU on the U card and the software running thereon is used. The WDT circuit 5 periodically operates the software when the CPU on the host CPU card and the software running thereon run normally. This register is a WDT clear register that writes data to the WD before the WDT counts up.
Clears the T counter value. If the operation of the CPU on the add-in card or the software running on it is abnormal, it appears as an abnormality in the CPU on the host CPU card and the software running on it, and as a result,
Writing to the DT clear register 5 stops. Therefore W
The DT circuit 4 also monitors the add-in card.

6 is activated when the WDT circuit 4 counts up, and a wake-up reset (W
A reset generation circuit 7 that issues an ake up reset) is a reset factor register that indicates whether a reset is released by power ON or a wakeup reset, and can be read from the PCI configuration cycle execution unit 1. The contents are stored in the memory of the access address storage area 2 and the memory of the function management table 3, and the contents are retained even if a wake-up reset is performed.

Next, the operation of the WDT circuit 4 will be described. 3 and 4 are diagrams illustrating an example of the movement of the counter value of the WDT circuit 4. FIG. (1) First, in FIG. 3A, the WDT circuit 4 starts counting when the power-on reset is released (time: T1). (2) The host CPU and the software running on the host CPU are operating normally, and the WDT counter is cleared by writing to the WDT clear register 5 by software before the WDT count-up. During this time, the configuration is completed and the system starts up.

(3) As shown in FIG. 3B, if there is an abnormality in a certain PCI function and the PCI configuration processing for the PCI function stops at time T2, the WDT clear register 5 Is stopped, and after the period P1, W
The DT counter value counts up, and since it is the first WDT count-up, execution of a wake-up reset is requested to the reset generation circuit 6, and the wake-up reset is executed by the reset generation circuit 6 (time: T
3). (4) The WDT circuit 4 starts counting again after the wake-up reset is released, but this time, the configuration to the abnormal PCI function is passed, so that the configuration is completed before the WDT count-up, and the WDT clear register 5
So the system starts up normally.

(5) When an abnormality occurs in the PCI function and the abnormality is not recovered, the writing to the WDT clear register 5 by the software remains stopped as shown in FIG. = P1), the WDT counter value is counted up again, and since this is the second consecutive WDT count up, it is determined that the function of the host CPU or the PCI bus itself, which is a common unit, has stopped, and an alarm signal is transmitted, for example. Then, an abnormality determination process is performed (time T5). (6) If the writing to the WDT clear register 5 is performed by software at least once during the period P2 as shown in FIG.
It is regarded as the first time and wake-up reset is performed. (Because the WDT clearing process has been performed during the period P2, it is not the second consecutive time.)

Next, the overall processing flow will be described.
FIG. 5 shows the PCI configuration cycle execution unit 1.
FIG. 2 is a flowchart showing an example of configuring each function on a PCI bus. First, a case where all PCI buses / devices / functions are normal and the reset factor is power ON will be described.

(1) The PCI configuration cycle execution section 1 reads the contents of the reset factor register 7 (step ST1-1), and (2) checks the reset factor of this time (step ST1-
2), (3) Since the reset cause is other than the wake-up reset due to WDT count-up, all function statuses in the function management table 3 are initialized to “0: normal” (step ST1-3), and (4) all PCIs Move on to bus / device / function configuration repetition processing (step ST
1-4), (5) Check the status of the target function to be configured during the current iteration (step S)
T1-5),

(6) Since there is no abnormality, the access address to be configured this time is stored in the access address storage area 2 (step ST1-6). (7) PCI configuration of the target function is executed (step ST1-7). (8) After completion, the access address storage area 2 is cleared (step ST1-8), and all PCI buses / devices / functions are repeatedly executed from step ST1-4 (step ST1-9) to complete all PCI configurations. (9) Write to the WDT clear register 5 before counting up the WDT (step ST1-10). (The value of the counter is determined so that the WDT does not count up even at normal termination.)

Next, PCI bus number = 0 / device number =
The flow from the power-on reset in a state where an abnormality has occurred at 1 / function number = 1 will be described. (1) Steps ST1-1 to ST1-6 are exactly the same as described above. (2) When the PCI configuration is performed for the PCI bus number = 0 / device number = 1 / function number = 1 (step ST1-7),

(3) In some cases, the PCI configuration cycle repeats the retry process indefinitely and does not end. (General-purpose PCI chipset and C
In the case of a PCI target card (add-in card) in which a PU is mounted and this general-purpose PCI chip is initialized by the S / W operating on the CPU, if an abnormality occurs such that the S / W does not operate properly, the PCI chip Does not complete initialization. In this case, the PC from the host CPU card
This may result in infinite repetition of the retry process for the I configuration cycle. ) As a result, the WDT clear register 5
Wake-up reset occurs because data cannot be written to

Next, the flow after the occurrence of the wake-up reset will be described. (1) PCI configuration cycle execution unit 1
Reads the contents of the reset cause register (step S
T1-1), (2) Investigate the current reset factor (step ST1-
2), (3) Since the reset factor is a wake-up reset due to WDT count-up, the access address storage area 2
(Step ST1-11), (4) check the stored contents (step ST1-12), and (5) clear the access address storage area 2 because the abnormal access address is stored (step ST1-12). After ST1-13)

(6) Based on the information accessed before the wake-up reset occurred, the PCI bus number = 0 / device number = 1 / function number = 1, the corresponding function status in the function management table 3 is set to " 1: abnormal "(step ST1-
14), (7) Shift to configuration repetition processing of all PCI buses / devices / functions (step ST)
1-4), (8) Check the status of the target function to be configured during the current repetition processing (step S)
T1-5),

(9) Since the function status of PCI bus number = 0 / device number = 1 / function number = 1 is set to "1: abnormal", PCI bus number = 0 / device number = 1 / function number =
1 is omitted, and all remaining PCI buses / devices / functions are repeatedly executed from step ST1-4 (step ST1-4).
The entire PCI configuration is completed according to 1-9), and (10) the WDT clear register 5 is written before the WDT count-up (step ST1-10).

(11) All remaining PCI buses / devices /
If a similar error occurs in another function during PCI configuration of the function, the PC
It stops in the I configuration process, and determines that the host CPU function has stopped after the second consecutive WDT count-up. In other words, only the disconnection processing of one PCI function that first detects an abnormality is performed, and when a plurality of PCI functions are abnormal, the host CP
It is determined that the function of the U or the PCI bus itself, which is a common unit, is stopped, and an alarm or the like is transmitted.

FIG. 6 shows that the PCI bus number = 0 / device number = 1 / function number = 1 causes an error and the PCI
7 shows an example of the function management table 3 after omitting the configuration processing.

As described above, the wake-up reset by the WDT count-up is provided so that the reset from the stop of the PCI configuration cycle processing for the abnormal function can be performed. Further, the access address storage area 2 and the function management table 3
As a result, the access destination (PCI bus number / device number /
A means for storing and holding the function number is provided, and the WDT clear processing is performed only after the completion of all the PCI configurations, so that one abnormal PCI function can be detected and the one PCI function can be logically separated. The continuous operability of the system in the part can be improved.

Further, it is not necessary to add a special H / W circuit for analyzing a PCI transaction.

Further, since no electrical load is imposed on the PCI bus, one PCI bus expansion slot is not occupied, so that the PCI bus expansion slot can be used effectively.

Embodiment 2 FIG. In the first embodiment, FIG.
In (a), after a wake-up reset by the first WDT count-up at time T3, abnormal P
Except for the CI function, the PCI configuration is executed for the remaining PCI functions. However, a transient abnormality occurs by chance due to the influence of noise or the like, and the normal PCI function may be regarded as abnormal. . In the second embodiment of the present invention, the PCI configuration is executed again for the PCI functions of all the addresses without removing the PCI functions of the abnormal addresses. That is, P in FIG.
The operation corresponding to the period 1 is repeated at least once, and thereafter, the process shifts to the process in the period P2.

Embodiment 3 Next, a third embodiment of the present invention will be described. The block diagram of the third embodiment is the same as that of FIG. 2 of the first embodiment, and differs from the first embodiment only in the flowchart of FIG. 7 showing the processing of the PCI configuration cycle execution unit 1 and the use of FIG. This is the contents of the function management table to be executed.

Next, the operation will be described. FIG. 7 is a flowchart showing an example in which the PCI configuration cycle execution unit 1 according to the third embodiment of the present invention uses the function management table 3 to perform processing.
In FIG. 7, the same processing steps as those in the first embodiment are denoted by the same step numbers as those in FIG. In FIG. 7, only steps different from those in FIG. 5 are described with new step numbers ST2-15.

When all the PCI buses / devices / functions are normal, the same processing as in the first embodiment is performed, so that the description is omitted. Also, the flow from the power-on reset to the first wake-up reset in the state where an error has occurred with the PCI bus number = 0 / device number = 1 / function number = 1 is the same as in the first embodiment. The description is omitted because the processing is performed.

Next, the flow after the first occurrence of the wake-up reset will be described. (1) Steps ST1-1 to ST1-14 are the same as those in the first embodiment. At this time, the PCI bus number = 0
The function status in the function management table 3 corresponding to / device number = 1 / function number = 1 is set to “1: abnormal”. (2) Thereafter, in the third embodiment, a writing process to the WDT clear register 5 is performed (step ST2-15),
(3) Move to configuration repetition processing of all PCI buses / devices / functions (step ST)
1-4), (4) Check the status of the target function to be configured during the current repetition processing (step ST1-5), and (5) PCI bus number = 0 /
Since the function status of the device number = 1 / function number = 1 is set to “1: abnormal”, the PCI configuration processing for the PCI bus number = 0 / device number = 1 / function number = 1 is omitted, and the remaining Are repeatedly executed from step ST1-4 for all PCI buses / devices / functions (step ST1-9).

(6) Here, assuming that a similar abnormality occurs in another PCI function during the PCI configuration of all the remaining PCI buses / devices / functions, PCI bus number = 0 / device number = 1 / function It is assumed that the abnormality of number = 3 (see FIG. 8).
The PCI configuration process for the PCI bus number = 0 / device number = 1 / function number = 3 repeats infinitely and does not end. As a result, the WDT counter counts up again. (7)
Here, the difference from the first embodiment is that steps ST2-15.
Since the writing to the WDT clear register 5 is performed once, the wake-up reset occurs even in the current count-up.

(8) After the wake-up reset, the process starts again from step ST1-1. (9) Finally, the PCI
Detects abnormalities in both bus number = 0 / device number = 1 / function number = 1 and PCI bus number = 0 / device number = 1 / function number = 3,
By omitting the PCI configuration process for both functions,
Logically disconnected from the I bus.

FIG. 8 shows PCI bus number = 0 / device number = 1 / function number = 1 and PCI bus number = 0.
9 shows an example of the function management table 3 after an error has occurred at / device number = 1 / function number = 3 and the PCI configuration processing has been omitted.

As described above, the wake-up reset by the WDT count-up is provided so that the reset from the stop of the PCI configuration cycle processing for the abnormal function can be performed. Further, the access address storage area 2 and the function management table 3
As a result, the access destination (PCI bus number / device number /
A means for storing and holding function numbers) is provided, and WDT clear processing is performed each time an abnormal function is detected. Therefore, detection of a plurality or all abnormal PCI functions and logical separation of the plurality or all abnormal PCI functions are performed. It is possible to improve the continuous operation of the system in the normal part.

As described above, there are a plurality of abnormal PCI functions, and the configuration can be completed by repeating the configuration until all the abnormal PCI functions are separated. However, if there is a failure in the host CPU function, the configuration operation is repeated.
It may be determined that the function of the PU or the PCI bus itself, which is the common unit, is stopped, and an alarm or the like is sent out to stop the configuration.

Embodiment 4 FIG. PCI as system configuration
As H / W mounted on the bus, 1 card = 1 device = 1 function or 1 card = 1 device =
There are many configurations of a plurality of functions, and an abnormal unit is often a card unit, that is, a device unit. In the fourth embodiment, logical disconnection is performed for each PCI device, and the system startup time is further reduced.

FIG. 9 shows a PC according to a fourth embodiment of the present invention.
FIG. 13 is a block diagram for realizing a method of isolating an I bus defective portion. In the figure, blocks equivalent to those in the third embodiment are denoted by the same reference numerals as in FIG. In FIG. 9, only portions different from those in FIG. 2 will be described with new block numbers in the thirties. In the fourth embodiment, since the unit of logical disconnection from the PCI bus is a PCI device, the function management table 3 in the third embodiment is a device management table 33. Other blocks are the same as in the third embodiment.

Next, the operation will be described. FIG. 10 is a flowchart showing an example in which the PCI configuration cycle execution unit 1 according to the fourth embodiment of the present invention performs processing using the device management table 33. In the figure, processing steps equivalent to those in the third embodiment are shown in FIG.
The same step numbers as those in FIG. Also, in FIG. 10, new step numbers ST3-3, ST3-5, ST3-1 only for portions different from FIG.
The description will be made with reference to 4.

When all the PCI buses / devices / functions are normal, the same processing as in the third embodiment is performed, so that the description is omitted. PCI bus number = 0 / device number =
The flow from the power-on reset in a state where an abnormality has occurred at 1 / function number = 1 will be described. (1) Steps ST1-1 to ST1-2 are completely the same as in the third embodiment. (2) Since the reset cause is other than the wake-up reset due to the WDT count-up, the device management table 3
3 are initialized to "0: normal" (step ST3-3).

(3) Step ST1-4 to Step ST
1-6 perform the same processing as in the third embodiment, and the PCI bus number = 0 / device number = 1 / function number = 1
When the PCI configuration is executed (step ST1-7), the PCI configuration cycle may endlessly repeat the retry processing and end up in a case where the retry processing is not completed. As a result, writing to the WDT clear register 5 cannot be performed before the WDT count-up, so that a wake-up reset occurs.

Next, the flow after the occurrence of the wake-up reset will be described. (1) In steps ST1-1 to ST1-13, the PCI bus number = 0 / device number = 1 / function number = 1, which is the information accessed before the occurrence of the wake-up reset, is written as in the third embodiment. Originally, the corresponding device status in the device management table 33 is set to “1: abnormal” (step ST3-14),
(2) Move to configuration repetition processing of all PCI buses / devices / functions (step ST)
1-4), (3) Check the status of the target device to be configured during the current repetition processing (step ST3-5).

(4) Since the device status of the PCI bus number = 0 / device number = 1 is set to “1: abnormal”, the PCI configuration processing for all functions of the PCI bus number = 0 / device number = 1 Is omitted, and all the remaining PCI buses / devices / functions are repeatedly executed from Step ST1-4 (Step ST1-9) to complete the entire PCI configuration.
Write to the DT clear register 5 (step ST
1-10).

(6) If a similar abnormality occurs in another device during the PCI configuration of all remaining PCI buses / devices / functions, the corresponding device status in the device management table 33 is set to “1:
"Abnormal" and restarts from step ST1-1 again. Even in this case, since the device management table 33 is retained without being cleared, the PC has been previously failed due to an abnormality.
Devices that omit the I configuration process
This time is omitted again.

FIG. 11 shows PCI bus number = 0 / device number = 1 / function number = 1, and PCI bus number =
7 shows an example of the device management table 33 after an error has occurred at 0 / device number = 3 / function number = 1 and PCI configuration processing has been omitted. It should be noted that the configuration and the detection of an abnormality are performed in function units, but the disconnection is performed in device units. Therefore, no function number is displayed in the device management table 33 in FIG.

As described above, the wake-up reset by the WDT count-up is provided so that the reset from the stop of the PCI configuration cycle processing for the abnormal device can be returned. Further, the access address storage area 2 and the device management table 33 allow Means for storing and holding the access destination (PCI bus number / device number) of the abnormal PCI configuration cycle is provided, and the WDT is detected every time an abnormal device is detected.
Since the clearing process is performed, it is possible to detect a plurality of or all abnormal PCI devices and to logically separate the plurality or all abnormal PCI devices, thereby improving the continuous operability of the system in a normal part.

Further, the logical separation in units of PCI devices shortens the system start-up time as compared with the logical separation in units of PCI functions.

In each of the above embodiments, the PCI bus has been described.
The present invention can be applied to a CI bus.

[0055]

(1) As described above, according to the first aspect of the present invention, it is possible to detect one abnormal PCI function and logically separate the one PCI function. This has the effect of improving the continuous operation of the system.

(2) According to the second aspect of the present invention, even if there is an abnormality, the configuration is repeated at least once for all PCI functions,
Even if an abnormality occurs transiently due to the influence of noise, there is an effect of preventing a normal PCI function from being regarded as abnormal.

(3) According to the third aspect of the invention, if there is an abnormality, the remaining PCI functions are sequentially configured to detect a plurality of or all abnormal PCI functions and to detect a plurality or all of them. The abnormal PCI function can be logically separated, and only the normal PCI function can be started up, which has the effect of improving the continuous operability of the system in the normal part.

(4) According to the invention described in claim 4, the PC
Since an abnormality is detected for each I device and the PCI device is disconnected, there is an effect of improving the continuous operation of the system in a normal part.

(5) According to the fifth aspect of the invention, there is an effect that a program for improving the continuous operability of the system in a normal portion is provided.

[0060]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PCI bus system according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a method of separating a PCI defective portion according to the first embodiment of the present invention.

FIG. 3 is an operation example of a WDT circuit used in a method of separating a PCI defective portion according to the first embodiment of the present invention.

FIG. 4 is an operation example of a WDT circuit used in the method of separating a PCI defective portion according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating an example of a method for separating a PCI defective portion according to the first embodiment of the present invention.

FIG. 6 is an example of a function management table used in the method of separating a PCI defective portion according to the first embodiment of the present invention.

FIG. 7 is a flowchart illustrating an example of a method of separating a PCI defective portion according to a third embodiment of the present invention.

FIG. 8 is an example of a function management table used in the method of separating a PCI defective portion according to the third embodiment of the present invention.

FIG. 9 is a block diagram illustrating an example of a method of separating a PCI defective portion according to a fourth embodiment of the present invention.

FIG. 10 is a flowchart illustrating an example of a method for separating a PCI defective portion according to a fourth embodiment of the present invention.

FIG. 11 is an example of a device management table used in a method of separating a PCI defective portion according to a fourth embodiment of the present invention.

FIG. 12 is a configuration example of a conventional PCI bus processing device.

[Explanation of symbols]

1 PCI configuration cycle execution unit 2 Access address storage area 3 Function management table 4 WDT circuit 5 WDT clear register 6 Reset generation circuit 7 Reset factor register 12, 13, 14 Add-in card 12a, 13a, 14a PCI device 12b, 12c, 13b , 14b, 14c PCI function

Claims (5)

[Claims] 1. A system in which a host CPU function and a PCI device having a built-in PCI function are connected to each other via a PCI bus. PCI function that separates a PCI function or PCI device from the above system
In the method for isolating a defective bus portion, a first method for sequentially executing configuration for each PCI function or each PCI device when the system is started up
And a second step of resetting all the PCI functions or PCI devices if there is an abnormality during the configuration, and separating the PCI function or the PCI device having an abnormality after the reset to remove the remaining PCI functions. Or a third step of sequentially executing a configuration for each PCI device by using the host CPU function to execute a program. 2. The method according to claim 1, wherein after resetting in the second step, returning to the first step, the first step is again performed to configure all PCI functions or PCI devices. And the second step is repeated at least once, and if the abnormality is not resolved, the process proceeds to the third step.
PC characterized by including the following steps in the program
How to isolate the defective part of the I bus. 3. In the method of isolating a defective portion of the PCI bus according to claim 1 or 2, if the abnormality is not resolved even if the configuration is executed in the third step, the process returns to the second step and returns to all the PCIs. In order to reset the function or the PCI function, the program includes a fifth step of repeating the second and third steps a predetermined number of times or until the abnormality is resolved.
A method for isolating a defective portion of a PCI bus, wherein a CI device can be isolated from a system. 4. A method for isolating a defective portion of a PCI bus according to any one of claims 1 to 3, wherein the third step is executed, and the abnormality is not resolved, or after the third step is executed. If the abnormality is not resolved after the desired time, or if any one of the first to third steps cannot be executed, a sixth step of determining that the host CPU function is abnormal is included in the program. PCI bus failure location isolation method. 5. The P according to claim 1, wherein
A program for executing a method of isolating a defective portion of the CI bus.