JP2002288036A - Memory reading circuit and ice - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read memories different from each other in accessing timing by one circuit. SOLUTION: A start address storage register 2 stores a CPU address 31 from a CPU 1 in response to an address start signal 51, and outputs the same as a start address 32. A boundary address of SDRAM and FLASH, and an accessing timing of each of SDRAM and FLASH are determined in an access adjusting part 10. The access adjusting part 10 compares the start address with the boundary address, selects a corresponding accessing timing among the determined access timings on the basis of a result of the comparison, generates an increment signal 53, and outputs a corresponding SDRAM or FLASH to lead signals 56, 57. A counter 3 reads the start address to determine as an initial value of the count, and counts up in response to the increment signal to output as an address 33 of a A memory 6 or a B memory 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory read circuit for reading data stored in a memory which is not built in a CPU, particularly a memory read circuit suitable for memories having various operation speeds. Used ICE (In
Circuit Emulator).

[0002]

2. Description of the Related Art When developing a device (for example, a video deck) using a microcomputer, an ICE is often used as a device for evaluating a program running on the microcomputer. As is well known, the ICE
A rewritable memory for storing the program and a CPU for reading the contents of the rewritable memory based on an instruction from the device under development, and a probe (terminal) for mounting a microcomputer on the substrate of the device under development. Connected via As a result, the program developer can simulate the development target device in which the microcomputer is mounted, and debug or evaluate the target program while confirming the operation of the simulated development target device.

FIG. 9 is a block diagram showing an interleave circuit 70 as a memory read circuit for a rewritable memory used in the above-mentioned ICE or the like. The interleave circuit 70 reads the contents stored in the two memories (A memory 76 and B memory 77) in an interleaved manner according to an instruction from the CPU 71. A memory 76 and B
The memory 77 stores, for example, a target program in the ICE, and functions as a substitute memory for the ROM built in the microcomputer after the development of the development target device is completed. That is, the program developer reads out the target program stored in the A memory 76 and the B memory 77 and debugs or evaluates it.

In FIG. 9, an AND gate 72 has a CP
Clock 80 and read enable signal 82 from U71
An increment signal 83 is generated by the logical sum of the above and output to the counter 73. When the CPU 71 sets the start address 81 in the counter 73, the counter 73 counts up the value of the start address 81 in synchronization with the increment signal 83 and outputs it as an address 85 to the A register 74 and the B register 75. That is, the counter 73
Is controlled by the increment signal 83.

At the same time, a part of the address 85 (for example, the least significant bit) is output as a partial address 84 to the A register 74 and the B register 75. A register 74 and B
The value of the address 85 is stored in the register 75 in synchronization with the partial address 84. A register 74 and B register 7
5 is an A address 8 for each of the stored address values.
6, A memory 76, B memory 77 as B address 87
Output to A memory 76 and B memory 77 store data corresponding to A address 86 and B address 87 in A data 8
8. Output as B data 89. FIFO 78 stores A data 88 or B data 89, and stores data 9 in the order of input.
Output to CPU 71 as 0.

By adding a timing adjustment circuit to the above-described interleave circuit 70, an increment signal 8
It is easy to make 3 variable. As a result, a memory reading circuit for the A memory 76 and the B memory 77 having various operation speeds can be realized. The conventional ICE uses such an external memory read circuit to debug or evaluate a target program at various speeds.

[0007]

The recent LS
With the advancement of the I technology, the storage capacity of memories that can be accommodated in one chip has been dramatically increased, and different types of memories such as synchronous SRAM (synchronous SRAM)
ou static RAM) and flash memory (flashmemor)
y) can be formed. In addition, the microcomputer R
As the OM, memories having different performances such as a mask ROM and a flash memory can be selected. Therefore, regardless of whether the two memories are configured on one chip or not, the two memories are used as the A memory 76 and the B memory 77 shown in FIG. If an SRAM area and a slower target program are stored in the flash memory area of each memory, an ICE that can debug or evaluate two target programs at once can be realized.

However, in the above-described conventional external memory readout circuit, since different timings cannot be supplied to each of a plurality of memory regions having different speeds, such ICE cannot be realized. This is not limited to the ICE alone, but is a problem that can be enjoyed if various timings can be varied for each memory area, and will spread to more application fields.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object of the present invention is to provide a memory read circuit which can supply different timings to a plurality of memories having different speeds, and furthermore, an ICE.

[0010]

A memory read circuit according to the present invention has a memory (A in FIG. 1) having different access timings based on an instruction from an access subject (CPU 1 in FIG. 1).
In a memory read circuit for accessing the memory 6 and the B memory 7), the CPU address (31 in FIG. 1) of each memory from the access subject is stored and started in response to the address start signal (51 in FIG. 1). Address (3 in FIG. 1)
A start address storage register (2 in FIG. 1) to be output as 2), a boundary address of each memory set from the outside and an access timing for each memory are set, and a result of comparison between the start address and the boundary address is set as follows. A corresponding one of the set access timings is selected to generate an increment signal (53 in FIG. 1), and a read signal (56, 5 in FIG. 1) is supplied to the corresponding one of the memories.
7) an access adjusting unit (10 in FIG. 1) that outputs a start address, and read a start address and set it as an initial value of a count;
And a counter (3 in FIG. 1) that counts up in response to the increment signal and outputs it as an address (33 in FIG. 1) of the memory.

The access adjustment unit (10 in FIGS. 1 and 2) includes an address setting register (11 in FIG. 2) for setting a boundary address of each memory from the outside, and a memory for setting access timing from the outside. For each timing setting register (12, 13 in FIG. 2), an address comparison circuit (14 in FIG. 2) for comparing the start address with the boundary address of the address setting register, and the correspondence of the memory to which the start address belongs based on the comparison result A timing selector (15 in FIG. 2) for selecting an access timing to be accessed, and an access timing adjustment unit (FIG. 2) for generating an increment signal delayed from the address start signal by the number of clocks based on the access timing selected from the address start signal.
20) and a distribution circuit (16 in FIG. 2) for outputting a read signal to the memory to which the start address belongs according to the result of the comparison.

Further, the access timing adjustment section (20 in FIGS. 2 and 3) includes a counter (23 in FIG. 3) for sequentially counting up a clock when a read enable signal from an access subject is active. A comparison circuit (24 in FIG. 3) for comparing the count value of the counter with the selected access timing, and an edge detection circuit (25 in FIG. 3) for detecting an address start signal.
When the result of the detection or comparison of the address start signal indicates a match, an increment signal is output.

Each of the above memories may be formed on one chip, and each memory may be read out in an interleaved manner.

[0014]

According to the present invention, first, the boundary addresses of memories having different speeds and the speed of each memory are externally set in the memory reading circuit. The CPU that reads the memory outputs the start address of each memory to the memory reading circuit. The memory read circuit compares the start address with the boundary address,
The address is transitioned at a speed corresponding to the speed of the corresponding memory, and is supplied to the corresponding memory by a read signal. As a result, it becomes possible to automatically switch and access a variety of memories with one memory reading circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory read circuit according to the present invention makes an address transition according to an access timing of each memory having a different access timing based on a value set from the outside, and automatically causes each memory to perform a read signal. It is characterized by switching supply.

[0015]

Next, an embodiment of a memory read circuit according to the present invention will be specifically described with reference to the drawings.

FIG. 7 is a diagram showing an environment in which the interleave circuit 9 as the memory read circuit of the present invention is used. In FIG. 7, an interleave circuit 9 reads out the stored contents of the A memory 6 and the B memory 7 in an interleaved manner according to an instruction from the CPU 1. The A memory 6 and the B memory 7 have the same configuration, and each includes a synchronous SRAM (hereinafter, referred to as “SSRAM”) area and a flash memory (hereinafter, referred to as “FLASH”) area.

More specifically, the A memory 6 and the B memory 7
The addresses 0000H to 0FFFH are in the SSRAM area, and the addresses 1000H to 1FFF are in the FLASH area. Note that the interleaving method is similar to the operation using the pipeline method.
It is well known as a technique for making a memory slower than a CPU look faster by simultaneously accessing a plurality of memories by slightly shifting the access phase.

FIG. 1 is a block diagram of an embodiment of a read circuit according to the present invention. An increment signal 53 for supplying an address 33 to the SSRAM area and the FLASH area at different speeds is different from the SSRAM area and the FLASH area. Read signal 5 for reading data 40 at speed
It is characterized in that an access adjusting unit 10 for generating 6, 57 is provided.

In the access adjustment unit 10, a boundary address 1000H between the SSRAM area and the FLASH area, a timing set value at addresses 0000H to 0FFFH, and a timing set value at addresses 1000H to 1FFF are set in advance by the external input 30. Is done. Then, an address start signal 51 is sent from the CPU 1.
In response, the start address 32 is set from the start address storage register 2, and an increment signal 53 is generated in response to the clock 50 and supplied to the counter 3.

If the start address 32 is less than the boundary address 1000H, the increment signal 53 is 0000H to 0FFF.
If the timing set value at the address H and the start address 32 are equal to or larger than the boundary address 1000H, it is generated based on the timing set values at 1000H to 1FFF. Further, upon receiving the read enable signal 52 from the CPU 1, the access adjusting unit 10 similarly performs a read signal 56 for the SSRAM,
A read signal 57 for FLASH is generated and the A memory 6
To the respective SSRAM area and FLASH area of the B memory 7.

The CPU 1 reads and processes the A data 41 and B data 42 stored in the A memory 6 and the B memory 7 in an interleaved manner. For this purpose, CPU address 31 is output to start address storage register 2. C
The PU address 31 has a meaning as an address which is activated first when the CPU 1 accesses a continuous address space of the A memory 6 and the B memory 7.

The start address storage register 2 stores the CPU address 31 and stores it in the access adjusting unit 10 and the counter 3.
CPU address 31 is output as start address 32. The counter 3 reads the start address 32, sets it as an initial value of the count, performs a counter increment in synchronization with an increment signal 53 from the access adjustment unit 10, and outputs the address 33 to the A register 4 and the B register 5. The counter 3 outputs one bit of the address 33 to the A register 4 and the B register 5 as a partial address 34. The partial address 34 is set to a bit corresponding to a count unit in the counter 3. Thus, the update timing of the A register 4 and the B register 5 can be controlled by the timing of the increment signal 53.

The A register 4 and the B register 5 input the partial address 34 to the bit complement, and the address 33 is written in synchronization with this. That is, the writing conditions for the A register 4 and the B register 5 are, for example, writing to the A register 4 when the partial address 34 is “0” and writing to the B register 5 when the partial address 34 is “1”. As a result, the address 33 is written to the A register 4 and the B register 5 alternately. The address 33 written in the A register 4 and the B register 5 is output to the A memory 6 and the B memory 7 as the A address 35 and the B address 36 as they are.

When the read signal 56 and the read signal 57 become active, the A memory 6 and the B memory 7
A data 4 corresponding to address 35 and B address 36
1 and B data 42 are output to the FIFO 8. FIFO8
Stores the A data 41 and the B data 42 and synchronizes the A data 41 or the B data 42 as the data 40 in the stored order in synchronization with the read enable signal 52 from the CPU 1.
Output to PU1.

FIG. 2 is a detailed block diagram of the access adjusting unit 10. In FIG. 2, an address setting register 11,
The timing setting register 12 and the timing setting register 13 are respectively allocated to appropriate memory spaces of the CPU 1, and writing to them is performed by designating the address of the register, but FIG. 2 avoids complication of the drawing. Therefore, illustration of the route is omitted.

The address setting register 11 includes a boundary address (for example, address 1000H), a timing setting register 12
The timing setting value (eg, “3”) in the address area (addresses 0000H to 0FFFH) smaller than the boundary address is stored in the timing setting register 13 in the address area (1000H to 1FFF) equal to or higher than the boundary address. 4 ″) is set by the external input 30. These timing setting values “3” or “4” indicate the delay time of the increment signal 53 after the address start signal 51 valid for one clock time, as a multiple of the clock 50.

The address comparison circuit 14 receives the start address 32 from the start address storage register 2, compares the start address 32 with the boundary address set in the address setting register 11, and compares the result with a comparison signal 54.
To the timing selector 15 and the distribution circuit 16. At this time, if the start address 32 is smaller than the boundary address, “0” is output to the comparison signal 54 and the start address 3
If 2 is equal to or larger than the boundary address, "1" is output to the comparison signal 54.

The timing selector 15 outputs a comparison signal 54
Is “0”, the timing setting value “3” of the timing setting register 12 is used. If the comparison signal 54 is “1”, the timing setting value “4” of the timing setting register 13 is used.
Each is output to the access timing adjustment unit 20 as the setting timing 55.

The access timing adjustment unit 20 is a CPU
When the read enable signal 52 is received from 1, an increment signal 53 delayed from the address start signal 51 by the clock number “3” or “4” of the set timing 55 is generated in synchronization with the clock 50 and output to the counter 3.

The distribution circuit 16 activates the read signal 56 in synchronization with the read enable signal 52 when the comparison signal 56 is "0", and synchronizes with the read enable signal 52 when the comparison signal 56 is "1". To make the read signal 57 active. The read signal 56 is supplied to each SSRAM area of the A memory 6 and the B memory 7, and the read signal 57 is supplied to each FLASH area of the A memory 6 and the B memory 7. 57 becomes active.

FIG. 3 is a detailed block diagram of the access timing adjustment unit 10. In FIG. 3, an AND gate 21
Supplies the clock 50 to the counter 23 when the read enable signal is active. The counter 23 includes a three-stage flip-flop (F / F). Each F / F outputs bit 1, bit 2, and bit 3 to the comparison circuit 24. The comparison circuit 24 calculates the value indicated by the bit 1, bit 2 and bit 3 of the counter 23 and the setting timing 55
Are compared, and if they match, the wait signal 58 is made non-active. Then, the non-active state is maintained until a new setting timing 55 is input.

The AND gate 22 does not output the A increment signal 5A while the wait signal 58 is active even if the read enable signal 52 is active. That is, in order to suppress the output of the increment signal 53 following the increment signal 53 based on the address start signal 51, the output of the A increment signal 5A is made to wait. Then, when the wait signal 58 becomes non-active and the read enable signal 52 is active, the A increment signal 5A is output to the OR gate 26 in synchronization with the clock 50.

When detecting the falling edge of the address start signal 51, the edge detection circuit 25 outputs a B increment signal 5B to the OR gate 26. This is for outputting the increment signal 53 by the address start signal. The OR gate 26 outputs the A increment signals 5A and B
The logical sum with the increment signal 5B is output to the counter 3 in FIG. 1 as an increment signal 53.

Next, the operation of the present embodiment will be described with reference to the timing chart of the interleave circuit shown in FIGS. 4 and 5, and the timing chart of the access timing adjusting section 20 shown in FIG.

In FIG. 4, first, at the time of clock 1, the boundary address “B0” (address 1000 in the above example) is stored in the address setting register 11 and the boundary address “B0” is stored in the timing setting register 12 by the external input 30. The timing setting value (“3” in the above example) is set in the timing setting register 12, and the timing setting value (“4” in the above example) below the boundary address “B0” is set in the timing setting register 12. The start address storage register 2 stores the CPU address 31 “A0” input from the CPU 1 in the address start signal 5
1 is output as the start address 32 in response to the "1".

It is assumed that the start address 32 "A0" is less than the boundary address "B0". In this case, the comparison signal 56
Becomes “0”, the timing selector 15 outputs “3” as the setting timing 55. The counter 3 outputs the start address 32 “A0” to the A register 4 as the address 33, and is held there. Since the read enable signal 52 is “0” at the time of input of the clock 1, as apparent from FIG.
3 is not output. Further, since the comparison signal 54 is “0”, the distribution circuit 16 outputs the read signal 56 to the SSRAM area of the A memory 6 and the B memory 7.

At the time of clock 2, since the B increment signal 5B is output from the edge detection circuit 25 of the access timing adjustment unit 20 which has detected the falling edge of the address start signal 51, the increment signal 53 is output from the OR gate 26 to the counter. 3 (see FIG. 3).
If the increment unit is “4”, the counter 3 increments the start address 32 “A0” by “4”,
The address 33 “A0 + 4” is output. Partial address 34
Becomes “1” because it is the third bit from the least significant bit of the address bit corresponding to the increment unit “4”. Therefore, the address 33 "A0 + 4" is output to the B register 5 as the B address 36 and is held there.

On the other hand, A clock from clock A
The address 33 “A0” held in the register 4 is supplied to the A memory 6 as the A address 35. In response to the read signal 54, the A
Data 41 “DA0” is read out to FIFO8.
In FIG. 3, the counter 23 counts the clock 50 and outputs “1” to bit 1.

At the time of the clock 3, the address start signal 51 is already "0", and in FIG. 3, the counter 23 counts the clock 50 and outputs "1" to the bit 2; Since the value (“2”) indicated by bit 1, bit 2 and bit 3 does not match the value (“3”) of setting timing 55, comparison circuit 24 keeps wait signal 58 active. Therefore, the increment signal 53 is not output, and the address 33 remains “A0 + 4”. As a result, the partial address 34 also maintains 1 ", so that the A address 35 remains" A0 "and the B address 36 remains" A0 + 4 ". B address 36 "A0
The B data 42 of "+4" is read out to the FIFO 8 as "DA0 + 4", and the A data 41 input from the FIFO 8 at the time of the clock 2 is read out to the CPU 1 as the data 40.

In the time period of the clock 4, the CPU 1 sends the CP
The U address 31 “A0 + 4” is output. However, as apparent from FIG. 4, this "A0 + 4"
Is already output from the counter 3 as the address 33 at the time. That is, it has been preempted. The counter 23 of FIG. 3 counts the clock 50 and outputs “1” to the bit 1 and the bit 2, and the value (“3”) indicated by the bit 1, the bit 2 and the bit 3 and the value of the setting timing 55 (“ 3 ″), the comparison circuit 24 makes the wait signal 58 non-active.

As a result, the A increment signal 5A is output from the AND gate 22 to the counter 3 as the increment signal 53 via the OR gate 26. The counter 3 counts up the address 33 “A0 + 4” to “A0 + 8” in response to the increment signal 53.
And Since the address 33 is updated, the partial address 34 becomes “0”, so that the address 33 “A0 + 8”
Are held in the A register 4. Since there is no change in the address 33 at the time of the clock 3, the A data 41 and the B data
The data 42 remains unchanged. Therefore, FIFO8
The data 40 is not read from the.

In the time of the clock 5, the CPU 1 sends the CP
The U address 31 “A0 + 8” is output. However, as apparent from FIG. 4, "A0 + 8"
Is already output from the counter 3 in advance as the address 33 at the time. Since the counter 23 of FIG. 3 outputs “1” to the bit 3, the count value “4” of the counter 23 does not match the set timing 55 “3” in the comparison circuit 24, but there is no change in the set timing 55. The wait signal 58 maintains a non-active state.

As a result, in response to the increment signal 53, the counter 3 counts up the address 33 "A0 + 8" so far to "A0 + C". Since the address 33 is updated, the partial address 34 becomes “1”, so that the address 33 “A0 + C” is held in the B register 5. From the SSRAM area of the A memory 6, the A data 4 of the A address 35 “A0 + 8” input at the time of the clock 4
1 is read out to the FIFO 8 by "DA0 + 8". FI
B data 4 input at the time of clock 2 from FO 8
2 “DA0 + 4” is read out as data 40 by the CPU 1.

In the time period of the clock 6, the CPU 1 sends the CP
The U address 31 “A0 + C” is output.
Has already been output from the counter 3 in advance as the address 33 at the time of the clock 5. Further, since there is no change in the setting timing 55, the wait signal 58 in FIG. 3 maintains the non-active state. As a result, in response to the increment signal 53, the counter 3 counts up the address 33 "A0 + C" so far to "A0 + 10". Since the address 33 is updated, the partial address 34 becomes “0”, so that the address 33 “A0 + 10”
Are held in the A register 6. SSRAM of B memory 7
From the area, the B data 42 of the A address 35 “A0 + C” input at the time of the clock 5 is “DA0 + C” in the FIFO 8
Is read out. The A data 41 “DA0 + 8” input at the time of the clock 5 is read out from the FIFO 8 as data 40 by the CPU 1.

At the time of the clock 7, the CPU 1 outputs the CPU address 31 "B0", which is stored in the start address storage register 2. This CPU address 31
Since “B0” matches the boundary address “B” set in the add setting register 11 of the access arbitration unit 10 by the external input 30 at the time of the clock 1, the address comparison circuit 1
4 outputs a comparison signal 54 "0". As a result, the timing selector 15 selects the timing setting register 13.

The comparison circuit 24 shown in FIG. 3 activates the wait signal 58 in response to the address start signal 51 and compares the set timing “4” from the timing setting register 13 with the address start signal 52. Become. Further, the distribution circuit 16 outputs the read signal 57 to the A memory 6.
And to the FLASH area of the B memory 7,
The A data 41 or the B data 42 is read from the H area. The other operations are the same as the operations at the time of clock 1. However, A data 41 “DA0 + 10”
Is read out to the FIFO 8. From the FIFO 8, the B data 42 “DA0 + C” input at the time of the clock 6 is read out to the CPU 1 as data 40.

The operation in the time zone of clock 8 is the same as the operation in the time zone of clock 2, and the operation in the time zone of clock 9 is the same as the operation in the time zone of clock 3. Even during the time of the clock 10, the number of the clocks 50 after the address start signal 51 is less than the timing "4" set in the timing setting register 13, so that the wait signal 58 in FIG. There is no difference from the operation at the time 9. For the time after the clock 9, refer to FIG.

At the time of clock 11, the counter 23 of FIG. 3 outputs "0" to bit 1 and bit 2 and "1" to bit 3 so that the count value and the setting timing 55 " 4 "coincide with each other, making the wait signal 58 inactive. As a result, the increment signal 53 is output, and continuous reading of the A data 41 and the B data 42 from the FLASH area of the A memory 6 and the B memory 7 is started. SS explained earlier
The continuous reading of data from the RAM area was started three clocks after the address start signal 51, while the data read from the FLASH area was started three times after the address start signal 51.
It will start after the elapse of the clock. As described above, since the read speed of the memory can be changed depending on the address area, the access timing can be changed according to the response time of the memory.

The operation after the time of clock 12 is as follows.
The description is omitted because it is the same as that after clock 5.

In the above description, the A memory 6 and the B memory 7 have the SSRAM area and the FL memory in one chip.
Although the ASH area is included, another type of memory may be configured on a different chip. Also, interleaving is not essential to the present invention, but merely a scheme adopted to speed up the memory.

Next, FIG. 8 shows the configuration of a debugging device when the above-described interleave circuit 66 is used for the ICE 63 and the video deck 60 is evaluated by the ICE 63.

In the development of the video deck 60, the development maker uses a microcomputer to control the motor 62 and the like. Because a program is needed to control a microcomputer, developers must of course debug the program. For this reason, a debugging function has been added to the microcomputer to enable rewriting of the built-in ROM.
Used for debugging as CE63. Since program debugging is performed using the personal computer 68, the IC
The E63 also includes an I / F that can communicate with the personal computer 68.

Since it is necessary to perform this debugging while confirming that the video deck 60 operates normally, the debugging is performed with a proper microcomputer mounted on the video deck 60. However, since a genuine microcomputer is still under development, the controller mounting socket 6 on which the genuine microcomputer is to be mounted is mounted on the VCR 60 board.
2 is connected to a probe of the ICE 60, and is led to the video deck 60 via the controller mounting socket 62.

Then, the CPU 65 is connected to the CPU 65 via the I / F 64 of the ICE 63, and the CPU 65 accesses the internal ROM alternative memory 67 by the interleave circuit 66. Built-in ROM replacement memory 67 is SSRAM, FLAS
H, etc., in which a target program to be run by an authorized microcomputer is stored. As a result, the VCR 60 equipped with a microcomputer and having a program written in its built-in ROM can be almost simulated, and the program developer can debug the program while checking the operation of the VCR. . And
By selectively using memories of different speeds, ie, the SSRAM and the FLASH, the target program can be debugged at once at different speeds.

[0055]

According to the effect of the present invention, since various access timings can be supplied to various types of memories having different access timings according to preset values, the various types of memories can be automatically switched and accessed. That's what it means. Thus, in the case of a device such as an ICE that simulates various types of memories,
Simulating a plurality of types of memories is possible only by preparing one ICE.

[Brief description of the drawings]

FIG. 1 is a block diagram of a read circuit according to an embodiment of the present invention;

FIG. 2 is a detailed block diagram of an access adjusting unit 10 in FIG.

FIG. 3 is a detailed block diagram of an access timing adjustment unit 20 in FIG. 2;

FIG. 4 is a partial view showing the first half of the timing chart of the interleave circuit shown in FIG. 1;

FIG. 5 is a partial view showing the latter half of the timing chart of the interleave circuit shown in FIG. 1;

6 is a timing chart of the access timing adjusting unit 20 shown in FIG.

FIG. 7 is a diagram showing an environment in which the interleave circuit 9 shown in FIG. 1 is used;

FIG. 8 shows an ICE in which the memory read circuit of the present invention is used.
Block diagram showing the configuration of a debugging device based on

FIG. 9 is a block diagram showing an example of a conventional memory read circuit.

[Explanation of symbols]

 1 CPU 2 Start address storage register 3 Counter 4 A register 5 B register 6 A memory 7 B register 8 FIFO 10 Access adjustment unit 11 Address setting register 12 Timing setting register 13 Timing setting register 14 Address comparison circuit 15 Timing selector 16 Distribution circuit 20 Access timing adjustment unit 21 AND gate 22 AND gate 23 Counter 24 Comparison circuit 25 Edge detection circuit 26 OR gate 60 Video deck 61 Controller mounting socket 62 Counter, motor, etc. 63 ICE 64 I / F 65 CPU 66 Interleave circuit 67 Internal ROM replacement Memory 68 PC

Claims (7)

[Claims] 1. A memory read-out device, wherein an address corresponding to each access timing of a memory having a different access timing is changed based on a value set from the outside, and automatically supplied to each memory by a read signal. circuit. 2. A memory read circuit for accessing memories having different access timings based on an instruction from an access subject, wherein a CPU address for each memory from the access subject is stored in response to an address start signal. A start address storage register to be output as a start address, a boundary address of each memory set externally, and an access timing for each memory are set, and the result of the comparison between the start address and the boundary address sets the setting. An access adjusting unit that selects an appropriate one of the set access timings to generate an increment signal, and outputs a read signal to the corresponding one of the memories; and reads the start address and initializes a count. In response to the increment signal A counter for counting up and outputting as an address of the memory. 3. An access setting unit, comprising: an address setting register in which a boundary address of each memory is externally set; a timing setting register in each memory in which the access timing is externally set; An address comparing circuit for comparing the boundary address of the address setting register with a boundary address; a timing selector for selecting a corresponding access timing of a memory to which the start address belongs according to a result of the comparison; and the access timing selected from the address start signal An access timing adjustment unit that generates the increment signal delayed from the address start signal by the number of clocks based on the address, and a distribution circuit that outputs a read signal to a memory to which the start address belongs based on a result of the comparison. Noted in 2 On-chip memory readout circuit. 4. The access timing adjustment section, comprising: a counter for sequentially counting up a clock when a read enable signal from the access subject is active; and comparing a count value of the counter with the selected access timing. 4. The memory read circuit according to claim 3, further comprising: a comparison circuit for detecting the address start signal and an edge detection circuit for detecting the address start signal, and outputting the increment signal when the result of the detection of the address start signal or the result of the comparison is identical. . 5. The memory read circuit according to claim 1, wherein each of said memories is formed on one chip. 6. The memory reading circuit according to claim 1, wherein each of said memories is read out in an interleaved manner. 7. An ICE, wherein the memory read circuit according to claim 1 is used for reading a built-in ROM alternative memory for storing a target program to be debugged.