JP2002269033A - Bus system using arbiter having retry control function and system lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus system having a retry control function for an arbiter controlling the use right of a bus in the computer system of a bus connection system and to provide system LSI. SOLUTION: In the bus system, a plurality of bus masters 105 and 106 and a bus slave 107 generating a bus cycle interruption request are connected to a common bus 108. When the arbiter 101 controlling the use right of the bus 108 receives the interruption request 103 from the bus slave 107, the connection of the bus master (105, for example) obtaining the bus 108 and the bus 108 is interrupted and cut, and another bus master (106, for example) and the bus 108 are connected. When the use of the bus by the other bus master 106 is terminated, the interrupted bus master 105 and the bus 108 are reconnected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system in which an arbiter for controlling the right to use a bus has a retry control function in a bus connection type computer system, and a system LSI.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration diagram of a conventional bus system having a retry function. In FIG. 3, the common bus 40
1 is connected to a plurality of bus masters 402 and 403 and a bus slave 404. Bus masters 402, 40
Reference numeral 3 denotes a bus master having a retry function. When a quest signal REQ 406 for acquiring the common bus 401 from the bus master 402 or 403 is input, the arbiter 405 returns a grant signal GNT 407 to one bus master (for example, the bus master 402) according to the priority and the like. The use of the common bus 401 is permitted. The bus master 402 accesses another slave (for example, a memory or an I / O controller) connected to the common bus 401 and executes data processing.
To release.

[0003] Of the bus masters described above, bus master 40
Numeral 3 is for acquiring a common bus 401 and causing a bus cycle, and also has a bus slave function. On the other hand, unlike the bus master 403, the bus master 402 does not have a bus slave function. These bus masters 402 and 40
3 when the interrupt request signal 410 from the bus cycle identification circuit 209 is input during the execution of the bus cycle by itself.
A bus cycle interruption / reconnection circuit 408 is provided for once releasing the common bus 401 and restarting (retrying) the same cycle later.

The bus slave 404 has a function of requesting interruption of the cycle of the common bus 401 at the time of accepting or executing a bus cycle, and a function of interrupting the cycle at the time of reading and continuing preparation of read data at the time of a delayed read operation. A bus cycle identification circuit 409 has a function of determining whether a cycle is caused by the same access as a read being executed. The bus master 403 also has a bus cycle identification circuit 409 similar to the bus slave 404.

In a conventional bus system having a retry mechanism having the above-described circuit configuration, when a bus cycle interruption request signal 410 is issued from the bus cycle identification circuit 409 of the bus slave 404 or the bus master 403 having a slave function, the bus is stopped. The bus master 402 or 403 that has started the cycle temporarily suspends the bus cycle by the suspend / reconnect circuit 408, releases the common bus 401, acquires the common bus 401 again, and re-executes the same bus cycle. ing. On the other hand, the bus slave 404 that issues a bus cycle interruption request or the bus master 403 having a slave function stores a read cycle to be interrupted by the bus cycle identification circuit 409 when performing a delayed read, and can reconnect. So that it is kept.

[0008] The delay read means, for example, the bus master 403.
During execution of the read cycle requested by the common bus 401
By temporarily interrupting the above read cycle and releasing the bus, while continuing to read and preparing the read data, the bus master 403 interrupted once in the read cycle makes the same read access again. Sometimes, this is a method that allows read data to be returned immediately. Even if it takes a long time from the read request to the return of the read data by performing the delayed read, the common bus 401 is not occupied (temporarily released) during the read operation. Can be improved.

However, in the process of reconnection after release,
The bus master 403 stores the address of the read request to be interrupted, the read size, and the like in the interrupt / reconnect circuit 408, compares the information with the information stored at the time of reconnection, and determines that the read is interrupted by itself. A determination is made. However, if the same read request is issued from another bus master 402 during the suspension, the bus slave 4
In 04, since it is not possible to identify from which bus master the access is made, the originally requested bus master 403
Instead, the bus master 402 that has issued the same request later
However, there is a problem that a phenomenon in which read data is returned occurs.

[0008]

As described above, in a conventional bus system having a retry function, it is necessary to provide each bus master with a circuit for interrupting and reconnecting a bus cycle. Further, the bus slave supporting the retry needs to be provided with a bus cycle identification circuit having a function of requesting the interruption of the bus cycle and a function of identifying the same bus cycle at the time of reconnection. In addition, there is a problem that the read data is returned not to the bus master originally requesting but to the bus master issuing the same request later.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. By providing an interrupt / reconnect circuit in a bus arbiter without providing an interrupt / reconnect circuit in a bus master or a cycle identification circuit in a bus slave. It is an object of the present invention to provide a bus system and a system LSI that realize a retry function.

[0010]

In order to achieve the above object, a bus system using an arbiter having a retry control function according to the present invention uses a plurality of bus masters and a bus slave that issues a bus cycle interruption request. In a bus system connected to the bus, when the arbiter that controls the right to use the bus receives the suspend request from the bus slave, suspends the connection between the bus master that has acquired the bus and the bus. The bus is disconnected, another bus master is connected to the bus, and when the bus use by the other bus master is finished, the interrupted bus master is reconnected to the bus.

Further, the system LSI of the present invention is a system LSI in which at least first and second bus masters having no bus cycle interruption / reconnection function and a bus slave having a bus cycle interruption request function are connected to a common bus. Wherein an arbiter having a function of receiving a bus cycle interruption request from the bus slave and disconnecting the bus master being accessed from the common bus is provided.

According to the present invention, the bus arbiter managing the right to use the bus disconnects the common bus in response to the interruption request from the bus slave, and reconnects the interrupted (disconnected) request to the request destination. By providing the function, (1) the logic of disconnecting and reconnecting the bus from the bus master of the bus system or the system LSI having the conventional retry mechanism can be deleted, and the amount of logic can be reduced. (2) Instead of adding a retry mechanism to all bus masters of a bus system or a system LSI having no retry mechanism, an arbiter that exists only in the system has a bus retry mechanism to easily implement the retry mechanism. I can do it. (3) The storage logic for identifying the interrupted read request at the time of reconnection at the time of delayed read from the bus slave that issues the interrupt request can be deleted to reduce the amount of logic. (4) The arbiter monitors the entire system,
It is possible to prevent the interrupted lead from being erroneously identified at the time of reconnection and being reconnected to another master.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a bus system to which the present invention is applied.

Arbiter 101 provided by the present invention
Is provided with an interruption / reconnection circuit 102 therein. When the suspend / reconnect circuit 102 receives the suspend request signal 103 from the bus slave 107 that outputs the suspend request or the bus master 106 having the slave function, the suspend / reconnect circuit 102 responds to this by sending the bus disconnect signal 104 to the bus masters 105, 10
6 and a gate 10 provided between the common bus 108
9 is output. Thereby, the bus master 105 or 1
06 and the common bus 108 are disconnected. Arbiter 101
Has a function of outputting a grant signal GNT permitting use of the bus 108 in response to reception of the request signal REQ from the bus masters 105 and 106, a function of controlling a normal bus use right, and the like. I have. Arbiter 1
01, the bus 108
, The bus 108 can be used efficiently. That is, there is no phenomenon that the read data is returned to the bus master that has issued the same request later instead of the bus master that originally requested it.

FIG. 2 shows a configuration of a second embodiment in which the bus system of FIG. 1 is developed on an LSI. That is, FIG.
Bus master of PU, DMA, PCI bus controller,
1 shows a configuration diagram of a system LSI having a bus slave.

The CPU 201 is an arithmetic and control unit for controlling the system, and corresponds to the bus master 105 in FIG.
The DMAC 202 is a DMA controller having a DMA function, and corresponds to the bus master 106 in FIG. PCI
A PCI host bridge controller C203 connects the local bus 205 inside the system LSI and the PCI bus 208 outside the LSI.
07. The arbiter 204 has a suspend / reconnect circuit 206, and receives a RETR of a suspend request from the PCIC 203.
Upon receiving the Y signal 207, the bus master (CPU 20
1 or the DMAC 202) to output a signal 208 for disconnecting (interrupting) the connection between the local bus 205 and the local bus 205 to the gate 209 between the local bus of the bus master and corresponds to the arbiter 101 in FIG.

The arbiter 204 has a CPU 201 and D
Upon receiving a request signal REQ0 or REQ1 requesting use of the local bus 205 from the MAC 202,
Use permission signal GNT0 to PU201 or DMAC202
Alternatively, it has a function of controlling the right to use the bus that returns GNT1.

Next, referring to the timing chart of FIG.
U201 uses the local bus 205 to
During communication with PCT3, the PCIC 203 outputs a RETRY signal 207 as a bus cycle interrupt request to the arbiter 204.
The operation from disconnection to reconnection will be described.

In FIG. 3, first, when a bus request REQ0 is output from the CPU 201 to the arbiter 204, the arbiter 204 returns a bus use permission signal GNT0 to the CPU 201 assuming that the local bus 205 is free. CPU 2 receiving this bus use permission signal GNT0
01 outputs a HAVEIT signal and a BSTART signal (bus start signal) on the local bus,
9 to output necessary commands and data to the PCIC 203. The PCIC 203 further executes data writing or reading with another slave device connected to the PCI bus 208.

The PCIC 203 has a built-in timer 210 for monitoring time, and when it is determined that the local bus 205 has not been accessed for a predetermined time (for example, when reading data takes time). RETR which is a suspend request to release the local bus 205
The Y signal 207 is sent to the interruption / reconnection circuit 20 of the arbiter 204.
6 is output. The PCIC 203 is a PCI bus 20
Similarly, when an access request is received from the
The Y signal 207 is sent to the interruption / reconnection circuit 20 of the arbiter 204.
6 may be output.

Upon receiving the RETRY signal 207, the interruption / reconnection circuit 206 of the arbiter 204 sends the CPU 201 and the local bus 2 while maintaining the restart condition.
A bus disconnection signal 208 is output to the gate 209 to disconnect (interrupt) 05.

On the other hand, assuming that the bus request REQ1 has been output from the DMAC 202 before that, the arbiter 204 immediately returns the bus use permission signal GNT1 to the DMAC 202. HAVEIT from DMAC202
The local bus 205 is occupied by the DMAC 202, and data processing is performed with another device (not shown) on the local bus 205. When the data processing between the DMAC 202 and the other device is completed, the ACK signal is transmitted from the other device to the DMAC2.
02, and upon receiving this ACK signal, the DMAC 202 stops outputting the bus request signal REQ1.

When the bus request signal REQ1 stops, the arbiter 204 stops outputting the bus use permission signal GNT1 to the DMAC 202,
The bus use permission signal GNT0 for the U201 is output again, and the RESTRAT (restart) signal 211 is output to the PCIC 203.

The PCIC 203 that has received the RESTART signal 211 returns to the state immediately before the interruption by the signal from the interruption / reconnection circuit 206, and resumes the data processing with the CPU 201. When all data processing is completed, PCI
An ACK signal is output from the C 203 to the CPU 201, whereby the CPU 201 operates to stop the local bus access.

[0025]

According to the present invention, it is sufficient to provide only one disconnection / reconnection circuit in the arbiter without having a bus disconnection / reconnection circuit in the bus master, and thus the circuit amount can be reduced. Further, when a bus system having no retry mechanism is provided with a retry mechanism, it can be easily realized because it is only necessary to add a disconnection / reconnection circuit to the arbiter. Further, since the bus cycle identification circuit is not required for the bus slave performing the retry, the circuit amount can be reduced. In addition, there is an effect that a phenomenon in which read data is erroneously passed to a source other than the original read request source during delayed read does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a bus system to which the present invention is applied.

FIG. 2 is a second diagram in which the bus system of FIG. 1 is developed on an LSI.
1 shows the configuration of the embodiment.

FIG. 3 is a view showing operation timings of the system LSI shown in FIG. 2;

FIG. 4 is a diagram showing a configuration of a conventional bus system.

[Explanation of symbols]

 101, 204: Arbiter 102, 206 ... Interruption / reconnection circuit 105, 106 ... Bus master 107 ... Bus slave 108 ... Common bus 109, 209 ... Gate 201 ... CPU 202 ... DMAC 203 ... PCIC 205 ... Local bus 208 ... PCI bus 210 … Timer

Claims (4)

[Claims] In a bus system in which a plurality of bus masters and a bus slave generating a bus cycle interrupt request are connected to a common bus, an arbiter for controlling the right to use the bus issues the interrupt request from the bus slave. If received, the connection between the bus master acquiring the bus and the bus is interrupted and disconnected,
An arbiter having a retry control function, which performs connection between another bus master and the bus and reconnects the interrupted bus master and the bus when the bus use by the other bus master is completed. Bus system. 2. A system LSI wherein at least first and second bus masters not having a bus cycle interruption / reconnection function and a bus slave having a bus cycle interruption request function are connected to a common bus. A system LSI comprising an arbiter having a function of receiving a bus cycle interruption request and disconnecting a bus master being accessed from the common bus. 3. When the arbiter receives a bus cycle interrupt request from the bus slave, the connection between the first bus master acquiring the common bus and the common bus is temporarily interrupted and disconnected. 3. A connection between the second bus master and the common bus, and reconnection between the first bus master and the common bus when the bus use by the second bus master is completed. System LSI. 4. The method according to claim 1, wherein the first or second bus master comprises a CP.
4. The system LSI according to claim 2, wherein the system LSI is configured by a U or DMA controller, and the bus slave is configured by a PCI host bridge controller.