JP2002262099A - Picture processor and dma controller for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve burden on a processor and to efficiently compress a picture when compression data is stored and managed at each image, not in a whole one page but partially. SOLUTION: A compression core outputs a restart mark FF and RSTm after ending a compression processing concerning one strip. A write DMAC detects the restart mark, inserts a padding in order to align the words of data in the succeeding strip to be successively outputted and transfers it to a memory. In this case, the address of head data in each kind of word-aligned compression data is successively stored in a pointer arrayal area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and a DMA controller for an image processing apparatus.

[0002]

2. Description of the Related Art In a system for handling color images, since the amount of data is enormous, it is effective to reduce the memory capacity by compressing and handling image data. However,
To compress and manage data in page image units, it is necessary to rotate an image or generate a mirror image. As described above, since it is necessary to decompress the image of one page, the buffer memory naturally requires the capacity of one page, and the throughput of the entire process cannot be increased.

Therefore, it is conceivable to reduce the buffer memory and improve the throughput of image processing by compressing and managing an image for one page in units of a plurality of small images (tiles or strips).

[0004]

However, operating the image compression circuit for each small image means that a large number of start-up operations for compressing the entire page image and interrupt processing at short time intervals occur. Thus, there is a problem that a load is applied to the CPU.

[0005] When an image compression method such as JPEG is adopted, the entire page image can be compressed at once by inserting a restart marker (RSTm) at the end of the small image, and the small image portion can be divided. It is. However, in this case, it is necessary to search an address on the memory serving as a delimiter of the small image by software, and there is a problem that it takes a long time for the processing. When the image processing circuit processes the compressed small image, the start address of the small image needs to be placed at the word boundary.
In the continuous compression by insertion of m), the start address of the small image cannot be aligned with the word boundary, and the process of copying the compressed small image to the memory space starting from the word boundary is required to process the image processing circuit. There is a problem that more time is required because it is necessary.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and reduces the load on a processor when storing and managing compressed data for each partial image instead of one entire page. It is another object of the present invention to provide an image processing apparatus and a DMA controller for an image processing apparatus that enable efficient image compression.

In order to solve this problem, for example, an image processing apparatus according to the present invention has the following configuration. That is, an image processing apparatus that generates compressed image data, compresses data for each set data amount, adds a restart marker to the end of the compressed data, and outputs the compressed data. A first DMA unit for DMA-transferring the stored image data to be compressed to the compression unit, and a DMA transfer of the compressed data output from the compression unit to a memory space separate from the memory; And a second DMA unit that inserts padding and transfers the compressed data to be output after word-alignment of the compressed data to be output when the presence of the compressed data is detected.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a system configuration applied in the embodiment. Hereinafter, the configuration and operation will be described with reference to FIG.

An image scanned by the scanner 106 is taken into the multifunction controller 111 via the scanner interface 107. The captured image is stored in the main memory 103 via the crossbar circuit 104. CPU102
Activates the image compression circuit 101 when a predetermined amount of image is stored in the main memory 103, and activates the main memory 1
Data compression of the image stored in the storage unit 03 is started. When the image compression circuit 101 is activated, the read DMAC 1
01a reads the scanned image from the main memory 103 and sends it to the image compression core 101b. The image compression core 101b performs data compression on the received image image,
The compressed data is transferred to the write DMAC 101c. The write DMAC 101 c
The compressed data received from 1b is written back to the main memory 103. The write DMAC 101c constantly compares the data received from the image compression core 101b with a restart marker indicating a predetermined strip (small image). If a restart marker exists in the compressed data, the restart DMAC 101c restarts. The start marker is replaced with an end-of-image marker, padding data is packed to the next word boundary after the marker, and the compressed image is written back to the main memory 103.

The write DMAC 101c further shifts data following the marker to word alignment, receives further data from the image compression core 101b, combines the data, and continues writing data to the main memory 103 as head data of a strip. To go. At the same time, the write DMAC 101c writes the start address of the strip to an area of the main memory 103 different from the compressed data. The data thus compressed is stored in the main memory 103.
Multiple spools within. The spooled compressed image data is expanded by the image expansion circuit 112,
After being rotated by the image processing circuit 110, it is printed on paper by the printer 108 via the printer interface 109. In the case of the network scan operation, the spooled compressed image data is transferred to the host 11 via the network interface 105.
Sent to 3.

FIG. 2 is a schematic diagram showing an image configuration of the present embodiment. The page data (a) is managed by being divided into M strips (small images in the horizontal direction). The image compression method of this embodiment is JPEG. Therefore, one strip (b) is composed of a plurality (N × 4) of MCUs (c). One MCU (c) (pixel block) is 8
It consists of × 8 pixels. When activating the image compression circuit 101, the CPU 102
In b, a setting is made so that a restart marker is inserted for every N × 4 MCUs. As a result, the compressed data having the restart marker inserted at the boundary of the strip is transferred from the image compression core 101b to the write DMAC 101c.

The CPU 102 sets the data amount (the number of bytes) of one strip for the image compression core 101b in the image compression circuit 101. The image compression core 101b receives the set data amount, adds the restart mark described above every time the data is compressed, and outputs it to the write DMAC 101c.

Further, the CPU 102 operates the image compression circuit 1
The timing of activating 01 (read DMAC 101a) will be described in the above example. In the buffer of the main memory 103, data of 4 MCU read lines × M (M is an integer of 1 or more) = 32 × M lines are possible. When For example, when M = 2, two strips of data are DMA-transferred and compressed, and the result (compressed data for two strips) is stored in the main memory.

FIG. 3 is a schematic diagram showing a state of the image compression processing. Page image (a) is read DMAC10
1a, is read from the main memory 103 and sent to the image compression core 101b. The image compression core 101b writes the compressed data (b) in word units (32 bits in the embodiment) and writes the DMAC 101c.
Output to The write DMAC 101c stores the start address of the received compressed data as Pointer [0] of the pointer array area secured in the main memory 103, and stores the compressed data in the data area of the main memory 103.
(d). Since the write DMAC 101c has detected the restart marker (FF, RSTm) in the sixth word, it detects the end of the strip and inserts padding in the latter two bytes of this word (c). Since the next strip starts from the last two bytes of the word, the data is shifted, merged with the first two bytes of the following word to create word data, and written to the main memory 103. Write DMAC 1
01c simultaneously stores the head address of the strip in the pointer array area of the main memory 103 as Pointer [1].

FIG. 4 is a block diagram showing the configuration of the write DMAC 101c. Core interface 401
The sequencer 401a performs handshake with the image compression core 101b, receives compressed data from the image compression core 101b in word units, and temporarily stores the data in the register 401b. The data stored in the register 401b is
The word is sent to the marker detector 402 to detect whether the word includes a restart marker. When the restart marker is detected, the information is sent to the marker converter 403 and the shift amount holder 404, and the restart marker is converted into an end-of-image marker, and the shift amount after padding is updated. The compressed data that has passed through the marker converter 403 is padded and merged with the previous word by the padding / shifter 405. The merged data is held in the register 406, the held data is selected in units of bytes by the selector 407, temporarily stored in the register 408a in the memory access circuit 408, and the sequencer 408b communicates with the crossbar switch 104. The data is written back to the address of the main memory 103 indicated by the address counter 408c. When the marker detector 402 detects the restart marker, the padded data word is written into the main memory 103, and then the subsequent address is written by the memory access circuit 409 into the pointer storage area of the main memory 103.

As a result, according to the first embodiment,
At a minimum, one strip consisting of a plurality of pixel blocks is simply compressed, and the data for each compressed strip is successfully stored in a word-aligned state.

<Second Embodiment> FIG. 5 is a schematic diagram showing an image configuration of the second embodiment.

In the second embodiment, the page data (a)
Is divided into N × M tiles (small images) and managed. The image compression method according to the second embodiment is JP
Since it is an EG, the tile (b) has a plurality (4 × 4) of M
CU (c). MCU (c) is composed of 8 × 8 pixels. The CPU 102 controls the image compression circuit 10
1 is activated, the image compression core 101b has 4 ×
Set to insert a restart marker for every 4 = 16 MCUs. As a result, the compressed data with the restart marker inserted at the boundary of the tile is transferred from the image compression core 101b to the write DMAC 101c.

FIG. 6 is a schematic diagram showing a state of the image compression processing. Page image (a) is read DMAC10
1a, is read from the main memory 103 and sent to the image compression core 101b. The image compression core 101b writes the compressed data (b) in word units by DM.
Output to AC 101c. The write DMAC 101c stores the start address of the received compressed data in the main memory 1
03 is stored as Pointer [0] in the pointer array area,
The compressed data is stored in the data area of the main memory 103 (d). Since the write DMAC 101c has detected the restart marker (FF, RSTm) in the sixth word, it detects the end of the strip and inserts padding in the latter two bytes of this word (c). Since the next strip starts from the latter two bytes of the word, the data is shifted and merged with the first two bytes of the following word to create word data.
Write to the main memory 103. Write DMAC
At the same time, 101c stores the start address of the strip in the pointer array area of the main memory 103 as Pointer [1].

FIG. 7 is a schematic diagram showing a sequence in which the read DMAC 101a reads image data. In the second embodiment, in order to compress tiles in the same manner as in the first embodiment, a function of calculating a tile address is added to the read DMAC 101a in addition to the write DMAC 101c. Read DMAC 101a
Reads tile data in the order shown in FIG. In the tile, the read DMAC 101a reads the MCU data in the order shown in FIG. This gives 4 × 4 =
16 MCUs can be divided as one tile.

FIG. 8 is a block diagram showing the configuration of the read DMAC 101a. The base register 801 holds the top address of the page image data, and the tile address calculator 802 calculates the top address of the tile starting from this address. The address of the base register 801 is held in the register 802f when the selector 802e switches. When the tile is switched, the selectors 802c and 802e are switched, the offset of the horizontal tile movement stored in the horizontal offset register 802a is added by the adder 802d, and the start address of the next tile is stored in the register 801f. When the tile is updated in the vertical direction, the horizontal offset register 802b is added to the address. The head address output from the tile address calculator 802 is M
The data is input to the CU address calculator 803, and the head address of the MCU is calculated. The head address of this MCU is input to the pixel address calculator 804, and the address of the pixel is calculated. The sequencer 805 acquires the image data from the main memory 103 according to the pixel address data, and stores the acquired image data in the register 806. The data stored in the register 806 is converted into frame sequential data in the MCU by a dot sequential frame sequential conversion circuit 807 and sent to the image compression core 101b by the image compression core interface 808 to perform data compression.

As described above, according to the first and second embodiments, the load on the CPU is small, and a plurality of small images can be compressed at a time. Thus, the problem of address alignment of the small image head address is solved, and the need for marker search after compression is eliminated. This makes it possible to improve the throughput in an image system that manages a page image with a plurality of small images.

[0024]

As described above, according to the present invention, 1
When compressed data is stored and managed for each partial image instead of the entire page, the load on the processor can be reduced, and the image can be efficiently compressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration according to an embodiment.

FIG. 2 is a schematic diagram illustrating a configuration of an image according to the embodiment.

FIG. 3 is a diagram illustrating a relationship between an image compression process according to the embodiment and a transition of a data sequence.

FIG. 4 is a block diagram showing a configuration of a write DMAC 101c.

FIG. 5 is a schematic diagram illustrating a configuration of an image according to a second embodiment.

FIG. 6 is a diagram illustrating a relationship between an image compression process according to the second embodiment and a transition in the arrangement of data.

FIG. 7 is a read DMAC 101 according to the second embodiment.
FIG. 4 is a schematic diagram showing a sequence for reading image data of FIG.

FIG. 8 shows a read DMAC 101 according to the second embodiment.
FIG. 3 is a block diagram showing the configuration of FIG.

Claims (8)

[Claims] 1. An image processing apparatus for generating compressed image data, comprising: compression means for compressing data for each set data amount, adding a restart marker to the end of the compressed data, and outputting the compressed data; A first DMA unit that DMA-transfers image data to be compressed stored in the memory to the compression unit, and DMA-transfers the compressed data output from the compression unit to a memory space separate from the memory, An image processing apparatus comprising: a second DMA unit that inserts padding and transfers the compressed data that is subsequently output when the presence of the restart marker is detected, in order to output word-aligned compressed data. . 2. The image processing apparatus according to claim 1, wherein when the second DMA unit detects a restart marker, the second DMA unit replaces the restart marker with an end-of-image marker. 3. The apparatus according to claim 2, wherein said second DMA means includes means for sequentially storing, in a predetermined address pointer area, information indicating an address position of the first compressed data to be word-aligned and output. 3. The image processing apparatus according to claim 2. 4. The compression unit according to claim 1, wherein a minimum unit for compression is K.
2. The image processing apparatus according to claim 1, wherein a restart marker is added to each of a pixel block of × K bits and a strip including a plurality of pixel blocks. 5. The compression unit according to claim 1, wherein a minimum unit for compression is K.
2. The image processing apparatus according to claim 1, wherein a restart marker is added to each tile of a pixel block of × K bits, the tile including a plurality of pixel blocks. 6. A DMA controller for an image processing apparatus for compressing image data of a predetermined amount and adding a restart marker at the end and outputting the compressed data. First DMA transfer means for transferring, and when the restart marker is present in the data after compression, padding is inserted and transferred for outputting word-aligned compressed data to be subsequently output when the restart marker is present. A DMA controller for an image processing apparatus, comprising: two DMA units. 7. The DMA controller according to claim 6, wherein the second DMA unit replaces the restart marker with an end-of-image marker when detecting the restart marker. 8. The apparatus according to claim 1, wherein said second DMA means includes means for sequentially storing, in a predetermined address pointer area, information indicating the address position of the head compressed data to be output after word alignment. 8. A DMA controller for an image processing apparatus according to claim 7.