JP2002208863A - Turbo code decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the processing quantity of a processor and memory capacity required for it by a large amount and to optimize a system in a turbo encoding/ decoding device. SOLUTION: The device has a turbo encoding/decoding processing part 105 for decoding turbo encoding data, a data accumulation memory 104 for storing turbo encoding data supplied to a turbo encoding/decoding processing means and a rate dematching circuit 107 which subjects turbo encoding data which have been rate-matched to rate dematching. Turbo encoding data which is rate-matched is supplied to the data accumulation part. A rate dematching processing means reads turbo encoding data stored in the data accumulation part, performs rate dematching and rewrites the data in the data accumulation part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device which enables highly reliable data transmission over a communication channel having noise, and more particularly to a turbo code decoding device.

[0002]

2. Description of the Related Art In radio communication, convolutional codes and block codes have been used as error correction codes. In the decoding process of these codes, the processing unit was small and the decoding processing time was short, so the memory capacity required to hold the data at the time of decoding was small, the time to hold the data was short, and the memory was used efficiently. can do.

[0003] In addition, error-correction-encoded data is subjected to a rate matching process in which a portion of data is repeated or thinned out in order to match a transmission frame. In the decoding process, a rate dematching process for restoring data that has been repeated or thinned out in the pre-processing is performed. Error correction using a convolutional code or a block code requires a small amount of data for error correction decoding, so that even if processing is performed by a processor, the processing load is small.

On the other hand, the turbo code, which is the latest error correction code, has a feature that the decoding result is fed back and the decoding process is repeated, and in order to obtain a sufficient decoding gain, the data length of the decoding process must be increased. There is a feature that does not become. For this reason, a large memory capacity for holding the data to be decoded is required, and the data holding time is also long due to the iterative decoding process.

[0005] Therefore, when configuring a turbo code decoding device, a dedicated data storage memory is required. Further, when the processor performs the rate dematching process, which is the preprocessing, the amount of data handled by the turbo code decoding circuit is large, so that the memory capacity required by the processor also increases.

FIG. 7 shows a circuit configuration of a conventional turbo code decoding device. The turbo code decoding circuit 106 includes a data storage memory 104 and a turbo code decoding processing unit 105. The data storage memory 104 further includes a data storage memory 101 for holding information data X,
Data storage memory 10 for holding inspection data Y of
2 and a data storage memory 103 for holding the second inspection data Z.
The turbo code decoding circuit 1 further includes a processor 108.
Before passing the encoded data to 06, rate dematch processing is performed.

[0007] In FIG. 7, the received data is passed to a data storage memory 104 after being subjected to rate dematch processing by a processor 108. The turbo code decoding processing unit 105 repeatedly uses the data stored in the data storage memory 104 to obtain a decoding result.

[0008]

However, in the above-mentioned conventional method, when a code such as a turbo code has a large amount of data to be processed in a decoding process, not only a dedicated data storage memory is required but also a processor. And the amount of memory required for that process also increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. In a turbo code decoding apparatus, a turbo code capable of greatly reducing a processing amount of a processor and a memory capacity required for the processor is provided. It is an object to provide a decoding device.

[0010]

According to a first aspect of the present invention, there is provided a turbo code decoding apparatus for decoding turbo encoded data.
5), a data storage unit (data storage memory 104) for storing turbo encoded data to be supplied to the turbo code decoding processing unit, and a rate dematching process for rate dematching the rate matched turbo encoded data. (Rate dematch circuit 107), and the data storage section is supplied with turbo-coded data subjected to the rate matching process, and the rate dematch processing section is provided with a turbo code stored in the data storage section. After reading out the coded data and performing the rate dematching process, the data is written into the data storage unit again.

[0011] According to a second aspect of the present invention, there is provided a turbo code decoding apparatus.
The data storage means includes three memory blocks (data storage memories 101, 102, 103), an address generation means (address generation circuit 302) for generating a common address for the memory blocks, and one of the memory blocks. And a memory block selecting means (memory block selecting circuit 301) for selecting one.

According to the first aspect of the present invention, the storage means for storing the turbo coded data supplied to the turbo code decoding processing and the data necessary for the rate dematch processing are stored. By sharing the storage means, there is no need to newly add a memory for the rate matching process, and the processor amount can be reduced by providing the dedicated rate matching processing means.

According to the turbo code decoding apparatus of the second aspect, it is only necessary to sequentially access three memory blocks specifying the same address without being aware of the three memory blocks. can do.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a turbo code decoding device according to one embodiment of the present invention. As shown in FIG. 1, a turbo code decoding device includes a turbo code decoding circuit 106 having a data storage memory 104 and a turbo code decoding processing unit 105, and a rate dematch processing for data stored in the data storage memory 104. And a rate dematch circuit 107 for performing The data storage memory 104 further includes a data storage memory 101 for storing information data X, a data storage memory 102 for storing first test data Y, and data for storing second test data Z. The storage memory 103 includes three memory blocks. Turbo code decoding circuit 1
The data stored in the data storage memory 104 is supplied with the rate-matched received data from the processor 108.

FIG. 2 shows a circuit configuration of the rate dematch circuit 107 shown in FIG. Rate dematch circuit 1
07, a read control circuit 201 for reading data from the data storage memory 104, a position determination circuit 202 for specifying a data position where degeneration or repetition has been performed by rate mismatch processing, Write control circuit 203, and arithmetic circuit 204 for performing addition processing and averaging processing of data repeatedly calculated by rate dematch processing and the immediately preceding data
And a flip-flop 2 for holding the immediately preceding data
05.

Next, the operation of the turbo code decoding device will be described. In order to perform turbo code decoding, the data storage memory 104 has an address structure as shown in FIG. In FIG. 3, RAM1, RAM2, and RAM3 are:
The data storage memory 101, the data storage memory 102, and the data storage memory 103 respectively belong to the memory blocks. That is, the data storage memory 101
3n, 3n + 1 is assigned to the data storage memory 102, and 3n + 2 (n is an arbitrary integer) is assigned to the data storage memory 103 as virtual addresses.

FIG. 4 shows the state of the data stored in the data storage memory in the rate dematch processing, where X is the information data, Y is the first inspection data, and Z is the second inspection data. The stored data before the rate match is X
0, X0, Y0, Z0, X1, Y1, Z1, X2, X
Data in which X0 and X2 are repeated such as 2, Y2, and Z2 are written. In order to decode the turbo code, X0 and X2 repeated by the rate matching process are deleted, information data X is written in RAM1, test data Y is written in RAM2, and test data Z is written in RAM3. Need to be.

As before the rate match processing in FIG. 4, data X0 is read from the virtual address 0 by the read control circuit 201 for the stored data. Data X0
Passes through the arithmetic circuit 204, but when the immediately preceding data is not stored in the flip-flop 205, the arithmetic is not performed. At this time, since the position determination circuit 202 indicates that the data X0 is repeated data, the data X0 is stored in the flip-flop 205. next,
The data X0 is read from the virtual address 1, the data X0 of the virtual address 0 stored in the flip-flop 205 is operated on by the arithmetic circuit 204, and the result is written back to the virtual address 0 by the write control circuit 203.

Next, data Y0 is read from virtual address 2. Since the data Y0 is not repeated data, it is written back to the virtual address 1 without any arithmetic processing. By repeating this process, the information data X is stored in the data storage memory 101, the first test data Y is stored in the data storage memory 102, and the second test data Z is stored in the data storage memory 103.

By providing the rate dematch circuit configured as described above and sharing the data storage memory constituting the turbo code decoding circuit between the rate dematch circuit and the turbo code decoding circuit, processing by the conventional processor is required. However, the processing time of the processor for the rate matching process and the memory required for the processing can be reduced.

FIG. 5 is a configuration diagram of an address circuit of a data storage memory constituting a turbo code decoding circuit according to an embodiment of the present invention. As shown in FIG. 5, the data storage memory 104 is composed of three memory blocks of a data storage memory 101, a data storage memory 102, and a data storage memory 103, and a rate dematch circuit 107 is stored in the data storage memory 104. Perform rate dematch processing on the received data. Further, the memory block selection circuit 301 generates a signal for selecting one of the memory blocks of the data storage memory 101, the data storage memory 102, and the data storage memory 103, and outputs the signal to the address generation circuit 30.
2 is a data storage memory 101, a data storage memory 10
2. Generate an address common to the three memory blocks of the data storage memory 103.

To access the data storage memory 104 managed by the virtual address shown in FIG. 3 by specifying the address, the specified address is divided by 3 to obtain the data storage memory 101. Selecting one of the three memory blocks, the data storage memory 102 and the data storage memory 103;
01, data storage memory 102, data storage memory 10
3 needs to be converted to a physical address. However, a circuit that divides an address by 3 has a large scale and a large delay time. Therefore, there is a disadvantage that an access cycle becomes slow and a time required for data transfer increases.

In the address circuit shown in FIG. 5, access to the data storage memory 104 is performed in conjunction with the selection of a memory block and the address generation circuit. The memory block selection circuit 301 includes a data storage memory 101,
The data storage memory 102 and the data storage memory 103 are sequentially cyclically selected, and when the storage memory 101 is selected next to the data storage memory 103, the address of the address generation circuit 302 is advanced by one.

For example, when data is written from the processor to the data storage memory 104, the processor
Write to a single address in the same way as write to.
On the other hand, the memory block selection circuit 301 cyclically selects a memory block to be written every time data is written, as the data storage memory 101, the data storage memory 102, the data storage memory 103, and the data storage memory 101. When moving from the storage memory 103 to the data storage memory 101, the address generation circuit 301
Performs address increment. Therefore, the processor only needs to perform the same operation as writing to the FIFO, and does not need to include an arithmetic circuit in the address decoder.
Interface can be speeded up.

FIG. 6 is a configuration diagram when the turbo code decoding device described in the above embodiment is applied to a receiving device. As shown in FIG. 6, after the received data is demodulated by the demodulator 601, the received data is decoded by the turbo code decoding device 602 according to the above embodiment, and is input to the channel forming circuit 603 to form a channel. By configuring the receiving device in this manner, the memory capacity required for the entire system can be reduced.

[0026]

As described above, according to the present invention,
By sharing storage means for storing turbo encoded data supplied to turbo code decoding processing and storage means for storing data necessary for rate dematch processing, for rate dematch processing There is no need to newly add a memory, and by providing a dedicated rate-dematch processing unit, the processing amount of the processor can be reduced as compared with the case where rate-dematch processing is performed by a conventional processor.

Furthermore, the speed of the interface can be increased by automatically selecting one memory block sequentially from the three data storage memory blocks specified by the common address.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a turbo code decoding device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a rate dematch circuit of the turbo code decoding device of the present invention.

FIG. 3 is a diagram showing a memory map of a data storage memory in the turbo code decoding device of the present invention.

FIG. 4 is a diagram showing a memory image of rate dematch processing in the turbo code decoding device of the present invention.

FIG. 5 is a diagram showing a configuration of an address circuit of a data storage memory of the turbo code decoding device of the present invention.

FIG. 6 is a diagram showing a configuration of a receiving device to which the turbo code decoding device of the present invention is applied.

FIG. 7 is a diagram showing a configuration of a conventional turbo code decoding device.

[Explanation of symbols]

 101, 102, 103 Data storage memory block 104 Data storage memory 105 Turbo code decoding processing unit 106 Turbo code decoding circuit 107 Rate dematch circuit 108 Processor 201 Read control circuit 202 Position determination circuit 203 Write control circuit 204 Operation circuit 205 Flip-flop 301 Memory block selection circuit 302 Address generation circuit 601 Demodulator 602 Turbo code decoder 603 Channel formation circuit

Claims (3)

[Claims] 1. A turbo code decoding processing means for decoding turbo encoded data, a data storage unit for storing turbo encoded data to be supplied to the turbo code decoding processing means, and a turbo code data subjected to rate matching processing. Rate dematch processing means for performing rate dematch processing, and the turbo coded data subjected to the rate match processing is supplied to the data storage unit, and the rate dematch processing means,
A turbo code decoding apparatus, comprising: reading out turbo encoded data stored in the data storage unit, performing rate dematch processing, and writing the data again into the data storage unit. 2. The data storage means comprises three memory blocks, an address generating means for generating a common address for the memory blocks, and a memory block selecting means for selecting one of the memory blocks. The turbo code decoding device according to claim 1, further comprising: 3. The turbo according to claim 1, wherein a demodulator for demodulating received data to generate turbo-coded demodulated data subjected to rate matching processing, and generating decoded data for the demodulated data. An encoding / decoding device, a channel forming circuit that generates channel data from the decoded data,
A receiving device comprising: