CN112820343A - Data protection method and device, computer equipment and storage medium - Google Patents
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- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention relates to a data protection method, a data protection device, computer equipment and a storage medium; the method comprises the following steps: acquiring write command data, and performing data bit width conversion on the write command data to obtain conversion data; performing read-rewrite verification on the conversion data; if the verification is passed, changing the write operation command into a read operation command, and storing the conversion data; sending the read operation command to an SRAM, reading the conversion data by the SRAM, and decoding the conversion data to obtain decoded data; according to the decoded data, covering and encoding the converted data to obtain encoded data; the encoded data is written into the SRAM. The invention solves the problem that the performance of the SRAM is influenced by the read-write operation, consumes little logic, supports multi-mode data protection and can better meet the requirement.
Description
Technical Field
The present invention relates to the field of data protection technologies, and in particular, to a data protection method, apparatus, computer device, and storage medium.
Background
In the current SRAM data protection technology, if hmecc (hamming error check and error correction technology) is adopted, because extra data protection bits are needed for supporting error correction and error detection, for example, hmecc-128 technology, which is to perform hmecc protection every 128 bits, 9 bits need to be additionally added to complete 1-bit error correction and 2-bit error detection functions, if there is a write that does not satisfy 128 bits, for example: byte/half word/double word, because of hmecc-128, RMW operation (read modify write) is required, which affects SRAM access performance.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a data protection method, a data protection device, a computer device and a storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme:
the data protection method comprises the following steps:
acquiring write command data, and performing data bit width conversion on the write command data to obtain conversion data;
performing read-rewrite verification on the conversion data;
if the verification is passed, changing the write operation command into a read operation command, and storing the conversion data;
sending the read operation command to an SRAM, reading the conversion data by the SRAM, and decoding the conversion data to obtain decoded data;
according to the decoded data, covering and encoding the converted data to obtain encoded data;
the encoded data is written into the SRAM.
The further technical scheme is as follows: in the step of obtaining the write command data and performing data bit width conversion on the write command data to obtain the converted data, the data bit width is converted into a data bit width which is changed from 128 to 256.
The further technical scheme is as follows: in the step of verifying the read-over-write of the conversion data, if the conversion data is less than 128 bits, the verification is not passed.
The further technical scheme is as follows: after the step of writing the coded data into the SRAM, the method further includes:
acquiring new write command data, and pressing the new write command data into a first-in first-out queue;
when the SRAM is idle, acquiring new write command data from the first-in first-out queue, and encoding the new write command data to obtain new encoded data;
and adding check bits to the newly encoded data, and then writing the newly encoded data into the SRAM.
A data protection device comprising: the device comprises an acquisition conversion unit, a verification unit, a storage unit, a sending reading decoding unit, an encoding unit and a writing unit;
the acquisition conversion unit is used for acquiring write command data and performing data bit width conversion on the write command data to obtain conversion data;
the verification unit is used for performing read-rewrite verification on the conversion data;
the change-to-save unit is used for changing the write operation command into a read operation command and saving the conversion data;
the sending and reading decoding unit is used for sending the reading operation command to the SRAM, and the SRAM reads the conversion data and decodes the conversion data to obtain decoding data;
the encoding unit is used for covering and encoding the conversion data according to the decoding data to obtain encoded data;
the writing unit is used for writing the coded data into the SRAM.
The further technical scheme is as follows: in the acquisition conversion unit, the conversion of the data bit width into the data bit width is changed from 128 to 256.
The further technical scheme is as follows: in the verification unit, if the conversion data is less than 128 bits, the verification is not passed.
The further technical scheme is as follows: further comprising: the device comprises an acquisition pressing unit, an acquisition coding unit and an addition writing unit;
the acquisition and press-in unit is used for acquiring new write command data and pressing the new write command data into a first-in first-out queue;
the acquisition coding unit is used for acquiring new write command data from the first-in first-out queue when the SRAM is idle, and coding the new write command data to obtain new coded data;
and the adding and writing unit is used for adding a check bit to the newly encoded data and then writing the check bit into the SRAM.
A computer device comprising a memory having a computer program stored thereon and a processor that, when executed, implements a data protection method as described above.
A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a data protection method as described above.
Compared with the prior art, the invention has the beneficial effects that: the problem that the performance of the SRAM is influenced by read-write operation is solved, little logic is consumed, multi-mode data protection is supported, and the requirements can be better met.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a data protection method according to an embodiment of the present invention;
fig. 2 is a first schematic application diagram of a data protection method according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an application of the data protection method according to the embodiment of the present invention;
FIG. 4 is a schematic block diagram of a data protection apparatus provided by an embodiment of the present invention;
FIG. 5 is a schematic block diagram of a computer device provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to the embodiments shown in fig. 1 to 5, wherein, referring to fig. 1 to 3, the present invention discloses a data protection method, comprising the following steps:
s1, acquiring write command data, and performing data bit width conversion on the write command data to obtain conversion data;
here, in step S1, the data bit width is converted from 128 to 256.
S2, performing read-rewrite verification on the converted data;
as shown in fig. 2, the RMW determination module performs read-rewrite verification on the conversion data, and if the conversion data is less than 128 bits, the verification fails, and normal operation is performed; if the transformed data is greater than 128 bits, the verification passes.
S3, if the verification is passed, changing the write operation command into a read operation command and saving the conversion data;
among them, in the present embodiment, by directly changing the control signal from writing to reading, it is simple and fast.
S4, sending the read operation command to the SRAM, reading the conversion data by the SRAM, and decoding the conversion data to obtain decoded data;
the conversion data is decoded by DEC to obtain 256-bit decoded data; if ECC error (error checking and correcting errors) occurs in the decoding process, the feedback is reported.
S5, according to the decoded data, covering and encoding the converted data to obtain encoded data;
in this embodiment, the conversion data is covered and encoded, using hmecc128(128bit for hmecc check), if 64 bits are written only, 128 bits need to be read out, then 64 bits therein are covered, and then hmecc encoding is performed to obtain encoded data.
And S6, writing the coded data into the SRAM.
After the step of S6, the method further includes:
s7, acquiring new write command data and pressing the new write command data into a first-in first-out queue;
s8, when the SRAM is idle, new write command data are obtained from the first-in first-out queue, and the new write command data are encoded to obtain new encoded data;
and S9, adding a check bit to the newly encoded data, and then writing the newly encoded data into the SRAM.
As shown in fig. 2 and 3, the terms are explained as follows:
parallel module conversion: because of the performance loss caused by RMW, the bus is idled for the insertion of read cmd by the parallel module translation.
RMW judging module: the read-rewrite judging module is used for triggering RMW operation, namely reading, changing and writing firstly, if the read-rewrite judging module finds that the write is less than 128 bits through a command.
WR FIF0 (first in first out): all writes (whether normal or RMW writes) are pushed into WR FIF0, ensuring read priority, and once the read is idle, data is automatically fetched from WR FIF0 and written into SRAM.
ENC: data coding, check bit addition, 128-bit hmecc support, 128-bit parity protection support, and signal selection can be controlled to specifically use which code
DEC: and data decoding, namely reading and decoding the data from the SRAM, sending the data to the RMW module, and if the data is read in RMW, rewriting the data based on the read data and then pressing the data back to FIF 0.
In this embodiment, if the read-write operation is not triggered, the following steps are performed:
as shown in fig. 2 and 3, the writing step:
the data bit width of the write command data command is changed from 128 to 256 through the parallel conversion module;
if the RMW is not triggered, no special treatment is carried out through the RMW judging module;
pushing write command data into WR FIF0 (first in first out queue);
when the SRAM is idle (no read-write command), command data is taken from WRFIF0, written to the ENC module for encoding, added with check bits after encoding, and then written to the SRAM.
A reading step:
the read command is sent to the SRAM through the parallel conversion module, and the SRAM returns data;
reading data and obtaining 256bit data through a DEC module; if ECC error appears, reporting out (depending on the application, if bus, reporting to the bus);
and then sent to the RMW module to find non-RMW operations (for example, using hmecc128, only 128-bit data write is non-RMW), and directly sent to the bit width conversion (see the example illustrated in fig. 2) to obtain 128-bit data.
The invention solves the problem that the performance of the SRAM is influenced by the read-write operation, consumes little logic, supports multi-mode data protection and can better meet the requirement.
Referring to fig. 4, the present invention also discloses a data protection device, including: an acquisition conversion unit 10, a verification unit 20, a change-to-save unit 30, a transmission read decoding unit 40, an encoding unit 50, and a writing unit 60;
the acquiring and converting unit 10 is configured to acquire write command data and perform data bit width conversion on the write command data to obtain conversion data;
the verification unit 20 is used for performing read-overwrite verification on the conversion data;
the change-to-save unit 30 changes the write operation command into the read operation command, and saves the converted data;
the sending and reading decoding unit 40 is configured to send a read operation command to the SRAM, where the SRAM reads the conversion data and decodes the conversion data to obtain decoded data;
the encoding unit 50 is configured to cover and encode the converted data according to the decoded data to obtain encoded data;
the writing unit 60 is configured to write the encoded data into the SRAM.
In the acquisition conversion unit 10, the data bit width is converted from 128 to 256.
In the verification unit 20, if the conversion data is less than 128 bits, the verification fails.
Wherein, the device still includes: an acquisition pushing unit 70, an acquisition encoding unit 80, and an addition writing unit 90;
the acquiring and pushing unit 70 is configured to acquire new write command data and push the new write command data into a first-in first-out queue;
the acquiring and encoding unit 80 is configured to acquire new write command data from the first-in first-out queue when the SRAM is idle, and encode the new write command data to obtain new encoded data;
the add write unit 90 is configured to add a check bit to the newly encoded data and then write the newly encoded data into the SRAM.
It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation processes of the data protection device and each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is provided herein.
The data protection means described above may be implemented in the form of a computer program which is executable on a computer device as shown in fig. 5.
Referring to fig. 5, fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.
Referring to fig. 5, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a data protection method.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can be enabled to execute a data protection method.
The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 5 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
It should be understood that, in the embodiment of the present Application, the processor 502 may be a Central Processing Unit (CPU), and the processor 502 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions which, when executed by a processor, implement the data protection method described above.
The storage medium may be a usb disk, a removable hard disk, a Read-only Memory (ROM), a magnetic disk or an optical disk, and various computer readable storage media that can store program codes.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. The data protection method is characterized by comprising the following steps:
acquiring write command data, and performing data bit width conversion on the write command data to obtain conversion data;
performing read-rewrite verification on the conversion data;
if the verification is passed, changing the write operation command into a read operation command, and storing the conversion data;
sending the read operation command to an SRAM, reading the conversion data by the SRAM, and decoding the conversion data to obtain decoded data;
according to the decoded data, covering and encoding the converted data to obtain encoded data;
the encoded data is written into the SRAM.
2. The data protection method according to claim 1, wherein in the step of obtaining the write command data and performing data bit width conversion on the write command data to obtain the converted data, the data bit width conversion is changed from 128 to 256.
3. The data protection method of claim 1, wherein in the step of performing read-write-over-write verification on the transformed data, if the transformed data is less than 128 bits, the verification is not passed.
4. The data protection method of claim 1, wherein after the step of writing the encoded data into the SRAM, further comprising:
acquiring new write command data, and pressing the new write command data into a first-in first-out queue;
when the SRAM is idle, acquiring new write command data from the first-in first-out queue, and encoding the new write command data to obtain new encoded data;
and adding check bits to the newly encoded data, and then writing the newly encoded data into the SRAM.
5. A data protection device, comprising: the device comprises an acquisition conversion unit, a verification unit, a storage unit, a sending reading decoding unit, an encoding unit and a writing unit;
the acquisition conversion unit is used for acquiring write command data and performing data bit width conversion on the write command data to obtain conversion data;
the verification unit is used for performing read-rewrite verification on the conversion data;
the change-to-save unit is used for changing the write operation command into a read operation command and saving the conversion data;
the sending and reading decoding unit is used for sending the reading operation command to the SRAM, and the SRAM reads the conversion data and decodes the conversion data to obtain decoding data;
the encoding unit is used for covering and encoding the conversion data according to the decoding data to obtain encoded data;
the writing unit is used for writing the coded data into the SRAM.
6. The data protection device of claim 5, wherein in the obtaining conversion unit, the conversion of the data bit width into the data bit width is changed from 128 to 256.
7. The data protection device of claim 5, wherein in the verification unit, if the transformed data is less than 128 bits, the verification fails.
8. The data protection device of claim 5, further comprising: the device comprises an acquisition pressing unit, an acquisition coding unit and an addition writing unit;
the acquisition and press-in unit is used for acquiring new write command data and pressing the new write command data into a first-in first-out queue;
the acquisition coding unit is used for acquiring new write command data from the first-in first-out queue when the SRAM is idle, and coding the new write command data to obtain new coded data;
and the adding and writing unit is used for adding a check bit to the newly encoded data and then writing the check bit into the SRAM.
9. A computer device, characterized in that the computer device comprises a memory, on which a computer program is stored, and a processor, which when executing the computer program implements the data protection method according to any one of claims 1-4.
10. A storage medium, characterized in that the storage medium stores a computer program comprising program instructions which, when executed by a processor, implement the data protection method according to any one of claims 1-4.
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