JP2002197880A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which write time and erasure time of a memory cell can be shortened, and an execution time of write and erase can be changed by a user command in accordance with usage. SOLUTION: In a nonvolatile semiconductor memory 45, voltage applied to a drain from a drain/source voltage setting circuit 41 when data is written in a memory cell 34 and voltage applied to a source from a drain/source voltage setting circuit 41 when data of a memory cell 34 is erased are switched to the prescribed value and applied. Also, at the time of an operation test before shipping, the number of write and erase pulses and an optimum value of drain voltage and source voltage in a range in which over-stress is not given to a memory cell are measured. And respective measured value is recorded in a test information storing memory 39.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device which is electrically writable and erasable and can control a data writing and erasing speed.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device is a memory which can hold data without backing up a power supply and which can be electrically written and erased.
EPROM is widespread. Among EEPROMs, flash memories, in particular, have relatively large capacities and can rewrite data on the system, so that applications to applications such as mobile phones are rapidly expanding.

This flash memory has a configuration as shown in FIG. FIG. 1 is a schematic sectional view of one memory cell in a NOR flash memory. The memory cell is a MOS transistor, and has a configuration in which a floating gate 7 is arranged between a source 1 and a drain 8 and a gate (control gate) 6 as shown in FIG. In a flash memory, data is stored in a memory cell by transferring charges into and out of a floating gate 7 of a MOS transistor. As a result, the threshold value of the transistor fluctuates, and this is extracted in the form of current on / off, and the data “1”, “0”
Is associated with.

FIG. 1A shows a state of a voltage applied to each part at the time of writing in a nonvolatile semiconductor memory.
Electrons (hot electrons) 9 are generated by grounding the source terminal 2 of the MOS transistor to ground, applying a predetermined gate voltage Vdd to the drain terminal 4 and applying a gate voltage Vgg to the gate terminal 3. Then, by taking the electrons 9 into the floating gate 7 through the tunnel oxide film 10, writing in the nonvolatile semiconductor memory can be performed (a method of injecting charges into the floating gate by hot electrons).

FIG. 1B shows the state of voltage applied to each part when erasing the nonvolatile semiconductor memory. MOS
By setting the drain terminal 15 of the transistor to the open state, applying the source voltage Vss to the source terminal 13 and applying the gate voltage Vgg to the gate terminal 14, an electric field is generated between the gate and the source, and the floating effect is caused by the tunnel effect. By extracting the 17 electrons to the source side through the tunnel oxide film 20, erasing of the nonvolatile semiconductor memory can be performed (a method of extracting charges to a source or a substrate using a tunnel phenomenon by a high electric field). The non-volatile semiconductor integrated circuit has a configuration including a plurality of memory cell transistors as shown in FIG. 1, which allows a large amount of data to be stored.

[0006] However, if the threshold value fluctuates greatly when writing data to the memory cell transistor, the charge held by the floating gate varies. Therefore, if the writing is not successful, the writing and checking (verify) must be repeated many times until the writing is completed, and there is a problem that the data writing time increases.

Therefore, in order to solve the above problem, for example, Japanese Patent Application Laid-Open No. H07-037395 discloses a technique relating to a nonvolatile semiconductor memory device capable of preventing an increase in writing time and narrowing a threshold distribution. Have been. Also, Japanese Patent Application Laid-Open No. 2000-113686 relates to a writing method and a recording medium of a nonvolatile semiconductor memory device which realizes a narrowing of a threshold distribution of a memory cell after writing, and a shortening of a writing time or a reduction of a writing stress. Techniques are disclosed.

[0008]

However, the nonvolatile semiconductor memory device disclosed in Japanese Patent Laid-Open Publication No.
It merely states that a means for changing the writing condition is provided, but no specific means is shown as the writing variable means that can be changed depending on the application.

Japanese Patent Application Laid-Open No. 2000-113686 discloses that “a threshold value of a memory cell is measured before and after a first write signal is applied to the memory cell, and a write operation is performed based on the measured threshold value of the memory cell. Determine the conditions,
A write signal corresponding to the determined write condition is applied to the memory cell, or a threshold of the memory cell is measured before and after the write signal is applied, and the write condition is determined based on the measured threshold of the memory cell. Determined, a change in the threshold value of the memory cell when a write signal corresponding to the determined write condition is applied to the memory cell is detected, and a write time during which the change is within a predetermined reference value is detected. Writing is performed, and writing to the memory cell is repeatedly performed until the threshold value after the writing reaches a predetermined reference value. "

However, when writing is performed by the method described in Japanese Patent Application Laid-Open No. 2000-113686, “threshold value measurement before and after pulse application” and “necessary Switching of the internal high-voltage circuit from the write pulse application mode to the threshold measurement mode is required, and the execution write time becomes longer. In addition, a change in threshold voltage must be measured in order to judge the write characteristics of the memory cell at each write, so that much time needs to be spent for the measurement, and the net execution time is not shortened. Furthermore, for example, in a NOR type nonvolatile semiconductor memory device, writing is performed in units of words or bytes, whereas erasing is performed in units of, for example, 64 kbyte blocks. Therefore, erasing time is generally longer than writing time. Will be much longer. However, no means for effectively shortening the erasing time is disclosed. Therefore,
The effect of improving the function of the nonvolatile semiconductor memory device is insufficient.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned problem, and an object of the present invention is to make it possible to shorten the time for writing and erasing a memory cell, and to write and erase by a user command. The purpose of the present invention is to provide a nonvolatile semiconductor memory device capable of changing the execution time of the nonvolatile semiconductor memory device according to the application.

[0012]

The present invention has the following arrangement as means for solving the above-mentioned problems.

(1) A nonvolatile semiconductor memory having a plurality of blocks constituted by a plurality of electrically readable and erasable memory cells, and a voltage for writing and erasing information in the nonvolatile semiconductor memory. A high-voltage power supply to be supplied, a microcode storage unit that stores a microcode selectable by an external command, and an operation of writing and erasing information to and from the nonvolatile semiconductor memory according to the microcode selected by the external command. And a write / erase control unit for controlling, the voltage applied from the high-voltage power supply unit is adjusted to obtain a voltage at which data can be written to the nonvolatile semiconductor memory and a voltage at which data can be erased. A write / erase voltage switching unit capable of switching to an arbitrary value is provided.

In this configuration, the nonvolatile semiconductor memory device includes a nonvolatile semiconductor memory having a plurality of blocks each including a plurality of electrically readable and erasable memory cells, and a nonvolatile semiconductor memory. A high-voltage power supply for supplying a voltage for writing and erasing information; a microcode storage for storing a microcode selectable by an external command; and a microcode storage for storing the microcode selected by the external command. A write / erase control unit for controlling the operation of writing and erasing of information, and a voltage applied from the high-voltage power supply unit, which can be arbitrarily set as a voltage for writing data to the nonvolatile semiconductor memory and a voltage for erasing data. And a write / erase voltage switching unit capable of switching to the value of Therefore, the nonvolatile semiconductor memory has a characteristic that the data erasing time becomes shorter as the erasing (source) voltage becomes higher, and the data writing time becomes shorter as the writing (drain) voltage becomes higher. Therefore, the writing / erasing time of the semiconductor memory can be controlled. Further, by setting a plurality of modes according to the voltage applied to the nonvolatile semiconductor memory, the nonvolatile semiconductor memory device can be used according to the application.

(2) A write / read memory for storing a write test pass data of a write pulse voltage value and a pulse width and an erase pulse voltage value and a pulse width of an erase test pass data to the nonvolatile semiconductor memory during an operation test. An erase voltage storage unit, the write / erase voltage switching unit adjusts a voltage applied from a high voltage power supply unit based on data stored in the write / erase voltage storage unit,
It is characterized in that the voltage is switched to an arbitrary value as a voltage at which data can be written to the nonvolatile semiconductor memory and a voltage at which data can be erased.

In this configuration, at the time of the operation test stored in the write / erase voltage storage section, the write test pass data of the write value and the pulse width of the write pulse to the nonvolatile semiconductor memory, and the voltage value and the pulse width of the erase pulse The voltage applied from the high-voltage power supply unit is adjusted based on the erase test pass data of (i), and the voltage is switched to an arbitrary value as a voltage at which data can be written to the nonvolatile semiconductor memory and a voltage at which data can be erased. Therefore, the writing and erasing characteristics of the non-volatile semiconductor memory fluctuate due to variations in processes and the like at the time of mass production.・ By storing the data in the erase voltage storage section, a normal write or erase pulse is applied, and then a write or erase verify is performed. If the write or erase is insufficient, the write or erase pulse is applied again and the verify operation is performed. However, the write / erase control unit that controls the write / erase algorithm accesses the write / erase voltage storage unit that stores the test data of each nonvolatile semiconductor memory, and uses that data to perform the nonvolatile operation. Pulse width or erase The scan width was variable, since it is the optimum setting, it is possible to operate with a single pulse application bets base Rifai is complete. In addition, since the circuit overhead time related to the mode switching between the writing or erasing and the verify can be minimized, the writing and erasing time can be shortened.

(3) In the configuration of (2), the write / read
The erase voltage storage unit stores a voltage value and a pulse width of a write pulse to the nonvolatile semiconductor memory measured during an operation test for each block, and stores a voltage value and a pulse width of an erase pulse for each block. can do.

In this configuration, the voltage value and pulse width of the write pulse to the nonvolatile semiconductor memory measured during the operation test are stored for each block, and the voltage value and pulse width of the erase pulse are stored for each block. The non-volatile semiconductor storage device includes a write / erase voltage storage unit to be written. Therefore, when writing data to the nonvolatile semiconductor memory, data can be written for each memory cell, and when erasing data for the nonvolatile semiconductor memory, data can be erased for each block. .

(4) The write / erase voltage switching unit includes: a write pulse voltage value and a write pulse width for the nonvolatile semiconductor memory cell stored in the write / erase voltage storage unit; The pulse width can be switched to an arbitrary value.

In this configuration, the voltage value and the pulse width of the write pulse to the nonvolatile semiconductor memory cell and the voltage value and the pulse width of the erase pulse stored in the write / erase voltage storage section are set to arbitrary values. The nonvolatile semiconductor memory device includes a switchable write / erase voltage switching unit. Therefore, even if the characteristics of individual nonvolatile semiconductor memories vary due to process dispersion, it is possible to correct the writing or erasing voltage and pulse width to arbitrary values based on the actually measured values. It is possible to provide a nonvolatile semiconductor memory device which suppresses variations and has uniform writing or erasing characteristics.

(5) The write / erase switching unit includes a data write voltage and an erase voltage at the time of the operation test as voltages for writing and erasing data with respect to the nonvolatile semiconductor memory cell. At least a voltage higher than the data write voltage and the erase voltage at the time of operation and a voltage lower than the data write voltage and the erase voltage at the time of the operation test.

In this configuration, the data write and erase voltages during the operation test and the data write voltage during the operation test are used as voltages for writing and erasing data in the nonvolatile semiconductor memory cell. And a voltage higher than the erase voltage, and a voltage lower than the data write voltage and the erase voltage during the operation test,
The nonvolatile semiconductor memory device has at least a switchable write / erase switching unit. Therefore, when switching to a voltage higher than the data write voltage and the erase voltage at the time of the operation test, the stress applied to the non-volatile semiconductor memory increases, and the data retention period after rewrite is shortened. Rewriting is frequently performed, and the interval at which data rewriting is repeatedly performed becomes short. In this case, the data retention period after rewriting is inevitably shortened, and no problem occurs. Further, when the voltage is switched to a voltage lower than the data write voltage and the erase voltage at the time of the operation test, the stress applied to the nonvolatile semiconductor memory can be reduced, and the data retention period after rewrite can be extended.

(6) The user writes, in response to an external command, a normal mode in which the write / erase speed is a predetermined speed, a high-speed mode in which data is written / erased faster than the normal mode, or a write in the normal mode and the high-speed mode It is characterized in that one of the high reliability modes having a long data retention time can be selected.

In this configuration, when the nonvolatile semiconductor memory device is used, a normal mode in which the write / erase speed is a predetermined speed, a high-speed mode in which data is written / erased faster than the normal mode, or a normal mode The user can select a high reliability mode having a longer data retention time than the high speed mode by an external command. Therefore, the user can use the normal mode, the high-speed mode, and the high-reliability mode using only the nonvolatile semiconductor memory device of the present invention without preparing a plurality of nonvolatile semiconductor memory devices according to the application. Becomes

[0025]

FIG. 2 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. The nonvolatile semiconductor memory device 45 includes a plurality of address pins 21, a plurality of data pins 29, and a circuit power supply pin 4.
2. Write / erase power supply pin 43 and ground pin 4
4 is provided outside. In FIG. 2, a plurality of address pins 21 and a plurality of data pins 29 are collectively displayed to simplify the description. The nonvolatile semiconductor memory device 45 includes an input buffer 22, an address latch 23, a column decoder 24, a row decoder 25, an output buffer 26, an output MUX 27, a sense circuit 28, an input buffer 30, a status register 31, and a device code ID register 32. , A column gate 33, a memory cell 34 which is a nonvolatile semiconductor memory cell, a command state machine 35, an interface register 36,
A write state machine 37 as an erase control unit, a microcode storage 38 as a microcode storage unit, and the test information storage memory 3 as a write / erase voltage storage unit
9. A write / erase high voltage booster circuit 40 as a high voltage power supply section and a drain / source voltage setting circuit 41 as a write / erase voltage switching section are provided therein.

In the nonvolatile semiconductor memory device 45, an address signal input by a user from a plurality of address pins 21 for inputting an address is latched by an address latch 23 via an input buffer 22. The output of the address latch 23 is decoded by the row decoder 25 and the column decoder 24, and selects one of a plurality of rows and one of the plurality of columns.

The memory cell 34 has a plurality of blocks, and each block is constituted by a plurality of memory cells as shown in FIG. The data read from the memory cell 34 is input to the sense circuit 28 via the column gate 33, passes through the output MUX 27 after making a “0” or “1” determination of the data. Output MUX27
The data that has passed through is impedance-converted by the output buffer 26 and output to the data pin 29.

In the status register 31, an execution result of the write state machine 37 when writing / erasing is performed on the memory cell 34 is recorded via the command state machine 35. A device code is recorded in the device code ID register 32. A command input from the external data pin 29 via the input buffer 30 is controlled by the command state machine 35, and the output of the sense circuit 28 and the status Register 31
And the data of the device ID register 32 are switched by the output MAX27.

The data in the nonvolatile semiconductor memory cell 34 is rewritten by a command and data externally provided by the user. Commands and data provided from the data pins 29 are provided to the command state machine 35 via the input buffer 30. The given command is decoded in the command state machine 35, and it is identified whether the command is a write command, an erase command or a read command.
When the given command is a write or erase command, control of data input at the same time as the command is transferred to the write state machine 37.

The write state machine 37 controls each unit according to a programming or erasing algorithm recorded in the microcode storage 38 in advance. That is, a high voltage necessary for writing / erasing is generated in the high voltage boosting circuit 40 for writing / erasing. Further, the write status machine 37 operates the drain / source voltage setting circuit 41 for setting the source voltage and the drain voltage via the interface register 36 according to the contents of the test information storage memory 39. At the same time, according to the information in the test information storage memory 39, the drain / source voltage setting circuit 41 is controlled so as to control the write / erase pulse width applied to the memory cell. In the test information storage memory 39, a pulse width measured when writing or erasing is performed on a memory cell during an operation test is recorded.

The circuit power supply pin 42 is connected to a power supply of an internal reference voltage generating circuit or a logic circuit supplied from the outside. The write / erase power supply pin 43 is used as a power supply terminal of a write / erase high voltage booster circuit 40 for generating a voltage higher than the power supply voltage connected to the circuit power supply pin 42. Further, a ground potential is connected to the ground pin 44 as a reference potential for operation of the nonvolatile semiconductor memory device 45.

In the nonvolatile semiconductor memory device 45 according to the embodiment of the present invention, when data is written to the memory cell 34, the voltage applied to the drain from the drain / source voltage setting circuit 41 and the data in the memory cell 34 are erased. In this case, the voltage applied from the drain / source voltage setting circuit 41 to the source can be switched to a predetermined value and applied. As a result, the speed of writing and erasing data in the memory cell 34 can be switched to an arbitrary speed. FIG. 3 is a characteristic diagram showing a relationship between a source voltage of a memory cell transistor and an erasing time when erasing stored contents. As shown in FIG. 3, when the voltage applied to the source of the memory cell transistor is 4.7 V, the erase time of the stored contents is 1.37 seconds, but the applied voltage is 5.0 V
, The erase voltage is 1.10 seconds, and the applied voltage is 6.
In the case of 0V, the erase voltage is 0.86 seconds. Thus, not only the memory cell 34 but also a nonvolatile semiconductor memory (MOS transistor) generally having a floating gate has a characteristic that the higher the source voltage, the shorter the data erasing time. Therefore, for example, the case where the voltage applied to the source is 4.7 V is the high reliability mode, and the case where the applied voltage is 5.0 V is normal (operation test).
By setting the mode and the case where the applied voltage is 6.0 V as the high-speed mode, it is possible to use the nonvolatile semiconductor memory device 45 according to the use situation of the user.

Although the write time-drain voltage characteristic in the memory cell 34 at the time of writing is not shown, FIG.
Similarly to the erase-drain voltage characteristic shown in FIG.
The OS transistor has a characteristic that the higher the drain voltage, the shorter the data writing time. Therefore, even when erasing data in the memory cell 34, the nonvolatile semiconductor memory device 45 is used in accordance with the use situation of the user by setting the high reliability mode, the normal (operation test) mode, and the high-speed mode. be able to.

Next, another feature of the nonvolatile semiconductor memory device of the present invention will be described. Normally, the nonvolatile semiconductor memory device performs a write or erase operation at the time of an operation test before shipment from a factory. However, the nonvolatile semiconductor memory device 45 according to the embodiment of the present invention performs the write or erase pulse count at the time of the test. And the measurement of the optimum values of the drain voltage and the source voltage within a range that does not apply excessive stress to the memory cell. Then, each measured value is
The test information is stored in the test information storage memory 39.

FIG. 4 is a flowchart for explaining an operation test of the nonvolatile semiconductor memory device according to the embodiment of the present invention. As shown in FIG. 4, before shipment of the nonvolatile semiconductor memory device from the factory, contact tests (step 101) and DC tests (step 1) are performed as operation tests.
02), logic function test (step 10)
3), data write test of memory cells (step 1)
04), data erase test of memory cells (step 10)
6) and other tests (step 108).
Each test is performed in the order described above. If each test is passed, the next test is further performed. If the other tests finally passed in step 108 are passed, the product is shipped as a non-defective product. On the other hand, if any of the tests fail, the product becomes a failure and is not shipped.

If the data write test of the memory cell in step 104 is passed, the write voltage value for writing data to the memory cell and the number of write pulses for writing data to the memory cell are equal to the test information for each block. Recorded in the storage memory 39 (step 1
05). Then, step 106 is executed.

If the data erase test of the memory cell is passed in step 106, the erase voltage value for erasing the data of the memory cell and the number of erase pulses for erasing the data in the memory cell are the test information storage memory. 39 is recorded (step 107). Then, step 108 is executed.

As described above, the test information storage memory 39
Since the voltage value and the pulse width of the write pulse and the voltage value and the pulse width of the erase pulse of the nonvolatile semiconductor memory cell measured during the operation test are recorded, the write state for controlling the write and erase algorithms is recorded. The machine accesses the test information storage memory that stores the test data of each nonvolatile semiconductor memory, and uses that data to vary the pulse width or erase pulse width when writing to memory cells, and to set the optimum settings Therefore, the operation can be completed by one pulse application and verification. Therefore, it is possible to minimize the circuit overhead time related to the mode switching between writing or erasing and verifying, and to shorten the writing or erasing time.

Further, in the nonvolatile semiconductor memory device of the present invention, even if the characteristics of individual nonvolatile semiconductor memories vary due to process dispersion, the voltage or pulse width for writing or erasing can be arbitrarily determined based on actually measured values. The value can be corrected. That is, based on the data of the voltage value and pulse width of the write pulse and the voltage value and pulse width of the erase pulse of the nonvolatile semiconductor memory cell measured during the operation test stored in the test information storage memory 39, the drain-source voltage is determined. The write state machine 3 outputs a corrected write pulse or erase pulse from the setting circuit 41.
7 is controlled. As a result, it is possible to provide a nonvolatile semiconductor memory device which suppresses variation in characteristics as a product and has uniform writing or erasing characteristics.

In the user mode, which is the normal use state of the nonvolatile semiconductor memory device 45, when the three modes of the high reliability mode, the normal (operation test) mode, and the high speed mode are set as described above, When making a selection,
Write, erase and read commands are sent to data pin 2
Give from 9. At this time, the data to be written and the mode data of the high-speed mode, the normal mode, or the high-reliability mode are input from the data pin 29 following the write and erase commands. With this mode data, the write state machine 37 automatically sets the drain voltage at the time of writing or the source voltage at the time of erasing.

With this function, in the high-speed mode, the stress applied to the memory cell 34 is increased, and the data retention period after rewriting is shortened. On the other hand, in the high reliability mode,
Although the writing / erasing time is longer than in the high-speed mode and the normal mode, the stress applied to the memory cell 34 can be reduced, and the data retention period after rewriting can be extended.

When the high-speed writing / high-speed erasing mode is used, rewriting is frequently performed in an actual application, and the interval at which data rewriting is repeatedly performed becomes short. Therefore, in this case, no problem occurs because the data retention period after rewriting is inevitably shortened. On the other hand, when the contents of the memory cells are not frequently rewritten, data retention characteristics are required, and this can be realized by performing writing / erasing at a low speed.

Further, by repeating the writing / erasing a plurality of times, the writing or erasing characteristics are changed, and sometimes the pulse width cannot be covered by the initially measured pulse width. In this case, the light state machine 37
Can be controlled so as to compensate for the insufficient pulse by separately applying the insufficient pulse from the drain / source voltage setting circuit 41 to the memory cell 34 via the interface register 36. Hereinafter, description will be made with reference to FIGS. FIG. 5 is a flowchart for explaining a conventional data write and erase operation in a nonvolatile semiconductor memory device. FIG.
9 is a flowchart for explaining a writing process. FIG. 7 is a flowchart for explaining the erasing process.

As shown in FIG. 5, the control unit of the nonvolatile semiconductor memory device determines whether the user has input a data write command from outside (step 201).
When the user inputs a write command from outside, the control unit of the nonvolatile semiconductor memory device performs a data write process (step 211). On the other hand, if there is no input of the write command in step 201, the control unit determines whether or not the user has input a data erase command from outside (step 202). When the user inputs an erasing command from the outside, the control unit of the nonvolatile semiconductor memory device performs a data erasing process (step 212).

The data write processing to the memory cell 34 is performed as follows. As shown in FIG. 6, in the write processing, the write state machine 37 first reads the measured value during the operation test stored in the test information storage memory 39 (step 221), and the memory cell 34 into which data is written. The address of the memory cell transistor is set (step 222). Further, the write state machine 37 includes a high voltage step-up voltage circuit 40 for writing / erasing in the drain / source voltage setting circuit 41.
Is set up so as to apply a write pulse having a predetermined voltage value and pulse width based on the measured value at the time of the operation test read from the test information storage memory 39 to the memory cell 34 (step 223). Then, a write pulse is applied from the drain / source voltage setting circuit 41 to the memory cell 34 (step 22).
4). When the application of the predetermined write pulse is completed, the application of the write pulse to the drain / source voltage setting circuit 41 is stopped (step 225).

Next, the write state machine 37 sets the drain / source voltage setting circuit 41 to apply a predetermined verify voltage to the memory cell 34 (step 226). Verify is performed to confirm (Step 227).
If the writing has not been successfully performed, the write state machine 37 stops the output of the verify voltage (step 231), and sends a preset write pulse having a rewrite voltage value and a pulse width to the memory cell. 3
4 (step 232). Then, a write pulse is applied from the drain / source voltage setting circuit 41 to the memory cell 34 (step 233). When the application of the write pulse is completed, the application of the write pulse to the drain / source voltage setting circuit 41 is stopped (step 225). As described above, the writing and the verifying are repeatedly performed while sequentially changing the writing voltage until the writing of the memory cell 34 becomes good.

On the other hand, if the writing of the memory cell 34 is good in step 227, the write state machine 37 stops outputting the verify voltage (step 228), and ends the write processing.

The data erasing process for the memory cell 34 is performed as follows. As shown in FIG. 7, in the erasing process, the write state machine 37 first
The measured value during the operation test stored in the test information storage memory 39 is read (step 241), and the address of the block of the memory cell 34 from which data is to be erased is set (step 242). In addition, the light state machine 37
Is written to the drain / source voltage setting circuit 41.
The voltage supplied from the high voltage boosting voltage circuit for erasing 40 is
The memory cell 34 is set up so that an erase pulse having a predetermined voltage value and a pulse width based on the measurement value at the time of the operation test read from the test information storage memory 39 is applied to the memory cell 34 (step 243). Then, an erase pulse is applied from the drain / source voltage setting circuit 41 to the memory cell 34 (step 244). When the application of the predetermined erase pulse is completed, the application of the erase pulse to the drain / source voltage setting circuit 41 is stopped (step 245).

Next, the write state machine 37 sets the drain / source voltage setting circuit 41 so as to apply a predetermined verify voltage to the memory cell 34 (step 246). Verification is performed to confirm the operation (step 247). If the erasure has not been successfully performed, the write state machine 37 stops the output of the verify voltage (step 251), and sends a preset erase value having a voltage value and a pulse width for re-erase to the memory cell. 34 to be applied (step 252). Then, an erase pulse is applied from the drain / source voltage setting circuit 41 to the memory cell 34 (step 253). When the application of the erase pulse is completed, the application of the erase pulse to the drain / source voltage setting circuit 41 is stopped (step 24).
5). As described above, the writing and the verifying are repeatedly performed while sequentially changing the writing voltage until the erasing of the memory cell 34 becomes satisfactory.

On the other hand, in step 247, if the erasure of the memory cell 34 is good, the write state machine 37
Stops the output of the verify voltage (step 24).
8), end the erasing process.

As described above, in the nonvolatile semiconductor memory device according to the embodiment of the present invention, the write state machine 37 for controlling the write and erase operations is optimally incorporated with the microcode for algorithmically controlling the write state machine 37. Since the drain voltage or the source voltage at the time of erasing is properly selected, if a mode is set at the same time when a user inputs a write or erase command, the "high-speed write or erase mode (high-speed mode)" It is possible to easily select the "factory default writing or erasing mode (normal mode)" or the "long-term data retention characteristic mode after rewriting (high reliability mode)".

[0052]

According to the present invention, the following effects can be obtained.

(1) A nonvolatile semiconductor memory device includes a nonvolatile semiconductor memory having a plurality of blocks each including a plurality of electrically rewritable and erasable memory cells, and information stored in the nonvolatile semiconductor memory. A high-voltage power supply for supplying a voltage for writing and erasing, a microcode storage for storing a microcode selectable by an external command, and information to the nonvolatile semiconductor memory according to the microcode selected by the external command. A write / erase control unit for controlling the writing and erasing operations, and a voltage applied from the high-voltage power supply unit to adjust the voltage as a voltage at which data can be written to the nonvolatile semiconductor memory and a voltage at which data can be erased. And a write / erase voltage switching unit capable of switching to a value. The higher the erase (source) voltage,
It has the property that data erasing time is shortened,
Since the data writing time is shortened as the writing (drain) voltage is increased, the writing / erasing time of the semiconductor memory can be controlled. Further, by setting a plurality of modes according to the voltage applied to the nonvolatile semiconductor memory, the nonvolatile semiconductor memory device can be used according to the application.

(2) Write test pass data of the write pulse voltage value and pulse width to the nonvolatile semiconductor memory at the time of the operation test stored in the write / erase voltage storage section, and the erase pulse voltage value and pulse width Based on the erasure test pass data, the voltage applied from the high-voltage power supply is adjusted to switch the voltage to any value as the voltage at which data can be written to the nonvolatile semiconductor memory and the voltage at which data can be erased. The writing and erasing characteristics of the non-volatile semiconductor memory fluctuate due to such variations.However, during the operation test, the optimum writing or erasing characteristics according to the memory cell characteristics of each device are measured,
By storing the data in the write / erase voltage storage unit, a normal write / erase pulse is applied, and then a write / erase verify is performed. Although application and verification are required, the write / erase control unit that controls the write and erase algorithms accesses the write / erase voltage storage unit that stores the test data for each nonvolatile semiconductor memory, and stores the data. Can be used to change the write pulse width or erase pulse width to the nonvolatile semiconductor memory and make the optimum setting, so that the operation can be completed by one pulse application and verification. Further, the circuit overhead time related to the mode switching between the writing or erasing and the verify can be minimized, so that the writing and erasing time can be shortened.

(3) The write pulse voltage value and write pulse width, and the erase pulse voltage value and pulse width to the nonvolatile semiconductor memory cell stored in the write / erase voltage storage section can be switched to arbitrary values. Since the nonvolatile semiconductor memory device includes the write / erase voltage switching unit which is a variable write / erase voltage or a write / erase voltage based on the actually measured value even if the characteristics of individual nonvolatile semiconductor memories vary due to process dispersion. The pulse width can be corrected to any value, suppressing characteristic variations as a product,
A nonvolatile semiconductor memory device having uniform writing or erasing characteristics can be provided.

(4) As a voltage for writing and erasing data with respect to the nonvolatile semiconductor memory cell,
Data write voltage and erase voltage during the operation test,
A non-volatile semiconductor device comprising a write / erase switching unit which is at least switchable to a voltage higher than a data write voltage and an erase voltage during the operation test, and a voltage lower than a data write voltage and an erase voltage during the operation test. Since the memory device is provided, when the voltage is switched to a voltage higher than the data writing voltage and the erasing voltage in the operation test, the stress applied to the nonvolatile semiconductor memory increases, and the data retention period after rewriting becomes shorter. However, in an actual application, rewriting is performed frequently, and the interval for repeatedly executing data rewriting is shortened.In this case, the data retention period after rewriting is inevitably shortened, and no problem occurs. Data is available. Further, when the voltage is switched to a voltage lower than the data write voltage and the erase voltage during the operation test, stress applied to the nonvolatile semiconductor memory can be reduced, and the data retention period after rewrite can be extended.

(5) When using the nonvolatile semiconductor memory device, a normal mode in which the write / erase speed is a predetermined speed, a high-speed mode in which data is written / erased faster than the normal mode, or a normal mode The user can select a high-reliability mode in which the written data retention time is longer than that in the high-speed mode by an external command, so that the user does not need to prepare a plurality of nonvolatile semiconductor memory devices according to the intended use. The normal mode, high-speed mode, and high-reliability mode can be used by using only the nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of one memory cell in a NOR flash memory.

FIG. 2 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a characteristic diagram showing a relationship between a source voltage of a memory cell transistor and an erasing time when erasing stored contents.

FIG. 4 is a flowchart for explaining an operation test of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a conventional data write and erase operation in a nonvolatile semiconductor memory device.

FIG. 6 is a flowchart illustrating a writing process.

FIG. 7 is a flowchart illustrating an erasing process.

[Explanation of symbols]

 34-memory cell 37-write state machine 38-microcode storage 39-test information storage memory 41-drain / source voltage setting circuit 45-nonvolatile semiconductor storage device

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G01R 31/28 B V

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory having a plurality of blocks constituted by a plurality of electrically rewritable and erasable memory cells, and supplying a voltage for writing and erasing information to the nonvolatile semiconductor memory. A high-voltage power supply unit, a microcode storage unit that stores microcodes that can be selected by an external command, and controls the operation of writing and erasing information to and from the nonvolatile semiconductor memory according to the microcode selected by the external command. And a write / erase control unit for controlling the voltage applied from the high-voltage power supply unit so that the voltage can be arbitrarily determined as a voltage at which data can be written to the nonvolatile semiconductor memory and a voltage at which data can be erased. Characterized by having a write / erase voltage switching unit capable of switching to different values Conductor memory device. 2. A write / erase memory for storing a write test pass data of a write pulse voltage value and a pulse width and an erase pulse voltage value and a pulse width erase test pass data to the nonvolatile semiconductor memory during an operation test. A voltage storage unit, wherein the write / erase voltage switching unit adjusts a voltage applied from the high-voltage power supply unit based on the data stored in the write / erase voltage storage unit, and stores the data in the nonvolatile semiconductor memory. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the writable voltage and the data erasable voltage are switched to arbitrary values. 3. The write / erase voltage switching unit includes: a write pulse voltage value and a write pulse width for the nonvolatile semiconductor memory cell stored in the write / erase voltage storage unit; and an erase pulse voltage value and a pulse. The width can be switched to any value.
Or the nonvolatile semiconductor memory device according to 2. 4. The write / erase switching unit includes: a data write voltage and an erase voltage during the operation test; and a data write and erase voltage during the operation test, when writing and erasing data with respect to the nonvolatile semiconductor memory cell. 4. The device according to claim 1, wherein the voltage is at least switchable between a voltage higher than the data write voltage and the erase voltage and a voltage lower than the data write voltage and the erase voltage during the operation test. 5. 3. The nonvolatile semiconductor memory device according to 1. 5. A normal mode in which a user performs a write / erase speed at a predetermined speed by an external command, a high-speed mode in which data is written / erased faster than the normal mode,
5. The non-volatile semiconductor memory device according to claim 1, wherein one of a high reliability mode and a high reliability mode having a longer data retention time than the normal mode and the high speed mode can be selected.