JP2007200553A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out erasure at a high speed by increasing a level of convergence in the erasing operation of a nonvolatile semiconductor memory device. <P>SOLUTION: A word latch circuit is provided for each word line, and threshold management is executed for each word line in a selected block. The latch circuit is shared by the plurality of word lines to reduce an occupied area. A write-back voltage is set for each completed nonvolatile memory, stored in the boot area of the nonvolatile memory, and recognized again for each power-ON. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an applied voltage control method in an erase operation of a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device to which the applied voltage control method is applied.

  The floating gate electrode type nonvolatile memory element (hereinafter referred to as “cell”) stores information based on the difference in cell characteristics depending on the number of electrons accumulated in the floating gate electrode, that is, the magnitude of the cell threshold voltage. Hereinafter, the process for increasing the threshold value is defined as “write”, and the process for decreasing the threshold value to converge to a desired value is defined as “erase”. Of course, the process of raising the threshold value can be defined as “erasing”, and the process of lowering the threshold value and converging to a desired value can be defined as “writing”.

FIG. 2 shows a cell threshold distribution of a general nonvolatile semiconductor memory device in which an array is composed of a plurality of cells. The write level is defined by the write lower limit value V _pmin , and the threshold distribution is A. In the erasing process, a predetermined voltage is applied to the cell group in the distribution A state to lower the threshold value. Normally, there are variations in the erasing characteristics, so that a threshold distribution with a wide skirt as in distribution B can be obtained by simply performing a process of lowering the threshold. A cell group (shaded area) whose threshold value is _{equal to} or lower than the erase lower limit value V _emin (over-erased level) becomes a source of leakage current and inhibits correct information reading. In order to prevent this, it is necessary to write back the cells at the overerase level and adjust the cell to the desired erase level distribution C (erase lower limit value V _emin to erase upper limit value V _emax ).

  Conventionally, as a method for lowering a threshold value, a method of managing a plurality of word lines collectively (hereinafter referred to as “block processing”) and a method of managing a cell threshold value in units of word lines (hereinafter referred to as “block processing”). "Sector processing"). In the block process, a block including a plurality of word lines is selected based on information stored in the register. For example, the well potential is used as a block selection signal, and a negative voltage is applied to all word lines in the block. Charges are released using an electric field generated by a negative voltage applied to the word line and a positive potential applied to the well. Subsequently, the cell threshold value is verified, and if a cell whose threshold value does not fall below the reference is detected, a negative voltage is applied again to all the word lines in the block. This process is repeated, and when the threshold values of all the cells in the block become below the reference, the process moves to the next block and the erase process is performed. Since block processing can process a large number of cells at once, the processing time for lowering the threshold is short.

  Sector processing is managed for each word line. After applying a negative voltage to a certain word line, the threshold value of a cell connected to that word line is verified. When a cell whose threshold value is not below the reference is detected, a negative voltage is applied again to the word line. When the threshold values of all the cells connected to the word line become below the reference value, the process proceeds to the next word line. In this method, the negative voltage that lowers the threshold is uniformly applied to the number of cells connected to one word line at most. Since the statistical parameter is reduced, the threshold distribution after processing can be narrower than that of block erasure. On the other hand, the processing time must be longer than the block processing.

  Also, a process for returning the threshold value that has decreased too much after the erasing process is performed. This process is called “write-back”. Regardless of whether the above-described block processing or sector processing is used, it is inevitable that a certain number of cells become over-erased. Therefore, it is necessary to write back the cells at the overerase level. This is done using weak writing. Similar to the variation in the erase characteristics, there is also a variation in the write characteristics. Therefore, in order to converge the threshold value to the erase level of FIG. 2, the threshold value must be controlled particularly precisely.

As a voltage application method for performing precise writing, there is known a method of sequentially increasing an applied pulse voltage applied to the drain and gate of a cell. An example of this is writing using hot electron injection. A cell having a high writing speed is converged with good controllability by applying an initial low voltage. A cell having a low writing speed at a low voltage converges with a high voltage in the latter half with good controllability in a short time. Such a method of applying the write voltage is disclosed in Patent Document 1 and Patent Document 2.
JP-A-8-96591 JP-A-10-228784

  Since the block process has a large number of target cells, the threshold distribution after the process becomes wider and the number of cells at the overerased level also increases. Therefore, there is a drawback that the processing time for writing back increases. The sector processing has a drawback that the processing for applying the voltage for lowering the threshold must be performed individually for the number of word lines, and the processing time for the voltage application increases. In order to shorten the entire erasure processing time, it is necessary to simultaneously shorten both the processing time for lowering the threshold and the processing for writing back. However, in the conventional block processing and sector processing, it is difficult in principle to reduce such simultaneous time.

  In addition, it is necessary to write with good convergence in writing back. Therefore, in the present invention, the voltage of the write voltage pulse is sequentially increased at the time of writing back. For this purpose, it is desirable that the minimum value, maximum value, voltage increment, and pulse time of the applied voltage are set appropriately. When the stress is too strong, such as when the start voltage is too high, cells with a fast write-back speed exceed the erase level upper limit value. If the starting voltage is too low or the maximum applied voltage is too low, the write-back speed is slowed, resulting in an increase in processing time. An appropriate method for setting the voltage pulse condition to be applied is also an important issue.

  In the selected block, the word line whose threshold value is in an appropriate range during the erasing process is excluded from the target of the additional erasing process. Selection / non-selection of the word line in the additional erasing process is performed by controlling a latch circuit attached to the word line based on the processing end information stored in the register. By sharing the latch circuit with other word lines that do not perform processing at the same time, an increase in area is also prevented.

  In addition, a voltage that gradually increases during writing back is applied. The applied voltage can be set for its initial value, final value, voltage increment, and pulse width, and is selected in accordance with the characteristics of each completed nonvolatile memory. The selected condition is stored in the chip as nonvolatile information, and is read and used every time the power is turned on.

  In erasing the nonvolatile memory, it is possible to achieve both a short processing time that is a feature of block processing and a small threshold variation that is a feature of sector processing. Therefore, the speed of the entire erase process can be improved.

  FIG. 3 shows the configuration of the nonvolatile semiconductor memory device (memory module MM). The memory array MARY has memory cells arranged in a matrix. Each memory cell can be electrically raised / lowered. In addition, the memory module MM includes a row address buffer XADB, a row address decoder XDCR, a data latch circuit DL, a sense amplifier circuit SA, a column gate array circuit YG-Gate, YW-Gate, YT-Gate, a column address buffer YADB, and a column address. The decoder YDCR, block selection control circuit BSLC, input buffer circuit DIB, output buffer circuit DOB, multiplexer circuit MP, mode control circuit MC, control signal buffer circuit CSB, built-in power supply circuit VS, and the like.

  Although not particularly limited, the control signal buffer circuit CSB receives a chip enable signal CEb, an output enable signal OEb, a write enable signal WEb, a serial clock signal SC, and the like, and performs internal control according to these signals. Generate a timing signal for the signal. Also, a ready / busy signal is output from the mode control circuit MC to the external terminal R / Bb.

  In the built-in power supply circuit VS, although not particularly limited, a power supply voltage Vcc is input from the outside, and a voltage necessary for writing, erasing, and reading is generated and supplied.

  An address signal formed through a row (column) address buffer XADB (YADB) that receives a row (column) address signal AX (AY) supplied from an external terminal is supplied to a row (column) address decoder XDCR (YDCR).

  FIG. 1 is a block diagram showing the word line latch system of the present invention. Memory array MARY has wells WELL01-n that are electrically isolated from each other. The well is divided as a region including a plurality of word lines W01-m. Word lines W01-m are driven by word drivers WD01-m, respectively. Each well is selected by a block selection signal BSL from the block selection control circuit BSLC.

  Row address decoder XDCR includes an erase unit selection decoder DECX1, a word line selection decoder DECX2, and latches LTC01 to 32. In this example, since 32 word lines are used as one erase unit, the output of the erase unit selection decoder DECX1 selects 32 word lines at once, and further, individual word lines are selected as word line selection decoders. The configuration is selectable by DECX2. Further, registers RES01 to RES32 corresponding to the latches LTC1 to 32 are provided in the controller or CPU for controlling the erasure of the memory array.

  A group of cells existing in the region defined by the well WELL01 forms one block. In this embodiment, the word lines W01 to 32 are the first erase unit. It is assumed that the block selection signal BSL is positive potential / 0 V and the block is selected / unselected. An example of voltage application at the time of erasing is shown in FIG. Charge discharge from the cell to the substrate is performed using an electric field formed by a negative voltage (−11 V) applied to the word line and a positive voltage (10 V) applied to the well.

  As a circuit configuration feature of the present invention, the latch circuits LTC01 to 32 are shared with word lines other than the plurality of erase units W01 to W32, that is, the latch circuits are shared by a plurality of word lines included in different erase units. . FIG. 1 shows that the latch LTC1 is shared by the word line W1 and the word line W33 included in different erase units. The increase in area due to the latch circuit LTC is approximately the product of the area per latch circuit and the number thereof. In this embodiment, since the latch circuit is shared by a plurality of erase units, there is an effect of suppressing an increase in the chip area of the nonvolatile memory due to the installation of the latch circuit.

  In FIG. 1, 32 word lines are used as an erasing unit, but the number is not limited to this. Further, although one block is configured to include a plurality of erase units, it is also possible for one block to include one erase unit. In the case of such a configuration, it is possible to eliminate the influence of disturbance caused by applying a positive voltage for erasing to the well. On the other hand, in this configuration, an increase in the area of the memory array caused by the well division can be suppressed.

  The cell erase operation will be described with reference to the flowchart of FIG. First, all the registers RES01 to 32 are set to “0” (S51). A block selection signal positive potential, for example, 10 V is supplied to the well WELL01 of the block including the word line to be erased through the BSL. Subsequently, the same negative voltage pulse is applied to all 32 word lines included in the erase unit (S52). After applying the voltage pulse, the cell threshold is verified sequentially from the word line W01 (S53). If a cell that does not reach the reference threshold value is detected, the process moves to the next word line (S54) and the verification is continued. If the threshold value of the cell has reached the reference threshold value, the process proceeds to the next memory cell in the same word line (S55), and the verification is continued. If the threshold values of all the cells in the same word line have reached the reference threshold value, the processing completion information “1” is stored in the corresponding register (S56). After the verification is completed for all 32 word lines in the erase unit, an additional erase process is performed on the word line in which “0” is stored in the corresponding register. If all the values stored in the registers RES01 to RES32 are "1", the same erase process is performed for the next erase unit (S57).

  Based on the information stored in the register RES, the latches LTC01 to LTC32 are controlled so that a minus 10V pulse is applied to a word line that requires additional erasing processing, and 0V is applied to an unnecessary word line, or a floating potential state is set. To do. The cell threshold is verified for the word line on which the additional processing has been performed. If the processing is not completed, “0” is stored again in the register corresponding to the word line address, and the processing is completed. If so, replace it with “1”. By repeating these procedures, the number of word lines to be subjected to additional erasure processing can be sequentially reduced, and the time required for verification can be shortened as compared with the conventional block processing. Further, since the minimum unit to which the voltage for lowering the threshold is applied is one word line, the threshold distribution after processing is equivalent to that in the sector processing. Therefore, it is possible to reduce the number of cells to be overerased, which is the target of the write-back process, as much as the sector process, and to shorten the write-back process time.

  FIG. 6 is a flowchart showing the write-back voltage selection method of the present invention. A plurality of cells to be used as voltage setting test targets are determined in advance from the completed nonvolatile memory (S61). The lowest write voltage expected from the manufacturing characteristic variation is set as the initial value of the voltage used in the test write. First, all the cells to be tested are written (S62). Thereafter, all the threshold values of the test target cell are read (S63). Two methods, Case A and Case B, will be described as methods for selecting the voltage according to the read value.

  In Case A, if the median value of the detected threshold values does not satisfy the reference threshold value (for example, the write lower limit value), the threshold value of the test cell is once lowered (S64). The write voltage is increased by ΔV from the initial applied voltage (S65), the write test is performed again, and the threshold value is verified. This process is repeated, and when the median cell threshold value after writing reaches the reference, the last applied voltage is determined for each chip as the writing voltage (S66). As the write-back voltage, a value associated with the write voltage selected here is selected and determined for each chip (S67).

  Case B does not repeat the process as in Case A. The applied voltage is determined for each chip based on the correspondence table of the threshold value after writing, the writing voltage, and the writing back voltage, which is created based on the actual writing data (S68). In both cases A and B, an appropriate write voltage and an appropriate write-back voltage are determined for each chip based on the characteristics of each completed nonvolatile memory.

  Here, the write-back voltage is determined for each chip from the write characteristics of the test cell. However, the write-back voltage may be determined by directly evaluating the write-back characteristics. Further, the step voltage that is sequentially raised may be made variable, and the voltage may be determined for each chip. In addition, even if the originally defined “write” and “erase” are interchanged, that is, the process for lowering the threshold value can be applied as “write” and the process for raising the threshold can be applied as “erase”.

  A method for reproducing an appropriate voltage pulse selected in FIG. 6 will be described with reference to FIG. A plurality of voltage pulse patterns such as pulses having different voltage increments ΔV and pulses having different pulse widths are prepared in advance. Assume that a suitable voltage pulse is shown in FIG. In this example, a pattern is selected from 64 types of patterns, the initial voltage value of the pulse, the increment ΔV, the pulse width, the final ultimate voltage, etc. are specified, and the voltage application conditions according to the individual product chip characteristics are reproduced. To do. Four types of patterns to be selected are shown in FIGS. 7 (a) to 7 (d). FIG. 7A shows a pulse voltage having a pulse width T001. FIG. 7A is selected as the initial pulse of the write-back voltage, and VG0001 is designated as the applied voltage initial value. The voltage increment is ΔV. The voltage applied subsequent to FIG. 7A is applied from the applied voltage VG00110 using the pulse having the pulse width T011 shown in FIG. 7B. The voltage increment is ΔV. The voltage applied subsequent to FIG. 7B is applied at the applied voltage VG01001 using the pulse of the unit time T110 of FIG. 7C. The voltage increment of this pulse is zero and is applied a specified number of times. The voltage applied subsequent to FIG. 7C is applied at the applied voltage VG01010 using the pulse of the unit time T110 of FIG. 7D. Thereafter, the pulse of FIG. 7D is applied until the writing back is completed.

  The voltage pulse pattern prepared in advance is stored as designation information in the voltage pulse control register as shown in FIG. In the example of FIG. 7 (e), 5 bits are assigned to the voltage value and 3 bits are assigned to the pulse width, and the total patterns are 64 types. Among the registers R01 to R64, the registers specifying the four patterns in FIGS. 7A to 7D are R02, R04, R21, and R63. The address of the register indicating this pulse designation condition is stored in a part of each nonvolatile memory array MM. As an area used for storing information, an area (boot area) that is always read when the power is turned on is selected. The operating voltage selected for each chip is selected from the voltage designation information stored in the register according to the register address read from the boot area each time the power is turned on.

  By selecting the applied voltage at the time of writing back according to the characteristics of each completed nonvolatile memory, it is possible to perform an appropriate erasing process. For example, even if the cell gate length is designed to be 0.3 μm, it is assumed that a non-volatile memory having an average value of the finished dimensions in the range of 0.28 μm to 0.32 μm is obtained. As a result, it is not uncommon for a difference of as much as 1 V to occur in the applied voltage that gives the same write-back speed, but even in such a case, the applied voltage can be selected for each product, I can do it. That is, even if there is processing variation, it can be provided as a product that functions normally. By storing appropriate voltage pulse information in the nonvolatile memory, the designation can be re-recognized when the power is turned on.

  The above method can be applied not only to write-back processing but also to writing. When the write application voltage is sequentially increased, the minimum and maximum values of the write voltage to be applied can be made variable, and the minimum, maximum value, and step voltage can be determined for each chip from the above test writing characteristics. The same applies to erasure.

  FIG. 8 shows an example of a semiconductor integrated circuit system in which a nonvolatile memory is mounted on the same substrate. The central processing unit CPU, the cache CM, the digital signal processor DSP, and the nonvolatile memory NVM are connected by a bus, and are configured as devices on the same chip CHIP51. The CHIP 51 is enclosed in one package PKG5. The NVM in such a semiconductor device is used, for example, for a purpose of storing a program. If the present invention is applied to this NVM, a semiconductor device with a short program update time, that is, a short information rewrite time can be realized.

  FIG. 9 shows an example of a semiconductor integrated circuit system including different chips CHIP61 and CHIP62 (NVM) and mounting both chips in the same package PKG6. The configuration is the same as that shown in FIG. 9, but the chip may be separated from this. Again, if the present invention is applied to the NVM, a semiconductor device with a short program update time, that is, a short information rewrite time can be realized. Although not shown, the CHIP 61 and CHIP 62 may be enclosed in separate packages. Even in this case, it will be easily understood that the present invention can be applied.

It is a block diagram of the non-volatile memory of this invention. It is a figure which shows the threshold value distribution in the "write" level of a non-volatile memory, and the "erasure" level. 1 is a block diagram of a nonvolatile semiconductor memory device. It is a figure which shows the voltage relationship applied at the time of erasure | elimination of a non-volatile memory. It is a flowchart of the process which lowers | hangs the threshold value of a non-volatile memory. 3 is a flowchart of a process for determining write and write-back voltages of the present invention. 7A is an example of a voltage pulse pattern applied at the time of writing back, FIG. 7B is an example of a voltage pulse pattern applied at the time of writing back, and FIG. 7C is an example applied at the time of writing back. FIG. 7D is an example of a voltage pulse pattern applied at the time of writing back, FIG. 7E is an example of contents of a register that controls the voltage pulse. 7 (f) is an example of a voltage pulse pattern applied at the time of writing back. It is a figure of the semiconductor integrated circuit system which mounted the non-volatile memory on the same board | substrate. It is a figure of the semiconductor integrated circuit system which mounted the non-volatile memory in the same package.

Explanation of symbols

  A: threshold distribution at write level, B: threshold distribution immediately after processing for lowering threshold, C: threshold distribution at appropriate erase level, DECX1: erase unit of nonvolatile memory array Decoder to be selected, DECX2... Decoder for selecting word lines of nonvolatile memory array, W01 to E33... Word lines, WD01 to WD33... Word driver circuit for driving word lines W01 to W33, WELL01. Wells including cells, BSL: power supply signal input terminals to the wells, LTC01 to LTC32, word latch circuits, RES01 to RES32, registers for storing word line erase information, CPU, central processing unit, CM, cache, DSP, digital Signal processor, NVM ... Non-volatile memory.

Claims (4)

A plurality of memory cells;
A plurality of word lines to which the plurality of memory cells are respectively connected;
Performing an erase operation for changing the threshold voltage of the memory cell from the first threshold voltage toward the second threshold voltage, and performing a write-back operation on the over-erased memory cell; A non-volatile semiconductor memory device in which a pulse increasing in sequence is applied at the time of writing back. In claim 1,
A nonvolatile semiconductor memory device capable of setting a minimum value, a maximum value, a voltage pulse width, and a voltage increment of an applied voltage applied at the time of writing back. In claim 2,
A nonvolatile semiconductor memory device that sets the characteristics of the applied voltage for each product. In claim 2,
A nonvolatile semiconductor memory device that stores information on the characteristics of the applied voltage in a boot area of the nonvolatile semiconductor memory device and reads and uses the information when the power is turned on.

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