JP2002185516A - Packet transmitter, packet receiver and packet communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet transmitter, a packet receiver and a packet communication system capable of improving a communication quality, by reducing a processing delay time of information requiring high real time properties and a fluctuation of the processing delay time. SOLUTION: The packet communication system selects and reads the packet having the highest priority each time the packet arrives irrespective of the set read priority of each packet; adds the information indicating the priority of the packet, the information indicating total packet length of the packet and dividing information of the packet; and transmits the packet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transmitting apparatus, a packet receiving apparatus, and a packet communication system, and more particularly, to a communication method which reduces processing delay time and fluctuation of processing delay time of information requiring high real-time performance. The present invention relates to a packet transmission device, a packet reception device, and a packet communication system that can improve quality.

[0002] The spread of the Internet, which has been made available to the general public around the world after the technology of the ARPA network, which was a U.S. military computer network, has recently become particularly widespread. Until telephones, which are the abutments of communication equipment, spread to 10% of homes, 7
It took more than 0 years, and it took 13 years for personal computers to spread to 10% of households. On the other hand, although personal computers have already spread to more than half of households, the Internet The fact that it took only five years to spread to homes demonstrates this.

[0003] In the Internet, communication is performed by transferring variable-length frames called packets using the Internet Protocol (Internet Protocol: usually abbreviated as "IP"). This communication is a method called “best effort” type, and the communication quality (Qo) means that a very long processing delay time may be required instead of accepting a communication request as much as possible.
S: Quality of Service is not guaranteed.

[0004] In recent years, real-time applications such as VoIP (Voiceover IP), which is voice communication using the Internet protocol, have been put into practical use. Sometimes it does n’t stop at voice communication,
Demand is growing.

However, as already experienced in voice communication via communication satellites, long transmission delays hinder natural conversation. Therefore, in order for the demand for communication of information having high real-time properties such as voice information to further increase on the Internet, a processing delay time for a packet of information having high real-time properties is short, and a packet having a small fluctuation of the processing delay time is required. Practical use of the transmitting device, the packet receiving device, and the packet communication system is an essential requirement.

[0006]

2. Description of the Related Art In response to the above-mentioned demand, Diff-serv, In
and a protocol such as t-serv, RSVP for performing communication to reserve the use band (R esouce R eser v a
As tion P rotocol) such protocols, the possible protocol ensuring fluctuation of processing delay time of a packet that is part of the communication quality and processing delay time has appeared.

However, the above protocol is based on OSI (Open S
It is a protocol of the network layer in the system interconnection (systems), and it is the lower layer physical layer and data link layer that actually perform the control for guaranteeing the communication quality.

At present, as an apparatus of a physical layer and a data link layer capable of guaranteeing communication quality, an ATM communication system (Asynchro) which performs communication using a fixed-length frame called a cell.
nousTransfer Mode: Translated as "asynchronous transfer mode". ) Is the main. In the ATM communication system, a variable length IP packet of 64 bytes to 1,500 bytes is divided.
8-byte payload and 5-byte OAM header (Oper
It is an abbreviation for ation, Administration and Maintenance.
Recently, there is a direction that it is an abbreviation of Operation And Maintenance. ) Are communicated using a 53-byte cell as a basic unit. Then, by controlling the priority using the OAM header, it is possible to guarantee the communication quality for a cell having a high priority.

[0009]

In the ATM communication system, a variable-length packet is divided into fixed-length packets and divided into short payloads, and a predetermined OAM header is added to each of the payloads to form a cell. Since the ratio of the total OAM header length to the total payload length increases, it is inevitable that the transfer efficiency decreases. For this reason, in order to suppress a decrease in transfer efficiency due to the ATM communication system, the IP packet remains a variable-length frame, and a variable-length processing is performed to suppress the processing delay time of the IP packet having a high real-time property and fluctuation of the processing delay time. There is a movement to prioritize and transfer IP packets.

However, in the method of transferring the IP packet with the priority given to the IP packet while keeping the variable-length frame, even if the packet has a low priority, once the transfer is started, the packet having a higher priority is transmitted. Even if it arrives, the packet is transferred according to the rule that the transfer of the high priority packet is kept waiting until the transfer is completed.
A problem arises in that packets with high priority are not necessarily transferred under advantageous conditions.

As described above, the packet length allowed for a variable length packet is 64 bytes to 1,500 bytes, and there is a very large difference. On the other hand, the packet length of a VoIP packet requiring high real-time property is as short as 100 to 200 bytes. Moreover, the band used is as narrow as 64 Kb / s at most. That is, in a plain language, VoIP packets have a small number of packets per unit time.

On the other hand, image transmission and FTP (File Transfer)
Protocol) for data transmission up to 1,500
Often, packets of bytes are transferred sequentially.

Therefore, VoI which has the highest real-time property
Even if the P packet is transferred preferentially, if a packet with a low priority and a long packet length starts to be transferred first, real-time transmission of a packet with a low priority and a long packet length is completed. Since a packet having high reliability is kept waiting for transfer, there arises a problem that the processing delay time becomes long and the fluctuation of the processing delay time becomes large.

FIG. 15 is a diagram showing a problem in the conventional packet communication.

In FIG. 15, a thick solid line rectangle is a packet having a high priority, and a thin solid line rectangle is a packet having a low priority. The former specifies an individual packet by adding a number to “H”. Each packet is specified by adding a number to “L”.

FIG. 15A shows a case where a fixed-length packet in which the length of all the packets is constant is shown in FIG.
(B) is a case of variable length packets that allow the packet length to be different, and shows a situation where the packet arrives at the buffer on the left side and a situation where the packet is output from the buffer and multiplexed on the right side. .

In FIG. 15A, a low-priority packet arrives at the buffer continuously after the first packet L1 arrives at time t0 until the last packet L8, and a high-priority packet arrives at the time t1 at time t1. H1 is at time t4
It is assumed that the packet H2 arrives at the buffer at time t7.

The packet L1 arriving at time t0 is immediately output from the buffer because no packet with a higher priority has arrived at that time.

At time t1, packets H1 and L
2 arrive at the same time, but the packet H1 with a higher priority is output first, and then the packet L2
Is output.

The packets L3 and L4 arriving after that are immediately output because no packets with high priority have arrived.

Thereafter, output from the buffer is performed in the same manner, and both packets are output from the buffer and multiplexed in the order shown in the diagram on the right side of FIG.

When the fixed packet length is set in accordance with the length of the high priority packet as shown in FIG. 15A, the high priority packets H1 to H3 are output with substantially no processing delay time. In addition, there is no fluctuation in the processing delay time. However, even with a fixed packet length,
If a packet length longer than the average length of a high priority packet is used as a standard, the processing delay time for a high priority packet becomes longer. In any case, the processing delay time for the packets L1 to L8 having low priority also fluctuates. However, since this is originally for information that is less affected by the length and fluctuation of the processing delay time, there is little problem.

On the other hand, FIG.
In (b), as for the packets with lower priority, the first packet L11 arrives at time t0, and the last packet L11 continues.
Assuming that the packet No. 12 arrives at the buffer at time t4, the packet having the higher priority is transmitted at time t4 in the same manner as in FIG.
It is assumed that the packet H1 arrives at the buffer 1, the packet H2 arrives at the time t4, and the packet H3 arrives at the buffer at the time t7.

The packet L11 arriving at the time t0 is immediately output from the buffer because no packet having a higher priority has arrived at that time.

At time t1, a packet H1 having a high priority
Arrives, but because the packet L1 is being output, the output is suspended, and the output is started from the buffer at time t4.

At time t4, a packet H2 having a high priority
And the low-priority packet L12 arrives at the same time, but since the packet H1 has begun to be output, the output is awaited. When the output of the packet H1 ends, the high-priority packet H2 is output first, and then Packet L1
2 is output.

At time t7, the packet H3 having a high priority
Arrives, but since the output of the packet L12 is being waited for because the output of the packet L12 is in progress, the output of the packet H3 is started when the output of the packet L12 ends.

As a result, even if the output priority is set to be high, a long processing delay time is required for the packets H1 to H3, and a large fluctuation occurs in the processing delay time, whereas the priority is low. Packet L11 and To L1
In the case of No. 2, there occurs a phenomenon that the average processing delay time is shorter and the fluctuation of the processing delay time is smaller.

That is, even if a packet is prioritized and transferred while maintaining the packet length of the variable length packet, a packet having a higher priority and a shorter packet length is transferred under disadvantageous conditions. Occurs. The unnaturalness of the voice communication caused by this can be avoided by absorbing the fluctuation of the processing delay time in the buffer provided on the receiving side, but it does not solve the problem that the processing delay time becomes long. .

In view of the above problems, the present invention reduces the processing delay time of a packet of information requiring high real-time performance and the fluctuation of the processing delay time to improve the communication quality for a packet requiring high real-time performance. An object of the present invention is to provide a packet communication system that can be improved.

[0031]

According to a first aspect of the present invention, a packet having the highest priority is selected and read each time a packet arrives, regardless of the transmission priority set for each packet. This is a packet transmission apparatus that adds information indicating the packet division status, information indicating the total packet length, and information indicating the length of a transmitted or waiting packet to be transmitted to a packet to be transmitted.

According to the first invention, the process of selecting the highest priority packet every time a packet arrives regardless of the transmission priority, adding information indicating the priority, and starting transmission. Is repeated. As a result, even when a packet having a long packet length is being transmitted, when a packet having a higher priority than the packet being transmitted arrives, the process shifts to transmission of a packet with a higher priority. Therefore, after the transmission of the highest-priority packet is completed in a specific time zone, the transmission shifts to the transmission of the next highest-priority packet, so that the transmission can be completed in order from the packet with the highest priority. And the fluctuation of the processing delay time and the processing delay time of a packet having a high packet delay can be reduced. Since information indicating the priority of the packet, information indicating the total packet length, and information indicating the length of the packet that has been transmitted or is waiting to be transmitted is transmitted, even when a packet of a specific priority is divided and transmitted. In the packet receiving apparatus, it is possible to confirm that the packets have the same priority and the same packet, and to correctly combine and restore the divided and transmitted packets.

According to a second aspect of the present invention, a packet having a specific priority is stored in a corresponding specific storage circuit in accordance with an analysis result of information added to a received packet, and the divided packets are combined. It is a packet receiving device.

According to the second aspect of the invention, information indicating the priority of the packet, information indicating the division status, information indicating the total packet length, and information indicating the length of the transmitted or waiting packet are added to the received packet. In this case, since the packets having the same priority and the same packet can be recognized and combined and restored, the packet arriving at the packet transmitting apparatus can be correctly restored in the packet receiving apparatus.

The third invention is a packet communication system in which the packet transmission device of the first invention is arranged on the transmission side and the packet of the second invention is arranged on the reception side.

According to the third aspect, in addition to the information indicating the priority of the packet, information indicating the division status, information indicating the total packet length, and information indicating the length of the transmitted or waiting packet to be transmitted are added. Therefore, it is possible to confirm that the packets are of the same priority and the same priority, and to correctly combine and restore the divided and transmitted packets.

According to a fourth aspect of the present invention, in the packet communication system according to the third aspect of the present invention, when all packets of a specific priority have been transmitted to the packet transmitting apparatus, the packet of the specific priority is deleted, and If a predetermined time elapses before transmitting all the packets of the specified priority, a configuration for retransmitting the packet of the specified priority is arranged, and all the packets of the specified priority are combined in the packet receiving device. This is a packet communication system in which, if the predetermined time elapses before the transmission, the packet of the specific priority is deleted to prepare for retransmission.

According to the fourth aspect, when all packets of a specific priority are transmitted to the packet transmitting apparatus, the packets of the specific priority are deleted, and before all the packets of the specific priority are transmitted. In the case where a predetermined time has elapsed, a configuration for retransmitting the packet of the specific priority is arranged, and the packet receiving apparatus is configured to retransmit the packet of the specific priority when all of the packets of the specific priority elapse before the predetermined time elapses. , A configuration in which the packet of the specific priority is erased and prepared for retransmission is arranged.
Therefore, when the processing delay time of a packet exceeds a predetermined time due to an accidental failure of the packet transmission device, the packet can be retransmitted, and the receiving side retransmits the same packet as the received partial packet. Since it is not necessary to store packets redundantly, the reliability of the packet communication system can be improved.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 13 is a diagram (1) for explaining the principle of the present invention. In the same case as FIG. The state of multiplexing in communication is shown for comparison.

That is, as for the packets of lower priority, the first packet L11 arrives at time t0, and the last packet L11 continues.
12 assuming that the packet arrives at the buffer at time t4, and the packets having the higher priority are assumed to arrive at the buffer at time t1, the packet H2 at time t4, and the packet H3 at time t7. I have.

The reading of the low priority packet L1 arriving at the time t0 is started immediately because the high priority packet has not arrived at that time.

When the high-priority packet H1 arrives at the time t1, the reading of the low-priority packet is stopped, the reading of the high-priority packet H1 is started, and the reading of the packet H1 is completed at the time t2. . The divided packet of the packet L11 read so far is represented by L11a.
And

At this time, the packet L11 having a low priority
Since no packet has arrived other than
11 is resumed.

At time t4, the packet H having the higher priority
2 arrives, the reading of the packet L11 is stopped again, and the process shifts to the reading of the packet H2. At the time t5, the reading of the packet H2 is completed. The divided packet of the packet L11 read so far is defined as L11b.

At time t5, the packet L11 having a lower priority
Therefore, the reading of the packet L11 is restarted, the output of the packet L11c is finished at time t6, and the reading of the packet L11 is completed.

At time t6, the packet L having a low priority has already been set.
Since packet 12 has arrived at the buffer and no other packet exists, reading of packet L12 is started.

At time t7, the packet H having the higher priority
3 arrives, the reading of the packet L12 is stopped, and the process proceeds to the reading of the packet H3. At the time t8, the reading of the packet H3 is completed. This completes the reading of all packets with a high priority. The divided packet of the packet L12 read so far is defined as L12a.

At time t8, the low priority packet L12
, The reading of the packet L12 is restarted, and the transfer is completed. Since the high priority packet does not arrive, the reading of the packet L12 is completed. The divided packet of the packet L12 read at the time t8 transition is represented by L12
b.

That is, each packet is multiplexed in the order shown by the arrow in FIG. 13 and output from the buffer.

As is apparent from this, since the packets H1, H2, and H3 with high priority do not wait for reading of the packet with low priority, the actual processing delay time is 0, and the processing delay is zero. There is no fluctuation of time. Moreover,
As can be easily understood from verification, the actual processing delay time of a high-priority packet is 0 regardless of the length of a low-priority packet, and there is no fluctuation in the processing delay time. . According to the conventional packet communication method described for comparison, even when a high-priority packet is read, a low-priority packet is read while waiting to be read, the processing delay time increases, and the processing delay time fluctuates. However, the communication quality is greatly improved.

Then, the packets are sorted and combined for each priority in the packet receiving device, and the packets arriving at the packet transmitting device are restored.

FIG. 14 is a diagram (part 2) for explaining the principle of the present invention. In the case where four classes of priorities are set,
At time t0, a packet 4 of priority 4 (lowest priority) (abbreviated as “PKT4” in the figure; hereinafter, the packet may be abbreviated as “PKT” in the figure) arrives, and time t2. In FIG. 3, the packet 3 having the priority 3 arrives, and the packet 1 having the priority 1 (the highest priority) arrives at the time t2.

In the case of FIG. 14, there are four priority classes.
In the case of FIG. 13, there are two priority classes, but the principle that the highest priority packet is read first when a new packet arrives or when the reading of a specific packet is completed is performed. Is the same.

Therefore, although a detailed description of the order of starting, stopping, and resuming reading is omitted, the state in which three packets are multiplexed is as shown in the middle diagram of FIG.
That is, the packet with the highest priority is read with substantially the processing delay time 0, and although the fluctuation of the processing delay time is not explicitly shown in FIG. 14, the fluctuation of the processing delay time for the packet with the highest priority is 0.

Then, in the packet receiving device, the packets are sorted for each priority and combined, and the packet arriving at the packet transmitting device is restored.

Now that the principle of the present invention has been described, the technology of the present invention will be described below with reference to more detailed drawings.

FIG. 1 shows the configuration of the packet transmitting apparatus according to the present invention.

In FIG. 1, 11, 11a and 11b
Is a transmission buffer for temporarily storing packets for each transmission priority, and these constitute a transmission buffer unit.

Reference numeral 21 denotes a buffer monitoring circuit for monitoring, for each transmission buffer, packets temporarily stored in the transmission buffer unit for each transmission priority based on the packet information supplied from the preceding stage. Reference numerals 22a and 22b denote buffer monitoring tables for storing information on packets for each transmission buffer, and these constitute a buffer monitoring unit.

A division management circuit 31 manages the division of the packets arriving at the transmission buffer 11, the transmission buffer 11a, and the transmission buffer 11b in cooperation with the buffer monitoring circuit 21, a timer 32 used by the division management circuit 31, 3
Reference numeral 3 denotes a division information table that stores information indicating the state of division of packets arriving at the transmission buffer 11, the transmission buffer 11a, and the transmission buffer 11b, and these constitute a division management unit.

A read control circuit 41 controls reading of packets temporarily stored in the transmission buffer 11, the transmission buffer 11a, and the transmission buffer 11b in accordance with an instruction from the division management circuit 31, and a read control circuit 42
A selector that selects and outputs the divided packets read from the transmission buffer 11, the transmission buffer 11a, and the transmission buffer 11b in accordance with the instruction from 1. The multiplexing unit is configured by these selectors.

Reference numeral 51 denotes a divided buffer for temporarily storing the divided packets output from the multiplexing unit, and 52 denotes a header for generating a header for managing the divided packets and a trailer for the divided packets in accordance with an instruction from the divided management circuit 31. The trailer generation circuit 53 is a header / trailer addition circuit that adds a header and a trailer to the divided packets stored in the divided buffer 51 in accordance with an instruction from the division management circuit 31, and these constitute a division unit.

Hereinafter, the functions of each part will be briefly described mainly with respect to information exchanged and stored by each part.

Each transmission buffer has a write enable signal (abbreviated as “write EN” in the figure; the enable signal is abbreviated as “EN” in the figure) and a write start address (in the figure) from the previous stage. "Write AD
D ". Hereinafter, the address is abbreviated as “ADD”. ), The packet to be transmitted is temporarily stored, and the packet stored by the read enable signal and the read address supplied from the read control circuit 41 is generally divided and output.

The buffer monitoring circuit 21 receives a write enable signal, a write address, and a head signal provided in the division management circuit at the head of a packet to be transmitted supplied from the preceding stage for each transmission buffer, and prepares for each transmission buffer. The total packet length and the write address are registered in the buffer monitoring table, and the priority information of the packet arriving at the transmission buffer (it is also the buffer number since the priority of the packet and the transmission buffer correspond one to one). ), A packet detection trigger indicating that the packet has arrived at the transmission buffer, and the total packet length of the packet arriving at the transmission buffer (in the figure, simply described as "packet length") is supplied to the division management circuit 31. .

The division management circuit 31 includes the buffer monitoring circuit 2
When the packet priority information, the packet detection trigger and the total packet length are received from 1, the total packet length is registered in the storage position of the corresponding priority in the division information table 33, and the division information table 33 is referred to. If necessary, stop reading of the packet being read, and output a buffer number, a read enable signal, and a read address to the read control circuit 41 in order to read the highest priority packet from the corresponding transmission buffer at that time. Then, the read out of the divided packet is performed from the transmission buffer.

When the reading of the packet of the specific priority is stopped, the read packet length and the next read address of the storage position of the corresponding priority in the division information table are updated.

Further, when the reading of the packet of the specific priority is completed, the storage position of the corresponding priority in the division information table is cleared, and the buffer number and the read completion trigger are supplied to the buffer monitoring circuit 21. Then, the corresponding buffer monitoring table is updated.

When the reading of the packets of the specified priority is stopped or when all the packets of the specified priority have been read, the division management circuit 31 sends the information of the total packet length and the read packet length to the header. The header and the trailer to be supplied to the trailer generation circuit 52 to be added to the divided packet are generated.

The selector 42 selects the divided packet read out according to the instruction from the division management circuit 31 and supplies it to the division buffer 51.

The header / trailer adding circuit 53
In response to a change in the read enable signal or a read completion trigger, the header and trailer output by the header / trailer generation circuit 52 are added to the divided packet and output.

FIG. 2 is a flowchart showing the operation of the configuration shown in FIG. 1, FIG. 3 is a diagram for explaining the read time and address of the packet from the transmission buffer, and FIG. 4 shows the transition of the contents stored in the division information table. FIG. 5 and FIG. 5 show the format of the fragmented packet. Hereinafter, the operation of the configuration shown in FIG. 1 will be described in more detail with reference to FIG.

Here, for the sake of specific description, the following cases are assumed in FIGS. That is, at time t0, the priority is 4 and the total packet length is 1,500.
When a packet 4 of bytes arrives and is written in the corresponding transmission buffer with the address 0 as a start address, and when 500 bytes of the packet 4 are read out at the time t1, the priority 3 and the total packet length of 1,500 bytes are read. When the packet 3 arrives and is written in the corresponding transmission buffer with the address 0 as the start address, and when the 750 bytes of the packet 3 are read out at time t2, the priority is 1
It is assumed that a packet 1 having a total packet length of 500 bytes arrives and is written to a corresponding transmission buffer with address 0 as a start address.
In the above description, to simplify the description as much as possible, it is assumed that a packet is written to all the transmission buffers with the address 0 as a start address, but the start address of each transmission buffer is originally set. Is optional.

As shown in FIG. 4, the structure of the division information table is such that the priority of a packet is defined as an address or a key (hereinafter, unified as an address), and the total of packets arriving at each priority is calculated. The packet length, the length of the read packet, the read address when resuming reading, and the remaining processing time allowed for packets of each priority are stored.

The buffer monitoring circuit extracts the total packet length from the head signal of the packet and transfers it to the division management circuit, and the division management circuit stores the total packet length in the division information table.

The length of the read-out packet is given by adding 1 to the number of steps to stop reading the read address generated by the address counter held by the division management circuit itself. This is from address 0 to address 49
When 500 bytes up to 9 are read and the reading is stopped, the number of steps is 499, and the length of the read packet is 500 bytes.

The read address is given from the address next to the address at which the reading was stopped.

As described above, when the start address of writing to the transmission buffer is 0, the read packet length and the read address become the same number, so that one storage can be omitted. If the write start address is set to an arbitrary address, it is necessary to store both addresses.

Further, the remaining time is set to 100 when a new packet arrives with the division management circuit referring to the timer,
The time elapsed while the same packet is waiting to be read is converted and subtracted, and the time when the allowable processing delay time has elapsed is set to 0.

In the division information table in the initial state, no significant information is stored, and the stored values are all 0.
It is. This is shown in FIG.

Returning to FIG.

S1. The buffer monitoring circuit 21 in FIG. 1 monitors whether or not a write enable signal to the transmission buffer from the previous stage has been received.

If the write enable signal has not been received (No), the above monitoring is continued.

S2. In step S1, when a write enable signal to the transmission buffer from the previous stage is received (Y
In es), the priority of the packet (corresponding to the buffer number on a one-to-one basis) depends on which input terminal corresponding to the transmission buffer detected the write enable signal. It is assumed that they are expressed by the same number.), The head signal of the packet is analyzed to extract information of the total packet length, and the start address of writing to the transmission buffer is recognized.

According to the assumption described above, since the packet 4 arrives earliest, the recognized priority is 4,
The extracted total packet length is 1,500, and the write start address is 0.

S3. The total packet length and the write start address are registered in the corresponding priority storage area of the buffer monitoring table.

In this case, the total packet length 1,500 and the write start address 0 are registered in the storage area of the priority 4 in the buffer monitoring table.

S4. The recognized priority and the total packet length are transferred to the division management circuit 31 of FIG. 1 together with the packet detection trigger indicating that a new packet has arrived, and the process returns to step S1.

S5. The division management circuit 31 receives the priority and the total packet length information from the buffer monitoring circuit 21 together with the packet detection trigger.

S6. After checking the timer 32, the division management circuit 31 proceeds to S7. The storage contents of the division information table 33 are updated.

At this point, since a packet having a total packet length of 1,500 of priority 4 has arrived, 1,500 and a remaining time of 100 are stored in the total packet length storage area of priority 4 in the division information table 33. Write. This is shown in FIG.

S8. At this point, the transmission buffer storing the highest priority packet is selected.

At this point, since only packet # 4 has arrived, the transmission buffer with the highest priority at this point is transmission buffer # 4 storing packet # 4.

S9. Information for reading supplied to the reading control circuit 41 constituting the multiplexing unit in FIG.
That is, a buffer number, a read enable signal, and a read address are set.

Now, since packet # 4 is stored starting from address 0 of transmission buffer # 4, buffer number # 4 and start address 0 are set.

S10. The division management circuit 31 sends a message to the header / trailer generation circuit 52 constituting the division unit in FIG.
The header information described in the header added to the fragmented packet is transmitted.

Although not shown, when the header / trailer generating circuit 52 receives the header information together with the read enable signal, it generates a header to be added to the divided packet.

FIG. 5 shows the format of a fragmented packet.
It is roughly divided into a header, data, and a trailer.

The header is a packet division unit I indicating the beginning of the divided packet, and a head / subsequent display unit indicating whether the divided packet is the first divided packet or the succeeding divided packet. II, priority class display section III indicating the priority of the packet, remaining time display section IV indicating the remaining time for the allowable processing time, total packet indicating the total packet length of the packet being read The length display unit V includes a read packet length display unit VI that indicates the length of a read packet at the start of reading among packets being read.

The data is the currently read data of the data of the arriving packet, and is supplied from the selector 42 of FIG. 1 to the header / trailer adding circuit 53 via the division buffer 51.

Further, the trailer has a total packet length display section VII, a read packet length display section VIII indicating the length of the packet being read out of the packets being read when the reading is stopped, and a further divided packet after the divided packet. A continuation packet presence / absence display section IX indicating whether or not to continue and a packet separation section X indicating the end of the divided packet.

Here, a special bit pattern that is very unlikely to appear in the header and trailer except for the data and the packet separating part is extremely small in the packet separating part added to the beginning and the end of the divided packet. , A relatively large number of bits are required.

The head / subsequent packet display section may be 2 bits to indicate the presence / absence of division and the presence / absence of a subsequent packet. Similarly, the continuous packet presence / absence display section indicates the presence / absence of division and the presence / absence of continuous packet. For this reason, two bits are sufficient.

For the other parts, the number of bits may be determined in consideration of the packet length and the processing time.

Therefore, the division management circuit 31 transmits the priority class # 4 and the remaining time 1 in step S10.
00, total packet length 1,500, read-out packet length 0, and 2 bits for displaying the first / subsequent packet.

S11. For the read control circuit 41,
The set information for reading, that is, the buffer number,
It outputs a read enable signal and a read address.

The information output first is a buffer number # 4, a read address 0, and a read enable signal.

Although not shown, when receiving the buffer number, the read enable signal, and the read address, the read control circuit 41 starts reading the packet from the specified address in the specified transmission buffer. In this case, packet reading is started from address 0 of the transmission buffer # 4.

S12. The division management circuit 31 compares the output read address with the total packet length stored in the division information table 33 to determine whether or not all the packets being read have been read.

Since it has just output the read address 0, it is determined that the reading has not been completed (No).

S13. If it is determined in step S12 that the reading has not been completed (No), the timer 32
To determine whether a timeout has occurred.

At present, the reading has just started and, of course, no timeout has occurred.

S14. If it is determined in step S13 that the timeout has not occurred (No), it is determined whether a packet having a higher priority than the packet currently being read has arrived at the transmission buffer.

This is because the buffer monitoring circuit 21 relates to the arrival of a new packet in parallel with the above processing (steps S1 to S4), and the buffer monitoring circuit 21 transmits when detecting the arrival of a new packet. Since the buffer number, the packet detection trigger, and the total packet length are received (step S5), the determination can be made by comparing the priority of the newly arrived packet with the priority of the packet being read.

According to the above assumption, when the packet of 500 bytes is read, the packet of the priority # 3 arrives, so that the packet having the higher priority than the packet currently being read arrives at the transmission buffer. If not (No), the process jumps to step S10, in which the read address is incremented and output. And the read address is 4
After reading the 500-byte packet at 99, it recognizes the arrival of the high-priority packet # 3. this is,
At the priority # 4 in FIG. 3B, this is the point in time when addresses 0 to 499 of the transmission buffer are read.

S15. If it is determined in step S14 that a packet having a higher priority than the packet currently being read has arrived at the transmission buffer (Yes), the reading of the packet being read is stopped.

S16. The division management circuit 31 stores the read stop address and temporarily stops the read enable signal.

At this time, since the data is read out to address 499, the read address to be stored is 499.

S17. The division management circuit 31 transmits the trailer information to be added to the trailer of the divided packet to the header / trailer generation circuit 52 constituting the division unit of FIG.
Jump to step S6.

Although not shown, the header / trailer generating circuit 52 detects that the read enable signal has stopped once, and upon receiving the trailer information, generates a trailer to be added to the divided packet.

Now, the total packet length is 1,500,
A trailer is generated by receiving the transmitted packet length 500 and 2 bits indicating the presence or absence of a continuation packet.

The header / trailer adding circuit 53
Receives the header generated after step S10 and the trailer just generated from the header / trailer generation circuit 52, receives the data supplied from the division buffer 51, and adds and outputs a header and a trailer before and after the data. I do. At present, a header and a trailer are added upon receiving 500 bytes of data.

The process jumps from step S17 to step S6 to check the timer 32, and in step S7, updates the storage contents of the division information table. Arrives, the total packet length 1,500 is written to the storage area of the priority # 3 in the division information table 33,
The read packet length 500 and the next read address 500 are written in the storage area of the priority # 4, and the remaining time is updated (here, it is set to 80). The storage contents of the division information table at this time are shown in FIG.

At this point, the packet with the highest priority is packet # 3. Therefore, in step S9, a read enable signal is output to the read control circuit 41 with the buffer number # 3 and the read address 0. , Starts reading packet # 3.

Thereafter, since packet # 3 is the highest priority packet until time t2 in FIG.
Steps S11 through S14 are repeated for packet #
Continue reading 3.

At time t2, the highest priority packet #
1 arrives, and stops reading packet # 3.
The process proceeds to reading packet # 1. At this time, the read packet length of the packet # 3 is 750 and the read stop address is 749. Therefore, the transmission packet length 750 and the next read start address 750 are stored in the storage area of the priority # 3 of the division information table 33. Also, the total packet length 500 of newly arrived packet # 1 is given a priority #
1 is written to the storage area. This is shown in FIG. FIG. 3 shows that 750 bytes of the packet of the priority # 3 were read between the time t1 and the time t2.

Thereafter, since the packet # 1 has the highest priority until the time t3, the reading of the packet # 1 is completed while repeating the processing of steps S11 to S14. It is determined that the processing has been completed (Yes).

S18. If it is determined in step S12 that the reading has been completed (Yes), the division management circuit 3
1 outputs a read completion trigger to the buffer monitoring circuit 21 and the header / trailer adding circuit 53.

S19. The division management circuit 31 determines whether all priority packets have been read.

If it is determined that packets of all priorities have been read (Yes), the process ends.

If it is determined that reading of all priority packets has not been completed, the process jumps to step S7 to update the storage contents of the division information table relating to the packets that have been read.

At this point, since the reading of the packet # 1 has been completed, the storage contents of the priority # 1 in the division information table 33 are cleared. FIG. 4E shows the contents stored in the division information table 33 in this state.

In FIG. 3, the priority # is set at time t3.
1 indicates that 500 bytes of packet # 1 have been read.

After the reading of the packet # 1 having the highest priority is completed at the time t3, it is assumed that the priority of the packet # 3 is high. Then, since there is no packet having the priority equal to or higher than the packet # 3, the reading of the packet # 3 is continuously performed, and the reading is completed at the time t4. This is shown in FIG. 3 in which packet # 3 of priority # 3 is transmitted between time t3 and time t4.
Are shown to be read out.

Then, since all the packets # 3 of the priority # 3 have been read, the priority # 3 of the division information table 33 is read.
Is cleared. This is shown in FIG.

Thereafter, all packets # 4 of priority # 4 are also read. This is shown in FIG. 3B as that packet # 4b of packet # 4 of priority # 4 is read between time t4 and time t5, and packet # 4
a, packet # 3a, packet # 1, packet # 3b,
This indicates that packets are read out and multiplexed in the order of packet # 4b.

Since all the packets # 4 of the priority # 4 have been read, the priority # 4 of the division information table 33 is read.
Is cleared, and the division information table 33 returns to the initial state. This is shown in FIG.

On the other hand, when a read completion trigger is received from the division management circuit 31, the buffer monitoring circuit 21 operates as follows.

S20. It monitors whether or not a read completion trigger has been received from the division management circuit 31.

If the read completion trigger has not been received (No), the above monitoring is continued.

S21. When the read completion trigger is received in step S20 (Yes), the storage contents of the buffer monitoring table corresponding to the packet are cleared.

For example, in the buffer monitoring table corresponding to the packet # 1 of the priority # 1, the total packet length 5
00 and the write start address 0 are stored. When the reading is completed, all the stored contents of the buffer monitoring table corresponding to the packet # 1 of the priority # 1 are cleared to 0.

S21. It is determined whether or not the stored contents of all the buffer monitoring tables have been cleared.

If it is determined that the contents stored in all the buffer monitoring tables have been cleared (Yes), the processing is terminated.

If it is determined that the contents stored in all the buffer monitoring tables have not been cleared (No), the process jumps to step S1 to shift to monitoring whether a new write enable signal has been received.

Although not shown, step S18
After that, when a read completion trigger is received from the division management circuit 31, the header / trailer addition circuit 53
The header and the trailer received from the trailer generation circuit 52 are added to the data received from the divided buffer 51 and output.

Now, the description of the configuration and operation of the packet transmitting apparatus of the present invention has been completed, but some additional explanation will be given on the format of the fragmented packet.

That is, the format of the fragment packet shown in FIG. 5 is to obtain the following advantages. (1) Most basically, if information on the read packet length at different times is described in the header and the trailer and transmitted,
Using the above information, the same packet can be stored in the packet receiving apparatus so as not to overlap with the empty packet.

(2) When there is an error in the packet division or division information and the read packet length stored in the division information table 33 is different from the read packet length described in the header, The error can be detected.

(3) Before reading all the packets being read, the packets are lost for some reason.
When different packets with the same priority arrive at the transmission buffer and are read out, the above situation can be detected based on the information of the total packet length.

(4) If there is an accidental failure in reading the packet and the reading of the packet does not end easily even though the reading is started, if the remaining time is described and transmitted, the receiving side Recognizing that fact, it can be processed.

However, the first / subsequent packet display section and the continuation packet presence / absence display section need not always be added separately for the header and the trailer. Instead of the read packet length, the length of a packet waiting to be read may be added.

The description of the packet transmitting apparatus of the present invention is completed above, and the description of the packet receiving apparatus of the present invention will be given hereinafter.

FIG. 6 shows the configuration of a packet receiving apparatus according to the present invention (No. 1), which has a receiving buffer corresponding to each of the transmission buffers of the configuration shown in FIG.

In FIG. 6, reference numeral 61 denotes a header / trailer separating circuit for separating a header and a trailer added to data divided by the packet transmitting apparatus, and 62 denotes a header / trailer separating circuit 61 for separating the header and the trailer. The data to be output (which has been described as “data” in the configuration of the divided packet, but is a part of the packet arriving at the packet transmitting apparatus, and hence is hereinafter referred to as “packet”) is the packet priority. And a distributing circuit for distributing the signals to the receiving buffers corresponding to the above.

Reference numeral 71 denotes a header / trailer analysis circuit for analyzing the header and trailer output from the header / trailer separation circuit 61. Reference numeral 72 denotes a header / trailer separated from the received packet based on the analysis result of the header / trailer analysis circuit 71. A coupling management circuit 73 for recognizing information on the received packet, supplying information for distributing the packet to the reception buffer to the distribution circuit, and further supplying a read enable signal from the reception buffer to the reception buffer and the subsequent stage; 73 Is a timer that the connection management circuit 72 refers to in the connection processing of the packet. 74 is a connection information table in which the connection management circuit 72 stores information necessary for the connection processing of the packet for each priority. The combination management unit is configured by the elements.

The distribution circuits 62, 91a and 91b
Is a reception buffer that writes, for each priority, a packet whose header and trailer have been separated from the divided packets by a write control signal output for each priority. These components constitute a reception buffer unit.

The functions of each part will be briefly described below mainly on the information transmitted and received by each part and the information stored therein.

The header / trailer separation circuit 61 separates the header and trailer from the received divided packet and supplies the header and trailer to the header / trailer analysis circuit 71. The header / trailer analysis circuit 71 also distributes the header and trailer separated packet from the divided packet. To supply.

The header / trailer analysis circuit 71 analyzes the header and the trailer supplied from the header / trailer separation circuit 61 and determines the priority of the received fragmented packet (this is because the header and the trailer are separated from the fragmented packet. One-to-one correspondence with the number of the receiving buffer in which the packet is written.), The total packet length of the packet, the packet length of the packet already received, and the address for writing the packet in the receiving buffer are extracted. It is supplied to the connection management circuit 72.

The connection management circuit 72 includes a priority of the packet received from the header / trailer analysis circuit, a total packet length of the packet, a packet length of the already received packet, and an address for writing the packet in the reception buffer. Is stored in the binding information table 74 for each priority, and the remaining time allowed for the binding process is calculated with reference to the timer 73 and stored in the binding information table 74 for each priority.

The connection management circuit 72 also assigns a buffer number (priority) and a write address to the reception buffer together with a write enable signal to the reception buffer.
2 and further supplies a read enable signal from the reception buffer to the reception buffer and the subsequent stage.

When the distribution circuit 62 receives the write enable signal, the buffer number, and the write address from the combination management circuit 72, the header / trailer separation circuit transmits the write enable signal and the write address to the reception buffer of the specified number. Supply the packet to output,
The packet is written to the reception buffer for each priority.

Each reception buffer is provided with a connection management circuit 72.
When a read enable signal is received from, the packet that has been written becomes readable, and the packet that has been written in the subsequent stage is supplied. Since the divided packets transmitted in each reception buffer are sequentially written for each priority, the packets read out from each reception buffer are obtained by restoring the packets arriving at the packet transmission device. .

FIG. 7 is a flowchart showing the operation of the configuration of FIG. 6, and FIG. 8 is a diagram showing the transition of the contents stored in the combination information table. Hereinafter, the operation of the configuration of FIG. 6 will be described in more detail with reference to FIG.

Here, in order to give a concrete description, FIG. 8 shows a state similar to that shown in FIG.
Is assumed to sequentially receive packets of priority # 1, priority # 3, and priority # 4.

Assuming that a state in which the packet receiving apparatus has not yet received a packet is an initial state, nothing is stored in the connection information table 74 in the initial state. This is shown in FIG.

When the divided packet transmitted from the packet transmitting apparatus arrives at the header / trailer separation circuit 61, the header / trailer separation circuit 61 separates the header and the trailer, and sends the separated header and trailer to the header / trailer analysis circuit 71. Forward. The flowchart of FIG. 7 starts from this stage.

S31. 6 monitors whether a header and a trailer are received from the header / trailer separation circuit 61.

When the header is not received by the trailer (N
In o), the above monitoring is continued.

S32. In step S31, when the header and the trailer are received from the header / trailer separation circuit 61 (Yes), the priority of the packet (the number of the receiving buffer), the total packet length, and the read-out packet length are extracted from the header, Extract the total packet length and read-out packet length from the trailer.

S33. Reference is made to the timer 73.

S34. From the header / subsequent packet display part of the header, it is determined whether the packet is the first packet or the subsequent packet.

S35. If it is determined in step S34 that the packet is the first packet (Yes), necessary items are registered in the binding information table 74. That is, the priority class is determined from the priority of the packet, the total packet length, the read packet length, the write address to the reception buffer, and the remaining time are registered in the storage area of the priority class, and the process jumps to step S39. I do. Since the head packet has been received at this time, a predetermined start address may be set as the write address to the reception buffer.

S36. If it is determined in step S34 that the packet is not the first packet (No), the previously registered binding information table is compared with the header just received (in the figure, referred to as "subsequent header").

S37. As a result of the comparison in step S36,
It is determined whether the packets are the same.

The determination may be made based on whether or not information on the received packet is stored in the storage area of the priority in the combination information table, and whether or not the total packet length and the read-out packet length of both are equal. . That is, it is only necessary to determine that the packet is the same when all of the above items are true, and to determine that the packet is not the same packet when any of the above items is false.

S38. If it is determined in step S37 that the packets are the same packet (Yes), the binding information table is updated based on the total packet length and read-out packet length of the currently received header, the write address to the reception buffer, and the remaining time. .

S39. The buffer number and the write address are supplied to the distribution circuit 62 together with the write enable signal, and the output of the header / trailer separation circuit 61 is written to a specific reception buffer.

S40. It is determined whether or not all the same packets have been stored in the reception buffer.

S41. If it is determined in step S41 that all the same packets are not stored in the reception buffer (No), the read packet length extracted from the trailer is stored as the read address of the binding information table, and the binding information table is updated. I do.

S42. It is determined whether or not a timeout has occurred by referring to the timer.

If it is determined that the timeout has not occurred (No), the process jumps to step S31, and the processing of each step described above is repeated.

S43. If it is determined in step S42 that a timeout has occurred (Yes), then in step S37,
If it is determined that the packets are not the same packet (No), the stored contents of the priority class in the binding information table are cleared, and the binding information table is updated, and S44. The contents stored in the reception buffer corresponding to the priority are also deleted, and the process jumps to step S31. this is,
If retransmission is performed when an accidental failure occurs in the packet transmission device, and if the succeeding packet is not the same packet as the preceding packet while having the same priority, the packet has already been received. This is for erasing a part of the packets stored in the reception buffer, and in accordance with this, the storage area of the priority in the combination information table is also cleared.

S45. When it is determined in step S41 that all the same packets have been stored in the reception buffer (Ye
In s), a read enable signal is supplied to the buffer and the subsequent stage to instruct reading of the packet stored in the buffer.

According to this instruction, the subsequent stage reads the packet from the reception buffer.

S46. The stored contents of the priority class corresponding to the buffer in the combined information table are cleared, and the combined information table is updated.

S47. It is determined whether the reading of the packet has been completed in all the reception buffers.

If it is determined that packet reading has not been completed in all the reception buffers (No), the process jumps to step S31.

When it is determined that the reading of the packet has been completed in all the reception buffers (Yes), the combination management circuit ends a series of processing.

Now, the explanation of the processing according to the above flowchart will be supplemented in association with the transition of the storage contents of the combination information table shown in FIG.

As shown in the lower part of FIG. 3B, first, packet # 4a is received. The header of the packet # 4a contains information indicating that the packet is the first packet, information indicating that the total packet length is 1,500, and information indicating that the read packet length is 0. Since information indicating that the total packet length is 1,500, information indicating that the read packet length is 500, and information indicating that there is a subsequent packet are described, step S
In step S35, it is determined that the packet is the first packet.
Register the total packet length of 1,500 bytes, the received packet length of 500 bytes, and the address of write address 0 in the storage area of the priority class # 4 in the binding information table, and have just received packet # 4a. Since there is, the remaining time 100 is registered. FIG. 8B shows the contents stored in the connection information table in this state.

Next, in step S39, a write enable signal is supplied to the distribution circuit 62 together with the buffer number # 4 and the write address 0, and a 500-byte packet # 4a is written into the buffer # 4. Packet # 4
Since there is a subsequent packet in a, the determination result in step S40 is No. In step S41, the write address of the binding information table is updated to 500 and the remaining time is updated. Here, it is assumed that the remaining time is 80. Since it is assumed that the time has not expired, the process jumps to step S31.

At this point, since packet # 3a is received, it is recognized from the header of packet # 3a that the packet is the first packet, that the total packet length is 1,500 bytes, and the received packet length is 0 bytes. The trailer recognizes that the packet # 3a is 750 bytes and that there is a subsequent packet, and stores a total packet length of 1,500, a received packet length of 750, a write address in the storage area of the priority # 3 of the binding information table. Register the address 0 and the remaining time 100. FIG. 8C shows the contents stored in the connection information table in this state.

When 750 bytes of packet # 3a are written in the reception buffer, 500-byte packet # 1 is received. Similarly to the above, using the analysis result of the header and the trailer of the packet # 1, the total packet length 500, the received packet length 500, the write address 0, the remaining time are stored in the storage area of the priority class # 1 in the connection information table. 1
Register 00. FIG. 8D shows the contents stored in the connection information table in this state. At this stage, the stored contents of the priority class # 4 remain as shown in FIG.

The total packet length of packet # 1 is 5
Since there is no subsequent packet in the 00 byte, step S4
The judgment of 0 is Yes. Since it is instructed to read out the packet # 1 from the buffer in step S45, the stored contents of the priority class # 1 in the combined information table become unnecessary. Therefore, in step S46, the storage content of the priority class # 1 in the binding information table is deleted, and the binding information table is updated. FIG. 8E shows the storage contents of the connection information table in this state. At this stage, the stored contents of the priority class # 3 and the priority class # 4 are shown in FIG.
(D) It remains.

Similarly, when packet # 3b is received and written into the reception buffer, the contents stored in the combination information table are as shown in FIG. Further, packet # 4
When b is received and written into the reception buffer, the stored contents of all the priority classes in the combined information table have been cleared.
(G)

Since it is assumed that one area for storing the received packet length is provided in the binding information table, the binding information table is updated in step S38 when a subsequent packet is received, and the received packet is After writing in the reception buffer, the binding information table is updated in step S41. However, if two areas for storing the received packet length are provided in the binding information table, the read packet length on the header and the trailer are stored. Since both of the above read packet lengths can be stored at once,
Step S41 can be deleted.

FIG. 9 shows a configuration (part 2) of a packet receiving apparatus according to the present invention, in which a received packet is written into a storage area secured for each priority of a common combining memory and combined therewith. is there.

In FIG. 9, reference numeral 61 denotes a header / trailer separation circuit for separating a header and a trailer from a received divided packet. 63 denotes a destination for writing a packet output from the header / trailer separation circuit, and a coupling memory. An input / output selector (abbreviated as “I / O selector” in the figure) that outputs the packet read from the reception buffer to the reception buffer, and these components constitute a coupling unit.

Reference numeral 71 denotes a header / trailer analysis circuit that analyzes the header and trailer output from the header / trailer separation circuit 61. Reference numeral 72a separates the header and the trailer from the received packet based on the analysis result of the header / trailer analysis circuit 71. A connection management circuit 73 that recognizes information about the received packet and generates connection processing information, a timer 73 that the connection management circuit 72a refers to when generating the connection processing information of the packet, and a connection management circuit 72a that the connection management circuit 72a A connection information table 75 for storing information necessary for the connection processing for each priority is provided by a connection management circuit 72a.
Input / output selector 63, an input / output management circuit that supplies a write control signal and a read control signal to the coupling memory and the reception buffer based on the coupling processing information (“I
Abbreviated as / O management circuit. ), The above components constitute a connection management unit.

Reference numeral 81 denotes a coupling memory for storing the packets output from the header / trailer separation circuit 61 in a storage area secured for each priority and coupling the packets.

Reference numeral 91 denotes an output from the input / output selector 63.
This is a reception buffer that temporarily stores the combined packets.

Hereinafter, the functions of each part will be briefly described mainly with respect to information transmitted and received by each part and information stored therein.

The header / trailer separation circuit 61 separates the header and the trailer from the received divided packet and supplies the separated header and trailer to the header / trailer analysis circuit 71. To supply.

The header / trailer analysis circuit 71 analyzes the header and trailer supplied from the header / trailer separation circuit 61, and determines the priority of the received divided packet, the total packet length of the packet, and the already received packet. The packet length of the packet and the address for writing the packet in the reception buffer are extracted and supplied to the connection management circuit 72a.

The combination management circuit 72a stores the priority of the packet received from the header / trailer analysis circuit 71, the total packet length of the packet, the packet length of the packet already received, and the The start address at which the packet is written is stored in the binding information table 74 for each priority, and the remaining time allowed for the binding process is calculated with reference to the timer 73 to obtain the binding information table 7.
4 is stored for each priority.

The connection management circuit 72a supplies the input / output management circuit 75 with connection processing information including the priority of the packet, the total packet length of the packet, and the packet length of the packet already received.

The input / output management circuit 75 includes a connection management circuit 72.
When receiving the combination processing information including the priority of the packet, the total packet length of the packet, and the packet length of the packet already received from a, a combination of a write enable signal and a write address is formed in the coupling memory 81. And a read control signal formed by a pair of a write control signal or a read enable signal and a read address.

The input / output management circuit 75 supplies a write enable signal to the coupling memory 81 and a read enable signal from the coupling memory 81 to the input / output selector 63, and the header / trailer separation circuit 61 outputs the signal. The writing of the packet to the combining memory 81 and the reading of the packet from the combining memory 81 are performed.

[0211] The input / output selector 63 is
5, the output of the header / trailer separation circuit 61 is connected to the coupling memory 81.
When the read enable signal supplied from the input / output management circuit 75 is received, a packet read from the coupling memory 81 is output to the reception buffer 91.

The reception buffer 91 is provided with an input / output management circuit 75.
Receiving the read enable signal supplied from the I / O management circuit 75, stores the packet read from the coupling memory 81 and supplied via the input / output selector 63; The combined packet is output.

FIG. 10 is a flowchart showing the operation of the configuration shown in FIG. 9, FIG. 11 is a view showing the transition of the contents stored in the connection information table and the connection memory, and FIG. 12 is an address mapping of the connection memory. FIG. Hereinafter, the operation of the configuration of FIG. 9 will be described in further detail with reference to FIG.

Here, in order to specifically explain, the packet receiving apparatus shown in FIG. 9 shows the packets of priority # 1, priority # 3 and priority # 4 at the bottom of FIG. It is assumed that they are sequentially received in the same manner as described above.

According to the above assumption, packet # 4a (500 bytes) of packet # 4 having priority # 4 and a total packet length of 1,500 bytes is first received, and thereafter, total # 4a is given priority # 3. Packet # 3a (750 bytes) of packet # 3 having a packet length of 1,500 bytes, packet # 1 (500 bytes) of priority # 1, packet # 3b (750 bytes) of priority # 3, priority Packet # 4b (1,000 bytes) of packet # 4 of degree # 4 is sequentially received.

The address of the corresponding coupling memory
The mapping is as shown in FIG. As described above, the order in which the packets are stored in the combining memory 81 is the same as the order in which the packets are received. Only the information on the total packet length and the received packet length described in the header and trailer of the received fragmented packet is used. This is because mapping is performed by using.

That is, first, when packet # 4a is received, the header and the trailer recognize that the total packet length is 1,500 bytes, and the trailer recognizes that the received packet length is 500 bytes. Therefore, a storage area of 1,500 bytes is secured for packet # 4. At this time, it is determined in advance that the start address for storing the received packet is address A. Therefore, the storage area for packet # 4 is an area having address A as the start address and address (A + 1,499) as the end address. And packet #
4a is stored from address A to address (A + 499).

Since addresses A to (A + 1,499) are secured as a storage area for packet # 4, the next received packet stores addresses (A + 1,500) and thereafter (this will be referred to as address B). Space is allocated.

Next, the header of the packet # 3a to be received indicates that the total packet length is 1,500 bytes, and the received packet length is 750 in the trailer.
It is described as a byte. Therefore, packet # 3
, Address B is used as the start address, and (B +
1,499) (this is C).
A storage area as an address is secured, and packet # 3b is stored in addresses B to (B + 749).

Next, when packet # 1 is received, it is recognized that the total packet length is 500 bytes and the received packet length is 500 bytes.
Addresses C to (C + 499) are reserved for 1, and the packet received at this time is stored in the above area.

Thereafter, when packet # 4b is received, it is stored in addresses (A + 500) to (A + 1,499), and when packet # 3b is received, it is stored in addresses (B + 750) to (B + 1,499). Therefore, the address mapping of the coupling memory 81 is determined as shown in FIG.

Each time a packet is received, the contents stored in the combination information table 74 and the combination memory 81 are changed as shown in FIG.
It changes as follows.

First, in the initial state in which no packet is received, nothing is stored in the binding information table for all priorities, and the prescribed start address is address A in the binding memory. , There is no stored address (0), so that the end address of the storage area is stored at address A. Nothing is stored in the storage areas corresponding to all priorities in the combination information table.
This is shown in FIG.

Next, when packet # 4a among packets of priority # 4 is received and packet # 4a is stored in the coupling memory, the total packet length is 1,500 bytes and the received packet length is 500 bytes. Therefore, the storage area of the priority # 4 of the binding information table has a total packet length of 1,500 bytes, a received packet length of 500 bytes, and a start memory of the binding memory.
The remaining time 100 is stored together with the address A, and the start address A, the stored address (A + 499), and the end address (A +
1,499) together with the stored 500-byte packet. FIG. 11B shows the contents stored in the connection information table 74 and the connection memory 81 in this state.

Next, in a state where the packet # 3a is received and stored in the coupling memory, the total packet length of 1,50 is stored in the storage area of the priority # 3 of the coupling information table 74.
0 bytes, the received packet length of 500 bytes, the start address A of the coupling memory, and the remaining time 100
Is stored, and only the remaining time is updated in the storage area of the priority # 4. Here, it is assumed that the remaining time is reduced to 80. On the other hand, the start address B and the stored address (B + 74) are stored in the storage area of the priority # 3 of the coupling memory 81.
9) The stored 750-byte packet is stored together with the address and the end address (B + 1,499).
FIG. 11C shows the contents stored in the connection information table 74 and the connection memory 81 in this state.

Further, when packet # 1 is received and stored in the coupling memory, the total packet length of 500 bytes and the received packet length of 500 bytes are stored in the storage area of the priority # 1 in the coupling information table 74. The remaining time 100 is stored together with the start address C of the memory, and only the remaining time is updated in the storage areas of priority # 4 and # 3. Here, the remaining time for priority # 4 is reduced to 60, and the remaining time for priority # 3 is reduced to 80. On the other hand, the priority # of the coupling memory 81
1, a start address C, a stored address (C + 449), and an end address (C + 49)
9) The stored 500-byte packet is stored together with the address. FIG. 11D shows the contents stored in the connection information table 74 and the connection memory 81 in this state.

Thereafter, every time the same packet is stored in the coupling memory 81, the packet is read out from the coupling memory and output to the reception buffer 91 each time the packet is read out of the coupling memory.
(E) As shown in FIG. 11 (f), the information on the packet which has been read from the combining memory is stored in the combining information table 74.
Then, after all packets are read from the combining memory 81 and all the packets are read from the combining memory 81, the contents stored in the combining information table 74 and the combining memory 81 return to the initial state as shown in FIG.

The transition of the contents stored in the combining information table 74 and the combining memory 81 when a packet is received as shown in FIG. 3B is described above. The process of combining the received packets as shown in FIG. Is shown in the flowchart of FIG.
Since this is essentially the same as the flowchart in FIG. 8, only the processing contents of the steps described in the flowchart in FIG. 10 will be described below.

S61. The header / trailer analysis circuit 71 in FIG. 9 monitors whether or not the header / trailer is received from the header / trailer separation circuit 61.

When the header is not received by the trailer (N
In o), the above monitoring is continued.

S62. In step S61, when the header and trailer are received from the header / trailer separation circuit 61 (Yes), the packet priority, the total packet length, and the read packet length are extracted from the header, and the total packet length is extracted from the trailer. , The length of the read packet and the like are extracted and supplied to the connection management circuit 72a.

S63. The connection management circuit 72 a
Please refer to FIG.

S64. From the header / subsequent packet display part of the header, it is determined whether the packet is the first packet or the subsequent packet.

S65. If it is determined in step S64 that the packet is the first packet (Yes),
Necessary items are registered in the connection information table 74 and the connection memory 81. That is, in the binding information table 74, the priority class is determined from the priority of the packet, and the total packet length, the received packet length, the start address of the writing to the combining memory 81 are stored in the storage area of the priority class. , The remaining time is registered, the start address of storage, the stored address, and the end address of storage are registered in the coupling memory 81, and the process jumps to step S69.

S66. If it is determined in step S64 that the packet is not the first packet (No), the previously registered combination information table is compared with the header just received (in the figure, referred to as “subsequent header”).

S67. As a result of the comparison in step S66,
It is determined whether the packets are the same.

The determination may be made based on whether or not the information on the received packet is stored in the storage area of the priority in the combination information table, and whether or not the total packet length and the read-out packet length of both are equal. . That is, it is only necessary to determine that the packet is the same when all of the above items are true, and to determine that the packet is not the same packet when any of the above items is false. If it is determined that they are not the same packet (No), the process jumps to step S61.

S68. If it is determined in step S67 that the packets are the same packet (Yes), only the remaining time in the combination information table 74 is updated, and the process proceeds to step S69.

S69. The write enable signal is supplied to the input / output selector 63, and the header / trailer separation circuit 6
1 is output to the write side of the input / output selector 63 to the coupling memory 81, and a write start address is supplied to the coupling memory 81 together with the write enable signal to combine the packets output by the input / output selector 63. Is written to the memory 81 for use.

S70. It is determined whether or not all the same packets have been stored in the combining memory 81.

S72. If it is determined in step S70 that all identical packets have not been stored in the combining memory 81 (No), it is determined whether or not a timeout has occurred by referring to a timer.

If it is determined that the timeout has not occurred (No), the process jumps to step S61, and the processing of each step described above is repeated.

S73. If it is determined in step S72 that a timeout has occurred (Yes), then in step S67,
If it is determined that they are not the same packet (No), the connection information table is updated by clearing the storage content of the priority class in the connection information table, and
By clearing the content of the priority class stored in the coupling memory 81, the coupling memory is updated, and the process jumps to step S61. This is because when retransmission is performed when an accidental failure occurs in the packet transmission device, and when the succeeding packet is not the same packet as the preceding packet while having the same priority, This is for erasing a packet that has been received and partially stored in the coupling memory 81, and in accordance with this, the storage area of the priority in the coupling information table is also cleared.

S75. When it is determined in step S70 that all the same packets have been stored in the combining memory 81 (Y
es), the read enable signal from the coupling memory 81 is supplied to the input / output selector 63, the coupling memory 81, and the reception buffer 91, and the read start address is supplied to the coupling memory 81, and Is written from the coupling memory 81 to the reception buffer 91 via the input / output selector 63.

S76. By clearing the storage contents of the priority class in the connection information table and the storage contents of the priority class in the connection memory 81, the storage contents of the connection information table 74 and the connection memory 81 are updated.

S77. It is determined whether reading of all packets from the combining memory 81 has been completed.

If it is determined that the packet reading has not been completed in all the reception buffers (No), the process jumps to step S61.

When it is determined that the reading of the packet has been completed in all the receiving buffers (Yes), a series of processing is ended.

Here, a case has been described where substantially the same information is redundantly stored in the combination information table 74 and a part of the combining memory 81. However, this is achieved by storing the same information redundantly. This is to increase the reliability of the information. If it is not particularly necessary to do so, the combination information table 74 may be deleted, or a packet other than the packet itself stored in the combination memory 81 may be deleted.

[0250]

As described above in detail, according to the present invention, a packet transmission device and a packet transmission device capable of improving the communication quality by reducing the processing delay time of information requiring high real-time performance and the fluctuation of the processing delay time. A receiving device and a packet communication system can be realized, and the utility of communication with high real-time properties on the Internet protocol can be further enhanced.

That is, according to the first aspect, regardless of the transmission priority, each time a packet arrives, a packet having the highest priority is selected, information indicating the priority is added, and transmission is started. Is repeated. As a result, even when a packet having a long packet length is being transmitted, when a packet having a higher priority than the packet being transmitted arrives, the process shifts to transmission of a packet with a higher priority. Therefore, after the transmission of the highest-priority packet is completed in a specific time zone, the transmission shifts to the transmission of the next highest-priority packet, so that the transmission can be completed in order from the packet with the highest priority. And the fluctuation of the processing delay time and the processing delay time of a packet having a high packet delay can be reduced. Since information indicating the priority of the packet, information indicating the total packet length, and information indicating the length of the packet that has been transmitted or is waiting to be transmitted is transmitted, even when a packet of a specific priority is divided and transmitted. In the packet receiving apparatus, it is possible to confirm that the packets have the same priority and the same packet, and to correctly combine and restore the divided and transmitted packets.

According to the second invention, when information indicating the priority of a packet is added to a received packet, packets having the same priority can be combined and restored, and the received packet can be restored. When information indicating the packet division status, information indicating the total packet length, and information indicating the length of the transmitted or waiting packet to be transmitted is added to the packet in addition to the information indicating the packet priority, the same priority is used. In addition, since it is possible to recognize that the packets are the same and combine them for restoration, it is possible to improve the reliability of restoration of the packets arriving at the packet transmitting apparatus.

According to the third aspect, when information indicating the priority of a packet is added and transmitted, the receiving side can combine and restore packets having the same priority.
In the case where information indicating the division status, information indicating the total packet length, and information indicating the length of a packet that has been transmitted or is waiting to be transmitted is transmitted in addition to the information indicating the packet priority, the reception side is the same. After confirming that the packets have the same priority, the packets can be combined and restored.

Further, according to the fourth invention, when all packets of a specific priority are transmitted to the packet transmitting apparatus, the packets of the specific priority are deleted, and all the packets of the specific priority are transmitted. If a predetermined time elapses before performing, a configuration for retransmitting the packet of the specific priority is arranged,
If the predetermined time elapses before all packets of a specific priority are combined, a configuration is provided in the packet receiving device to erase the packet of the specific priority and prepare for retransmission. Therefore, if the processing delay time of a packet becomes longer than a predetermined time due to an accidental failure on the transmitting side, the packet can be retransmitted. Need not be stored redundantly, the reliability of the packet communication system can be improved.

[Brief description of the drawings]

FIG. 1 shows the configuration of a packet transmission device according to the present invention.

FIG. 2 is a flowchart showing the operation of the configuration of FIG.

FIG. 3 shows a packet read time from a transmission buffer and an address.

FIG. 4 shows the transition of the contents stored in a division information table.

FIG. 5 shows a format of a fragmented packet.

FIG. 6 shows the configuration of a packet receiving apparatus according to the present invention (part 1).

FIG. 7 is a flowchart showing the operation of the configuration of FIG. 6;

FIG. 8 shows the transition of the content stored in the binding information table.

FIG. 9 shows a configuration of a packet receiving apparatus according to the present invention (part 2).

FIG. 10 is a flowchart showing the operation of the configuration of FIG. 9;

FIG. 11 shows the transition of the contents stored in the binding information table and the binding memory.

FIG. 12 is an address mapping of a coupling memory.

FIG. 13 illustrates the principle of the present invention (part 1).

FIG. 14 illustrates the principle of the present invention (part 2).

FIG. 15 shows a problem in the conventional packet communication system.

[Explanation of symbols]

 Reference Signs List 11 transmission buffer 11a transmission buffer 11b transmission buffer 21 buffer monitoring circuit 22 buffer monitoring table 22a buffer monitoring table 22b buffer monitoring table 31 division management circuit 32 timer 33 division information table 41 read control circuit 42 selector 51 division buffer 52 header / trailer generation circuit 53 Header / Trailer Addition Circuit 61 Header / Trailer Separation Circuit 62 Distribution Circuit 63 Input / Output Selector 71 Header / Trailer Analysis Circuit 72 Connection Management Circuit 72a Connection Management Circuit 73 Timer 74 Connection Information Table 75 Input / Output Management Circuit 81 Connection Memory 91 Receive buffer 91a Receive buffer 91b Receive buffer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Setsuo Abiru 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Limited (reference) 5K030 GA02 HA08 HB28 JA05 KA03 LA03 5K034 AA03 BB06 HH12 MM21 MM25

Claims (4)

[Claims] A priority is set for each packet to be transmitted, and a packet having the highest priority is selected and read out each time a packet arrives, and information indicating the priority of the packet and a total packet length are determined. A packet transmitting apparatus, which adds information to be indicated and packet division information to transmit the packet. 2. A packet having a specific priority is stored in a specific storage circuit in accordance with an analysis result of the information added to the received packet according to claim 1, and the divided packets are combined and restored. A packet receiving apparatus. 3. A packet communication system, wherein the packet transmitting apparatus according to claim 1 is arranged on a transmitting side, and the packet receiving apparatus according to claim 2 is arranged on a receiving side. 4. The packet communication method according to claim 3, wherein when all packets of a specific priority have been transmitted to said packet transmitting device, said packet of said specific priority is deleted, and said specific priority is deleted. If a predetermined time elapses before all the packets of the specified priority are transmitted, a configuration for retransmitting the packet of the specific priority is arranged. A packet communication system characterized by arranging a configuration for erasing the packet of the specific priority and preparing for retransmission when the predetermined time has elapsed.