JP2002175053A - Active matrix display and mobile terminal which uses the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display in which a narrower frame can be formed in a polysilicon TFT structure integrated with drive circuits, and to provide a mobile terminal which uses the above device as a display part. SOLUTION: In the polysilicon TFT-active matrix type liquid crystal display device integrated with drive circuits, at least one of circuits relating to signals with small amplitudes or circuits relating to the power supply voltage, or a part of the circuits relating to the signals with small amplitudes such as a sampling clutch circuit 132, or a part of the circuits relating to the power supply voltage, such as a circuit 19 generating the voltage on a counter electrode is formed by using TFTs having a dual gate structure. Other circuits are formed by using TFTs, having a top gate structure or a bottom gate structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device and a portable terminal using the same, and more particularly, to a drive circuit integrally formed on the same substrate as a display area in which pixels are arranged in a matrix. The present invention relates to a so-called active-matrix display device integrated with a driving circuit and a portable terminal using the same as a display unit.

[0002]

2. Description of the Related Art In recent years, portable telephones and PDAs (Personal Digital
gital Assistants) and other mobile terminals are remarkable. One of the factors behind the rapid spread of these mobile devices is that
There is a liquid crystal display device mounted as the output display unit. The reason is that the liquid crystal display device has a characteristic that does not require power for driving in principle, and is a display device with low power consumption.

In an active matrix type display device using a polysilicon TFT (Thin Film Transistor) as a switching element of a pixel, a poly-silicon TFT (Thin Film Transistor) is formed on the same substrate as a display area where pixels are arranged in a matrix. There is a tendency to integrally form a drive circuit using a silicon TFT. An active matrix type display device integrated with a driving circuit using a polysilicon TFT is very promising as a technology enabling small size, high definition and high reliability. Polysilicon TFT
Has a mobility approximately two orders of magnitude higher than that of an amorphous silicon TFT, so that the driving circuit can be integrally formed on the same substrate as the display area.

On the other hand, a polysilicon TFT has a lower mobility, a larger threshold voltage Vth, and a larger variation than a single-crystal silicon transistor, so that a high-speed circuit or a low-voltage circuit can be constructed. There is a problem that you can not. Threshold voltage Vth
The size of the variation makes it particularly difficult to configure a differential circuit that requires a pair of transistors having the same characteristics, which is a very serious problem in circuit design.

The variation of the threshold voltage Vth is caused by the TFT
Is high impedance. That is, since the conventional TFT has a gate structure of either a bottom gate structure or a top gate structure, the back gate of the transistor has high impedance, and the variation of the threshold voltage Vth is increased. Therefore, a TFT having such characteristics
It is very difficult to create a low voltage circuit, a small signal amplitude circuit, etc.

On the other hand, a structure in which a gate electrode is provided on the back gate side of the transistor and connected to the gate electrode on the front side, that is, as shown in FIG. Channel region 1
03, a pair of gate electrodes (front gate electrode 1
04 and a back gate electrode 105), and the gate electrodes 104 and 105 are connected to each other by a contact portion 106 (hereinafter, this structure is referred to as a dual gate structure). The TFT having the dual gate structure has an advantage that variation in the threshold voltage Vth can be reduced.

[0007]

However, in a TFT having a dual gate structure, as is apparent from FIG.
Since it is necessary to provide a contact area including a contact portion 106 for connecting the pair of gate electrodes 104 and 105, the area required for forming an element increases. Therefore, when a driving circuit is formed using a TFT having a dual gate structure, a very large circuit area is required, and as a result, the frame of the display device (the peripheral area of the display area portion) becomes large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an active matrix type display device capable of narrowing a frame in a polysilicon TFT structure integrated with a driving circuit, and To provide a mobile terminal using the same as a display unit.

[0009]

In order to achieve the above object, according to the present invention, there is provided a transistor circuit including transistors operating in pairs together with a display area in which pixels having electro-optical elements are arranged in a matrix. An active matrix display device formed over the same substrate, in which the transistor circuit is formed using a dual-gate thin film transistor including a pair of gates arranged and connected to each other with a channel interposed therebetween. I have. Further, in an active matrix type display device in which a first circuit for handling a signal with a small amplitude and a second circuit for handling a power supply voltage are integrally formed together with a display area on the same substrate, At least one of the circuits
This embodiment employs a dual gate thin film transistor having a pair of gates arranged and connected to each other with a channel interposed therebetween. These active matrix display devices are used as display units of mobile terminals.

In the active matrix type display device having the above structure or a portable terminal using the same, a transistor circuit including a pair of transistors or a circuit for handling a signal having a small amplitude is formed by a thin film transistor having a dual gate structure. Variations in the threshold voltage Vth are suppressed, and a highly reliable circuit is formed. On the other hand, a circuit having a high current capability is formed by forming a circuit that handles a power supply voltage with a thin film transistor having a dual-gate structure.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a configuration example of a display device according to the present invention. Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

In FIG. 1, an H driver (horizontal driving circuit) is provided on a transparent insulating substrate, for example, a glass substrate 11, together with a display area section 12 in which a large number of pixels including liquid crystal cells are arranged in a matrix. 13 and a V driver (vertical drive circuit) 14 are mounted. Glass substrate 11
A first substrate on which a number of pixel circuits including active elements (eg, transistors) are arranged and formed in a matrix;
It is composed of the first substrate and a second substrate which is arranged to face the first substrate with a predetermined gap. Then, a liquid crystal is sealed between the first and second substrates.

FIG. 2 shows an example of a specific configuration of the display area section 12. Here, for simplification of the drawing, a case of a pixel array of 3 rows (n-1 row to n + 1 row) and 4 columns (m-2 column to m + 1 column) is taken as an example. In FIG. 2, vertical scanning lines...
−1, 21n, 21n + 1,..., And data lines.
, 2m-2, 22m-1, 22m, 22m + 1,... Are wired in a matrix, and the intersection of the unit pixels 2
3 are arranged.

The unit pixel 23 has a structure including a polysilicon thin film transistor TFT as a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. here,
The liquid crystal cell LC means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed to face the pixel electrode.

In the thin film transistor TFT, the gate electrodes have vertical scanning lines..., 21n-1, 21, n, 21n + 1,.
, And the source electrode is connected to the data line.
2, 22m-1, 22m, 22m + 1,... In the liquid crystal cell LC, the pixel electrode is a thin film transistor T
The counter electrode is connected to the common line 24 and the drain electrode of the FT is connected. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 24. The common line 24 is supplied with a common electrode voltage (common voltage) Vcom.

Vertical scanning lines..., 21n-1, 21n,
21n + 1 are connected to the V driver 14 shown in FIG.
Is connected to each output terminal of the corresponding row of. The V driver 14 is configured by, for example, a shift register,
The operation starts in response to the vertical start pulse VST, and sequentially generates vertical selection pulses in synchronization with the vertical transfer clock VCK to generate vertical scanning lines..., 21n-1, 21, n, 21
Vertical scanning is performed by giving to n + 1,.

Data lines ..., 22m-2, 22m-
1, 22m, 22m + 1,...
Each output terminal of the corresponding column of the driver 13 is connected. As is apparent from FIG. 1, the H driver 13 has a digital interface driver configuration including a shift register 131, a sampling latch circuit (data signal input circuit) 132, a line sequential latch circuit 133, and a DA conversion circuit 135. For example, it is arranged along the upper side of the display area section 12.

Referring again to FIG. 1, a clock I / F (interface) circuit 15, a synchronizing signal I / F circuit 16, a timing generation circuit 17, The reference voltage generation circuit 18, the common electrode voltage generation circuit 19, and the power supply voltage conversion circuit 20 are formed integrally with the display area unit 12. These circuits 13 to 20 are formed together with the display area unit 12 using the same polysilicon TFT as that of each pixel transistor.

The clock I / F circuit 15 takes in a master clock MCK provided from outside the substrate, and supplies the master clock MCK to the timing generation circuit 17. The synchronizing signal I / F circuit 16 receives a horizontal synchronizing signal HD and a vertical synchronizing signal VD supplied from outside the substrate, and outputs these synchronizing signals HD and VD to the timing generator
Give 7

The timing generation circuit 17 has a clock I /
A master clock MCK provided from the F circuit 15,
Horizontal synchronization signal H provided from synchronization signal I / F circuit 16
Based on D and the vertical synchronization signal VD, various timing signals such as the above-described vertical start pulse VST, vertical transfer clock VCK, horizontal start pulse HST, and horizontal transfer clock HCK are generated.

The reference voltage generation circuit 18
And generates a reference voltage corresponding to the number of gradations corresponding to the number of bits of the input image data.
To supply. The common electrode voltage generation circuit 19 generates a common electrode voltage (common voltage) Vcom to be commonly applied to the common electrode of the liquid crystal cell for each pixel, and applies the common electrode voltage Vcom to the common line 24 in FIG.

The power supply voltage conversion circuit 20 converts a single DC power supply voltage supplied from outside the substrate into a plurality of types of DC voltages having different voltage values, and supplies these DC voltages to each circuit section. As an example, the H driver 13 uses different DC power supply voltages for the logic unit and the analog unit, and the V driver 14 for writing information to pixels uses a DC power supply voltage having a larger absolute value than the H driver 13 side. Will be.

In the active matrix type liquid crystal display device having the above configuration, the H driver 13, V driver 14, clock I / F circuit 15, synchronization signal I / F circuit 16 and timing generation circuit 17 are circuits for handling small amplitude signals. It is. Although not shown, a CPU I / F circuit and the like are also examples of circuits that handle signals of small amplitude. A circuit that handles these small-amplitude signals uses a transistor threshold voltage Vth
This is a circuit whose variation is to be suppressed as much as possible. On the other hand, the reference voltage generation circuit 18, the common electrode voltage generation circuit 19, and the power supply voltage conversion circuit 20 are circuits that handle the power supply voltage.
These circuits that handle the power supply voltage are circuits that want to increase the current capability of the transistor as much as possible.

Therefore, in the active matrix type liquid crystal display device according to the present embodiment, at least one of a circuit for handling a small amplitude signal and a circuit for handling a power supply voltage, or a part of a circuit for handling a small amplitude signal Some of the circuits that handle the power supply voltage or some of the circuits that handle the power supply voltage are created using dual-gate TFTs, and other circuits are created using top-gate or bottom-gate TFTs. I do.

Since the TFT having the dual gate structure has an excellent characteristic that the variation of the threshold voltage Vth is small, the reliability of the circuit is improved by forming a transistor circuit using the dual gate TFT. Therefore, it is useful for a circuit that handles a signal having a small amplitude, particularly a transistor that operates in pairs, that is, a circuit that includes a pair of transistors having substantially equal characteristics, such as a differential circuit and a current mirror circuit. .

However, in the case of a TFT having a dual gate structure, it is necessary to provide a contact area for connecting the front gate electrode and the back gate electrode, and the area required for forming an element becomes large. If all circuits are created using gate TFTs, the circuit scale becomes enormous. Therefore, among circuits that handle signals of small amplitude, the minimum necessary circuits such as circuits including transistors that operate in pairs are created using dual-gate TFTs, and other circuits require a small area. It is formed using a TFT having a gate structure or a bottom gate structure. This makes it possible to configure a highly reliable circuit with small variations in the threshold voltage Vth without increasing the circuit scale.

Further, the TFT having the dual gate structure has a feature that, although having a small area in plan view, it is equivalent to forming a transistor having a larger size, and has a large current capability. Therefore, by creating a circuit that handles power supply voltage using this dual-gate TFT, the current capability of the circuit can be increased. However, as in the case described above, if all circuits are created using dual-gate TFTs, the circuit scale becomes enormous. Therefore, the minimum necessary circuits are created using dual-gate TFTs. For other circuits, TFTs with a top gate structure or bottom gate structure
Thus, a circuit having a high current capability can be configured without increasing the circuit scale.

Here, a TFT having a bottom gate structure, a TFT having a top gate structure, and a TF having a dual gate structure
Each specific structure of T will be described with reference to FIG.
3A shows a sectional structure of a TFT having a bottom gate structure, FIG. 3B shows a sectional structure of a TFT having a top gate structure, and FIG. 3C shows a sectional structure of a TFT having a dual gate structure.

First, in a TFT having a bottom gate structure, as shown in FIG. 3A, a gate electrode 32 is formed on a glass substrate 31, and a channel region (polysilicon) is formed thereon via a gate insulating film 33. A layer 34 is formed thereon, and an interlayer insulating film 35 is further formed thereon. And
A source region 36 and a drain region 37 are formed on the gate insulating film 33 on the side of the gate electrode 32, and a source electrode 38 and a drain electrode 39 are connected to these regions 36 and 37 through an interlayer insulating film 35, respectively. The structure is such that an insulating film 40 is formed thereon.

Next, in the TFT having the top gate structure, as shown in FIG. 3B, a channel region (polysilicon layer) 42 is formed on a glass substrate 41, and a gate insulating film 43 is formed thereon. Thus, a gate electrode 44 is formed, and an interlayer insulating film 45 is further formed thereon. And
A source region 46 and a drain region 47 are formed on the glass substrate 41 on the side of the channel region 42, and a source electrode 48 and a drain electrode 49 are connected to these regions 46 and 47 through an interlayer insulating film 45, respectively. And an insulating film 50 is formed thereon.

Finally, in the dual-gate TFT, as shown in FIG. 3C, a front gate electrode 52 is formed on a glass substrate 51, and a channel region (poly) is formed thereon via a gate insulating film 53. A silicon layer 54 is formed, and an interlayer insulating film 55 is further formed thereon. Further, on the front gate electrode 52, a back gate electrode 56 is formed with a channel layer 54 and an interlayer insulating film 55 interposed therebetween. And the front gate electrode 5
A source region 57 and a drain region 58 are formed on the gate insulating film 53 on the side of the second region 2.
8, a source electrode 59 and a drain electrode 60 are connected to each other through an interlayer insulating film 55, and an insulating film 61 is formed thereon.

Next, as a specific example of a circuit for handling a signal having a small amplitude, FIG. 4 shows a specific configuration example of a sampling latch circuit using a differential circuit (corresponding to the sampling latch circuit 132 in FIG. 1). Show.

The sampling latch circuit according to this embodiment has an NchMOS transistor Qn11 and a PchMOS
CMOS inverter 71 including transistor Qp11
And NchMOS transistors Qn12 and Pch having their gates and drains connected in common, respectively.
It has a comparator configuration in which a CMOS inverter 72 composed of a MOS transistor Qp12 is connected in parallel.

Here, the input terminal of the CMOS inverter 71 (the common gate connection point of the MOS transistors Qn11 and Qp11) and the output terminal of the CMOS inverter 72 (the common drain connection point of the MOS transistors Qn12 and Qp12).
The input terminal of the CMOS inverter 72 (the common connection point of the gates of the MOS transistors Qn12 and Qp12) and the output terminal of the CMOS inverter 71 (the common connection point of the drains of the MOS transistors Qn11 and Qp11)
And are connected.

The input terminal of the CMOS inverter 71 receives a data signal from a signal source 73 via a switch SW1, and the input terminal of the CMOS inverter 72 receives a comparison voltage from a voltage source 74 via a switch SW2. . The power supply side common connection point of the CMOS inverters 71 and 72 is connected to the power supply VDD via the switch SW3. The switches SW1 and SW2 are directly controlled by a sampling pulse (supplied from the shift register 131 in FIG. 1), and the switch SW3 is controlled by an inverted pulse of the sampling pulse passed through the inverter 75.

The gate connection point of the PMOS inverter 71,
That is, the potential of the node A is inverted by the inverter 76 and the next-stage line sequential latch circuit (the line sequential latch circuit 1 in FIG. 1).
33). The potential of the gate common connection point of the CMOS inverter 72, that is, the potential of the node B is inverted by the inverter 77 and supplied to the next-stage line sequential latch circuit.

In the sampling latch circuit having the above configuration, the CMOS inverter 71 and the CMOS inverter 72
Constitute a comparator using a differential circuit. Therefore, the NchMOS transistor Qn11 and the NchMO
S transistor Qn12 operates as a pair, and PchMOS
Transistor Qp11 and PchMOS transistor Qp
12 operate in pairs.

As described above, in a transistor circuit that operates in a pair such as a differential circuit, it is necessary to use a transistor pair having the same characteristics. Therefore, in a sampling latch circuit using a comparator having a differential circuit configuration,
MOS transistor Qn1 of CMOS inverter 71
1, Qp11 and MOS transistors Qn12, Qp12 of CMOS inverter 72 are connected to threshold voltage Vth
By using a TFT having a dual gate structure with a small variation in the circuit size, the reliability of the circuit can be improved and a stable operation can be performed.

In this embodiment, in the sampling latch circuit, the MOS transistors Qn11 and Qp11 of the CMOS inverter 71 and the MOS transistors Qn12 and Qp12 of the CMOS inverter 72 are configured using dual-gate TFTs. The transistors used as the switches SW1 and SW2 are not limited to the above. By configuring the transistors using the dual-gate TFTs, the reliability of the circuit can be improved, and stable operation can be performed. Become.

Next, as a specific example of a circuit for handling a power supply voltage, FIG. 5 shows a specific configuration example of a common electrode voltage generation circuit (corresponding to the common electrode voltage generation circuit 19 in FIG. 1).

The counter electrode voltage generating circuit according to the present embodiment includes a switch circuit 81 for switching and outputting a positive power supply voltage VCC and a negative power supply voltage VSS at a constant cycle, and a switch circuit 81 for outputting the output voltage VA of the switch circuit 81. A DC level conversion circuit 82 converts a DC level and outputs the converted voltage as a common electrode voltage Vcom.

The switch circuit 81 has a positive power supply voltage VCC.
For example, an Nch MOS transistor switch Qn21 which receives an input and an NchM transistor which receives a negative power supply voltage VSS.
An OS transistor switch Qn22. The transistors Qn21 and Qn22 are switched by control pulses φ1 and φ2 having opposite phases to alternately output a positive power supply voltage VCC and a negative power supply voltage VSS at a constant cycle. Configuration. As a result, the switch circuit 81 outputs the voltage VA having the amplitude VSS to VCC.

The DC level conversion circuit 82 converts the level of the output voltage VA having the amplitude VSS to VCC of the switch circuit 81 into, for example, a DC voltage having the amplitude VSS-ΔV to VCC-ΔV and outputs the converted voltage as the common electrode voltage Vcom. Although various circuit configurations are conceivable as the DC level conversion circuit 82, a simple circuit configuration including a capacitor and a DC voltage generation circuit is generally used.

In the counter electrode voltage generation circuit having the above configuration, the MOS transistors Qn21 and Qn22 are required to have a current capability since they directly handle the power supply voltages VCC and VSS. Therefore, these MOS transistors Qn21, Qn
22 is a dual-gate TFT with large current capability
, The current capability of the circuit can be increased.

Subsequently, as another specific example of the circuit for handling the power supply voltage, a power supply voltage conversion circuit (the power supply voltage conversion circuit 2 in FIG. 1)
6 is shown in FIG. The power supply voltage conversion circuit according to the present example is a charge pump type DC-DC converter. 6A shows a negative voltage generation type, and FIG. 6B shows a boost type.

In FIG. 6A, a PchMO is connected between a power supply for applying a single DC power supply voltage VCC and ground.
S transistor Qp31 and NchMOS transistor Q
n31 are connected in series, and each gate is connected in common to form a CMOS inverter 83. This C
A switching pulse having a predetermined frequency is applied from a pulse generation source 84 to a common connection point of the gates of the MOS inverter 83.

One end of a capacitor C11 is connected to a common drain connection point of the CMOS inverter 83.
The other end of the capacitor C11 is connected to the drain of the NchMOS transistor Qn32 and the source of the PchMOS transistor Qp32. NchM
A load capacitor C12 is connected between the source of the OS transistor Qn32 and the ground. PchM
The drain of the OS transistor Qp32 is grounded.

One end of a capacitor C13 is connected to a common connection point of the gates of the CMOS inverter 83. The other end of the capacitor C13 has an anode of a diode D11, an NchMOS transistor Qn32 and a PchM
The gates of the OS transistor Qp32 are connected to each other. The cathode of the diode D11 is grounded.

The power supply voltage conversion circuit of the boost type shown in FIG. 6B has the same basic circuit configuration. That is, in FIG. 6B, the switching transistors (MOS transistors Qp32, Qn32)
Are the MOS transistors Qn33, Qn33 in the circuit of FIG.
Qp33 and the diode D11
Is connected between the other end of the capacitor C11 and the power supply (VCC), and this point is different only in configuration from the circuit of FIG.

In the power supply voltage conversion circuit having the above configuration, M which handles the power supply voltages VCC and VSS (ground in this example) is used.
OS transistors Qp31, Qn31 and switching transistors Qp32, Qn32 (Qn33, Qp3
3) a TFT with a dual gate structure with large current capability
, The current capability of the circuit can be increased.

Here, a specific circuit configuration has been described by taking as an example a sampling latch circuit as a circuit for handling small amplitude signals, and a counter electrode voltage generation circuit and a power supply voltage conversion circuit as circuits for handling power supply voltage. Is merely an example, and it goes without saying that the other circuits shown in FIG. 1 may also be applied to a circuit configured using a TFT having a dual gate structure.

As described above, in a polysilicon TFT-active matrix type liquid crystal display device integrated with a driving circuit, at least one of a circuit for handling a small amplitude signal and a circuit for handling a power supply voltage, or a circuit for handling a small amplitude signal A part of the circuit or a part of the circuit that handles the power supply voltage is formed by using a TFT having a dual gate structure, and the other circuits are formed by using a TFT having a top gate structure or a bottom gate structure. A highly reliable circuit in which the variation in the value voltage Vth is suppressed, and a circuit in which the current capability is increased can be configured.

Also, since each circuit for handling a signal having a small amplitude and each circuit for handling a power supply voltage are formed integrally on the same substrate together with the display area section 12, the number of interface terminals can be reduced. , Cost reduction, reduction of the number of IC terminals, noise reduction, etc.
In addition, the combined use of a dual-gate TFT and a top-gate or bottom-gate TFT can reduce the circuit scale, so that a drive circuit-integrated display device with a narrow frame can be realized.

In the above embodiment, the case where the present invention is applied to an active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this. The present invention can be similarly applied to other active matrix display devices such as an EL display device used as an element.

The active matrix type display device represented by the active matrix type liquid crystal display device according to the above embodiment is used not only as a display for OA equipment such as a personal computer and a word processor, but also for a display such as a television receiver. It is suitable for use as a display unit of a portable terminal such as a cellular phone or a PDA whose main body has been reduced in size and size.

FIG. 7 is an external view schematically showing the configuration of a portable terminal to which the present invention is applied, for example, a portable telephone.

The portable telephone according to this embodiment has a configuration in which a speaker 92, a display 93, an operation unit 94, and a microphone 95 are arranged in this order from the upper side on the front side of an apparatus casing 91. In the mobile phone having such a configuration, the display unit 9
For example, a liquid crystal display device 3 is used as the liquid crystal display device 3, and the active matrix liquid crystal display device according to the above-described embodiment is used as the liquid crystal display device.

As described above, in a portable terminal such as a portable telephone, by using the active matrix type liquid crystal display device according to the above-described embodiment as the display unit 93,
Since the liquid crystal display device has a narrow frame and each of its constituent circuits has excellent performance characteristics, it is possible to improve the performance of the terminal body and to reduce the size and cost.

[0059]

As described above, according to the present invention,
In an active matrix display device or a portable terminal using the same as a display portion, at least one of a circuit that handles a signal with a small amplitude and a circuit that handles a power supply voltage,
Alternatively, for a part of a circuit for handling a signal of a small amplitude or a part of a circuit for handling a power supply voltage, a T of a dual gate structure is used.
By using FT and other circuits using top-gate or bottom-gate TFTs, without increasing the circuit scale,
A circuit in which the variation in the threshold voltage Vth is suppressed and a circuit in which the current capability is increased can be configured.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a display area of a liquid crystal display device.

3A and 3B are cross-sectional structural views of a TFT, in which FIG. 3A shows a case with a bottom gate, FIG. 3B shows a case with a top gate structure, and FIG. 3C shows a case with a dual gate structure.

FIG. 4 is a circuit diagram illustrating a specific configuration example of a sampling latch circuit.

FIG. 5 is a block diagram illustrating a specific configuration example of a common electrode voltage generation circuit.

FIG. 6 is a circuit diagram showing a specific configuration example of a power supply voltage conversion circuit.

FIG. 7 is an external view schematically showing a configuration of a mobile phone as a mobile terminal according to the present invention.

FIG. 8 is a plan pattern diagram of a TFT having a dual gate structure.

[Explanation of symbols]

11, 31, 41, 51: glass substrate, 12: display area, 13: H driver (horizontal drive circuit), 14: V driver (vertical drive circuit), 15: clock I / F circuit,
Reference Signs List 16: Synchronous signal I / F circuit, 17: Timing generation circuit, 18: Reference voltage generation circuit, 19: Counter electrode voltage generation circuit, 20: Power supply voltage conversion circuit, 23: Unit pixel, 3
2, 44 gate electrode, 52 front gate electrode, 5
6 back gate electrode, 131 shift register, 13
2: sampling latch circuit, 133: line sequential latch circuit, 134: reference voltage selection type DA converter

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612B 614 617L F term (Reference) 2H092 GA59 JA26 JA37 JA38 JB13 JB38 JB46 JB57 JB63 JB69 KA04 KA07 NA22 NA27 2H093 NA16 NA53 NC15 NC21 NC22 NC23 NC25 NC26 NC34 NC35 ND31 ND60 NG01 5C006 AC02 AF83 AF84 BB16 BC06 BC20 BF25 BF34 BF43 EC13 FA41 5C094 AA13 AA15 AA25 AA53 A04 EB01 FA04 FB14 FB15 GA10 5F110 AA04 BB02 BB04 CC01 CC05 EE30 GG02 GG13 NN78

Claims (18)

[Claims] 1. A transistor circuit including transistors operating in pairs is integrally formed on a same substrate together with a display area in which pixels having electro-optical elements are arranged in a matrix. And an active matrix display device formed of a dual-gate thin film transistor having a pair of gates arranged and connected to each other with a channel interposed therebetween. 2. A horizontal drive circuit formed on the same substrate together with the display area unit and including a sampling latch circuit for sequentially sampling and latching input image data, wherein the transistor circuit constitutes the sampling latch circuit. 2. An active matrix display device according to claim 1, wherein the active matrix display device is a differential circuit. 3. The active matrix display device according to claim 1, wherein said electro-optical element is a liquid crystal cell. 4. The active matrix display device according to claim 1, wherein said electro-optical element is an electroluminescent element. 5. A first circuit for handling small-amplitude signals and a second circuit for handling power supply voltage, together with a display area in which pixels having electro-optical elements are arranged in a matrix, are integrated on the same substrate. At least one of the first and second circuits is formed of a thin film transistor having a dual gate structure having a pair of gates arranged and connected to each other with a channel interposed therebetween. An active matrix display device characterized by the above-mentioned. 6. The active matrix display device according to claim 5, wherein said first circuit is a circuit for receiving a data signal, a master clock signal or a synchronization signal from outside. 7. A horizontal drive circuit formed on the same substrate together with the display area section and including a sampling latch circuit for sequentially sampling and latching input image data, wherein the first circuit includes the sampling circuit. The active matrix type display device according to claim 5, wherein the active matrix type display device is a differential circuit constituting a latch circuit. 8. The active matrix display device according to claim 5, wherein said second circuit is a power supply voltage conversion circuit for converting a single DC voltage into a plurality of DC voltages having different voltage values. . 9. A sampling latch circuit formed on the same substrate together with the display area section and sequentially sampling and latching input image data, and a line-sequentialization latch circuit for line-sequencing each latch data of the sampling latch circuit. And a horizontal drive circuit including a reference voltage selection type DA conversion circuit for converting the digital image data line-sequentialized by the line-sequentialization latch circuit into an analog image signal. 6. The active matrix type display device according to claim 5, wherein the active matrix type display device is a reference voltage generation circuit for generating a plurality of reference voltages used in a selective DA conversion circuit. 10. The active matrix type display device according to claim 5, wherein said electro-optical element is a liquid crystal cell. 11. The counter electrode voltage generation circuit formed on the same substrate together with the display area section and generating a voltage to be applied to a counter electrode of the liquid crystal cell. Item 11. An active matrix display device according to item 10. 12. The active matrix display device according to claim 5, wherein said electro-optical element is an electroluminescence element. 13. A display circuit comprising: a display area including pixels each having an electro-optical element arranged in a matrix; and a transistor circuit including a pair of transistors formed on the same substrate. A mobile terminal, wherein the transistor circuit uses an active matrix display device formed using a thin film transistor with a dual-gate structure having a pair of gates arranged and connected to each other with a channel interposed therebetween. 14. The portable terminal according to claim 13, wherein said active matrix type display device is a liquid crystal display device using a liquid crystal cell as said electro-optical element. 15. The portable terminal according to claim 14, wherein the active matrix display device is an electroluminescence display device using an electroluminescence element as the electro-optical element. 16. A first circuit for handling small-amplitude signals and a second circuit for handling power supply voltage are the same as a display area together with a display area in which pixels having electro-optical elements are arranged in a matrix. At least one of the first and second circuits is formed integrally on a substrate, and is formed of a thin film transistor having a dual gate structure having a pair of gates arranged and connected to each other with a channel interposed therebetween. A portable terminal using an active matrix display device according to claim 1. 17. The mobile terminal according to claim 16, wherein the active matrix display device is a liquid crystal display device using a liquid crystal cell as the electro-optical element. 18. The portable terminal according to claim 16, wherein the active matrix display device is an electroluminescent display device using an electroluminescent element as the electro-optical element.