JP2002175049A - Active matrix display and portable terminal using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display which can reduce power consumption of the system as a whole, and to provide a portable terminal which uses it. SOLUTION: A power circuit, composed of a charge pump type source voltage converting circuit stops supplying switching pulses, by inhibiting clock pulses generated by a pulse generation source 32 from passing through by an AND circuit 31, according to control pulses supplied from a partial mode control circuit 16' in power-saving mode and then stops the pumping operation of a charge pump circuit in large part of a non-display area period, thereby lowering the current supply capability of the power circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device and a portable terminal using the same, and more particularly, to an active matrix display device having a power supply circuit for converting a single DC voltage into a plurality of types of DC voltages having different voltage values. The present invention relates to a matrix type display device and a mobile terminal using the same for a display unit.

[0002]

2. Description of the Related Art In recent years, portable telephones and PDAs (Personal Digital
gital Assistants) and other mobile terminals are remarkable. One of the factors behind the rapid spread of these mobile devices is that
There is a liquid crystal display device mounted as the output display unit. The reason is that the liquid crystal display device has a characteristic that does not require power for driving in principle, and is a display device with low power consumption.

[0003] With the rapid spread of these portable terminals, further reduction in power consumption of the display device is required, and various power saving technologies have been proposed in response thereto. A representative one of them is a partial screen display mode (partial mode) in which information is displayed only on a part of the screen. In the partial screen display mode, low power consumption is realized by stopping unnecessary circuit operations of the drive circuit in the non-display area period.

In a portable terminal, a battery having a single power supply voltage is used as a power supply. On the other hand, in a liquid crystal display device, different DC voltages are used in a logic part and an analog part in a horizontal drive circuit that drives pixels arranged in a matrix, and in a vertical drive circuit that writes information to a pixel, a horizontal drive circuit is used. A DC voltage having an absolute value larger than that on the side is used. Therefore, a liquid crystal display device mounted on a portable terminal needs a power supply voltage conversion circuit (DC-DC converter) for converting a single DC power supply voltage into a plurality of types of DC voltages having different voltage values as a power supply circuit. .

[0005]

The power supply circuit for the drive circuit generally consumes a certain amount of power by itself irrespective of the load current. Therefore, even if the mode shifts to a power saving mode such as a partial screen display mode, and the current to be supplied to the load is reduced due to the stoppage of the operation of some drive circuits, the power consumption of the power supply circuit does not change. Absent. That is, in the conventional display device, when the power saving mode is set, power consumption is reduced on the drive circuit side, but power consumption is not reduced on the power supply circuit at all.

Accordingly, the present invention is to provide an active matrix type display device capable of reducing the power consumption of the entire system by reducing the power consumption also on the power supply circuit side, and a portable terminal using the same. Aim.

[0007]

In order to achieve the above object, according to the present invention, there is provided a display area in which pixels having electro-optical elements are arranged in a matrix, and each pixel in the display area is divided into rows. And a horizontal drive circuit for supplying an image signal to each pixel in a row selected by the vertical drive circuit. Of the power supply circuit, which is converted into a plurality of different types of DC voltages and supplied to at least the vertical drive circuit and the horizontal drive circuit, in a power saving mode. And this active matrix type display device,
Used as a display unit of a portable terminal.

In the active matrix type display device having the above configuration or a portable terminal using the same, in the power saving mode, a part of the circuit operation is stopped in the drive circuit system, so that the circuit portion where the circuit operation is stopped is originally stopped. Power consumption can be reduced by the amount of power consumed. At this time, by reducing the current supply capability of the power supply circuit, unnecessary through current flowing through the power supply circuit is suppressed, so that the power consumption can also be reduced, and as a whole, the power consumption of the entire system can be further reduced. I can do it.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention. Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

In FIG. 1, a pair of upper and lower H drivers (horizontal drive circuits) 13U are provided on a transparent insulating substrate, for example, a glass substrate 11, together with a display area 12 in which a large number of pixels including liquid crystal cells are arranged in a matrix. , 13D and a V driver (vertical drive circuit) 14, a power supply circuit 15 and a power saving mode control circuit 16 are further mounted. The glass substrate 11 includes a first substrate on which a large number of pixel circuits including active elements (for example, transistors) are arranged in a matrix, and a second substrate arranged to face the first substrate with a predetermined gap. And a substrate. Then, a liquid crystal is sealed between the first and second substrates.

FIG. 2 shows an example of a specific configuration of the display area section 12. Here, for simplification of the drawing, a case of a pixel array of 3 rows (n-1 row to n + 1 row) and 4 columns (m-2 column to m + 1 column) is taken as an example. In FIG. 2, vertical scanning lines...
−1, 21n, 21n + 1,..., And data lines.
, 2m-2, 22m-1, 22m, 22m + 1,... Are wired in a matrix, and the intersection of the unit pixels 2
3 are arranged.

The unit pixel 23 has a configuration including a thin film transistor TFT as a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC
Means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed opposite to the pixel electrode.

In the thin film transistor TFT, the gate electrodes have vertical scanning lines..., 21n-1, 21, n, 21n + 1,
, And the source electrode is connected to the data line.
2, 22m-1, 22m, 22m + 1,... In the liquid crystal cell LC, the pixel electrode is a thin film transistor T
The counter electrode is connected to the common line 24 and the drain electrode of the FT is connected. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 24. A predetermined DC voltage is applied to the common line 24 as a common voltage Vcom.

Vertical scanning lines..., 21n-1, 21n,
21n + 1 are connected to the V driver 14 shown in FIG.
Is connected to each output terminal of the corresponding row of. The V driver 14 is configured by, for example, a shift register,
A vertical selection pulse is sequentially generated in synchronization with a vertical transfer clock VCK (not shown) to generate vertical scanning lines.
, 21n + 1, 21n + 1,... To perform vertical scanning.

On the other hand, in the display area section 12, for example, odd-numbered data lines..., 22m-1, 22m +
, 22m are connected to the respective output ends of the corresponding columns of the H driver 13U shown in FIG.
Each of the other ends of −2, 22 m,.
D is connected to each output terminal of the corresponding column. FIG. 3 shows an example of a specific configuration of the H drivers 13U and 13D.

As shown in FIG. 3, the H driver 13U includes:
The configuration includes a shift register 25U, a sampling latch circuit (data signal input circuit) 26U, a line sequential latch circuit 27U, and a DA conversion circuit 28U. The shift register 25U performs horizontal scanning by sequentially outputting a shift pulse from each transfer stage in synchronization with a horizontal transfer clock HCK (not shown). The sampling latch circuit 26U responds to a shift pulse given from the shift register 25U, and samples and latches input digital image data of predetermined bits in a dot-sequential manner.

The line-sequentializing latch circuit 27U re-latches the digital image data latched in the dot-sequential manner by the sampling latch circuit 26U line by line, thereby line-sequentially converting the digital image data for one line. Output to The DA conversion circuit 28U has, for example, a circuit configuration of a reference voltage selection type, and has a line-sequential latch circuit 27.
The digital image data for one line output from U is converted into an analog image signal to convert the digital image data into an analog image signal.
, 22m-2, 22m-1, 22m,
22m + 1, ....

The lower H driver 13D also has a shift register 25 just like the upper H driver 13U.
D, a sampling latch circuit 26D, a line sequential latch circuit 27D, and a DA conversion circuit 28D. In the liquid crystal display device according to this example, the H drivers 13U and 13D are arranged above and below the display area unit 12, but the present invention is not limited to this. It is also possible to adopt a configuration.

As is apparent from FIGS. 1 and 3, the power supply circuit 15 and the power saving mode control circuit 16 also include the H drivers 13U and 13D and the V driver 1
Similarly to 4, the display area 12 and the display area 12 are mounted on the same glass substrate 11. Here, for example, the display area unit 12
In the case of a liquid crystal display device adopting a configuration in which H drivers 13U and 13D are arranged above and below, a power supply circuit 15 and a power supply circuit 15 are provided in a frame area (a peripheral area of the display area section 12) on a side where the H drivers 13U and 13D are not mounted. It is preferable to mount the timing control circuit 16.

The reason is that the H drivers 13U, 13D
As described above, since the number of components is larger than that of the V driver 14 and the circuit area is often very large as described above, the H driver 13U, 13D is mounted in the frame area on the side where the H driver 13U, 13D is not mounted. The power supply circuit 15 and the power-saving mode control circuit 16 are connected to the same glass substrate 11 as the display area 12 without reducing the effective screen ratio (the area ratio of the effective area 12 to the glass substrate 11).
This is because it can be mounted on top.

In the liquid crystal display device according to the present embodiment, the V driver 14 is mounted on one side of the frame area of the side where the H drivers 13U and 13D are not mounted. Power supply circuit 1 in the frame area
5 and a power saving mode control circuit 16.

When the power supply circuit 15 is mounted, a thin film transistor TFT is used as each pixel transistor of the display area section 12, so that a thin film transistor is used as a transistor constituting the power supply circuit 15,
At least these transistor circuits are connected to the display area 12
By using the same process as described above, the production can be facilitated and can be realized at low cost.

At present, integration of thin film transistors has been facilitated with recent improvements in performance and reduction in power consumption. Therefore, by integrally forming the power supply circuit 15, particularly at least the transistor circuit, on the same glass substrate 11 using the same thin film transistor as the pixel transistor in the display area section 12 in the same process, the manufacturing process is simplified. The cost can be reduced, and the thickness and the size can be reduced with the integration.

The power supply circuit 15 is composed of, for example, a charge pump type power supply voltage conversion circuit (DC-DC converter), and converts a single externally supplied DC power supply voltage VCC into a plurality of types of DC voltages having different voltage values. These DC voltages are applied to H drivers 13U and 13D, V driver 14, and the like. When the power saving mode is designated from the outside, the power saving mode control circuit 16 controls the H driver 13U,
Control is performed to reduce the power supply current of the 13D or V driver 14 and the current supply capability of the power supply circuit 15.

Here, in the active matrix type liquid crystal display device, the power saving mode is, for example, a partial screen display mode (partial mode) in which information is displayed only in a part of the display area section 12 or a normal mode. R
A two-gradation display mode in which 260,000 colors are displayed with 6 bits each of (red), G (green), and B (blue), while 8 colors are displayed with 1 bit of RGB.

Among these power saving modes, for example, in a partial screen display mode, specific information is displayed only on a part of the display area section 12, for example, only on the upper portion, while white or white is displayed on a non-display area. Black display will be performed. In the non-display area, white or black information only needs to be displayed at all times, and it is not necessary to rewrite information by the H driver. Therefore, by stopping the H driver, the power originally consumed by the H driver can be reduced. Only low power consumption can be achieved.

As described above, in the active matrix type liquid crystal display device, in the power saving mode, the operation of the H driver is stopped in the non-display area to reduce the power consumption and decrease the current supply capability of the power supply circuit 15. By doing so, the power consumption of the power supply circuit 15 can be reduced, so that the power consumption of the entire display device can be further reduced. In addition, the DC-DC conversion efficiency is defined as power consumption at load / total power consumption, and since total power consumption = power consumption at load + power consumption at this circuit, the power consumption at this circuit is The conversion efficiency can be improved by the reduction.

Next, a specific configuration of the power supply circuit 15 will be described. Here, for example, a charge pump type power supply voltage conversion circuit is used as the power supply circuit 15, and a partial screen display mode (partial mode) is used as a power saving mode.
Is set as an example.

FIGS. 4A and 4B are circuit diagrams showing a first configuration example of a charge pump type power supply voltage conversion circuit. FIG. 4A shows a negative voltage generation type, and FIG. 4B shows a step-up type. In FIG. 4, the partial mode control circuit 16 'corresponds to the power saving mode control circuit 16 in FIGS.

In FIG. 4A, the partial mode control circuit 16 'outputs an "H" level (high level) control pulse in the normal mode, and the power saving mode, that is, the partial screen display mode is set. At this time, an "L" level (low level) control pulse is output during the screen non-display area period based on the externally given information on the position of the partial display area and the number of lines. This control pulse is given by AN
This is one input of the D circuit 31. As the other input of the AND circuit 31, a clock pulse generated by the pulse generation source 32 is provided.

On the other hand, a PchMOS transistor Qp11 and an NchMOS transistor Qn11 are connected in series between a power supply for supplying a single DC power supply voltage VCC and a ground (GND), and each gate is connected in common.
The MOS inverter 33 is constituted. An AND circuit 32 is connected to a common connection point of the gates of the CMOS inverter 33.
The clock pulse from the pulse generation source 32 that has passed through is applied as a switching pulse.

One end of a capacitor C11 is connected to a common drain connection point (node B) of the CMOS inverter 33. The other end of the capacitor C11 is connected to a switch element, for example, the drain of the NchMOS transistor Qn12 and the source of the PMOS transistor Qp12. NchMOS transistor Qn12
A load capacitor C12
Is connected.

One end of a capacitor C13 is connected to a common connection point of the gates of the CMOS inverter 33. The other end of the capacitor C13 is connected to the anode of the diode D11. The cathode of the diode D11 is grounded. The other end of the capacitor C13 further includes N
The gates of the chMOS transistor Qn12 and the PchMOS transistor Qp12 are connected to each other.
The drain of PchMOS transistor Qp12 is grounded.

As described above, a power supply voltage conversion circuit having a charge pump circuit configuration for generating a negative voltage -VCC as an output voltage Vout based on a single DC power supply voltage VCC externally applied is provided.

Next, the circuit operation of the negative voltage generation type charge pump type power supply voltage conversion circuit having the above configuration will be described with reference to the timing chart of FIG. Note that the timing chart of FIG.
Signal waveforms A to E at nodes A to E in the circuit of FIG.
Is shown.

First, in the normal mode, an "H" level control pulse is output from the partial mode control circuit 16 ', so that the clock pulse generated by the pulse generation source 32 passes through the AND circuit 31 and switches the switching pulse. At the gate common connection point of the CMOS inverter 33. At this time, the output potential of the capacitor C13 based on the switching pulse, that is, the potential of the node D is clamped by the diode D11.

When the switching pulse is at "L" level (0 V), the P-channel MOS transistor Qp1
1 and Qp12 are turned on, so that the capacitor C11
Is charged. At this time, the NchMOS transistor Qn
Since 11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the NchMOS transistor Qn1
1 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V).
It becomes CC level. The potential of this node C remains unchanged for Nch
Output voltage Vout through MOS transistor Qn12
(= −VCC).

Next, when the partial mode (partial screen display mode) is set, the partial mode control circuit 16 'displays the screen based on the externally given designation information of the position of the partial display area and the number of lines. An “L” level control pulse is output during the non-display area period. Then
The AND circuit 31 prohibits the passage of the clock pulse generated by the pulse generation source 32 by the "L" level control pulse. Thus, the supply of the switching pulse to the charge pump circuit is stopped.

When the switching pulse is not supplied, the pumping operation of the charge pump circuit stops.
At this time, the current supply capacity (current capacity) of the charge pump circuit, that is, the present power supply voltage conversion circuit is reduced to almost zero. That is, since the current supply capability of the charge pump circuit is inversely proportional to the frequency of the switching pulse and the capacitance of the capacitor C11, the supply of the switching pulse is stopped. It becomes 0.

Here, the period during which the current supply capability (current capacity) of the present power supply voltage conversion circuit is reduced should be as long as possible in order to reduce power consumption. It is preferable to set it to 1/2 or more.

As described above, in the power supply voltage conversion circuit using the charge pump circuit, the pumping operation of the charge pump circuit is stopped during most of the non-display region period, and the current supply capability of the power supply voltage conversion circuit is reduced. By reducing the power consumption, it is possible to suppress the flow of unnecessary through current in the charge pump circuit in the non-display period in which the current consumption on the driver system side is small, so that the power consumption in the power supply voltage conversion circuit can be reduced. Further, the reduction in power consumption in the power supply voltage conversion circuit can improve the DC-DC conversion efficiency.

The booster DD converter shown in FIG. 4B has the same basic circuit configuration and operation. That is, in FIG. 4B, the switching transistors (MOS transistors Qp13, Qn1)
3) is the MOS transistor Qn1 in the circuit of FIG.
2, Qp12 and diode D
11 is connected between the other end of the capacitor C11 and the power supply (VCC), and this point is different only in configuration from the circuit of FIG.

In terms of circuit operation, basically, FIG.
This is exactly the same as the circuit of FIG. The difference is that the output voltage Vout is a voltage value 2 × VC that is twice the power supply voltage VCC.
The only point at which C is derived. FIG.
Signal waveforms A to E at nodes A to E in the circuit of FIG.
3 shows a timing chart.

FIGS. 6A and 6B are circuit diagrams showing a second configuration example of the charge pump type power supply voltage conversion circuit. FIG. 6A shows a negative voltage generation type, and FIG. 6B shows a boost type. In the drawing, the same parts as those in FIG. 4 are denoted by the same reference numerals. The power supply voltage conversion circuit according to this configuration example has a configuration in which a VCO (voltage controlled oscillator) 34 is provided instead of the AND circuit 31 and the pulse generation source 32 in FIG. The configuration is exactly the same.

In the normal mode, the VCO 34 receives a control voltage of, for example, "H" level from the partial mode control circuit 16 ', generates a first clock pulse of a predetermined frequency based on the control voltage, and Sometimes, for example, a control voltage of an “L” level is supplied from the partial mode control circuit 16 ′, and a second clock pulse having a lower frequency than the first clock pulse is generated based on the control voltage.
These first and second clock pulses are applied to the gate common connection point of the CMOS inverter 33 as switching pulses.

Next, the circuit operation of the negative voltage generation type charge pump type power supply voltage conversion circuit having the above configuration will be described with reference to the timing chart of FIG. Note that the timing chart of FIG.
Signal waveforms A to E at nodes A to E in the circuit of FIG.
Is shown.

First, in the normal mode, the VCO 34 generates a first clock pulse of a predetermined frequency by receiving an "H" level control voltage from the partial mode control circuit 16 '. The first clock pulse is used as a switching pulse as the CMOS inverter 33.
At the gate common connection point. At this time, the output potential of the capacitor C13 based on the switching pulse, that is, the potential of the node D is clamped by the diode D11.

When the switching pulse is at "L" level (0 V), the P-channel MOS transistor Qp1
1 and Qp12 are turned on, so that the capacitor C11
Is charged. At this time, the NchMOS transistor Qn
Since 11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the NchMOS transistor Qn1
1 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V).
It becomes CC level. The potential of this node C remains unchanged for Nch
Output voltage Vout through MOS transistor Qn12
(= −VCC).

Next, when the partial mode (partial screen display mode) is set, the partial mode control circuit 16 'displays the screen based on the externally given designation information of the position of the partial display area and the number of lines. An “L” level control voltage is output during the non-display area period. This "L"
The level control voltage is applied, so that the VCO 34
Generates a second clock pulse having a lower frequency than the first clock pulse in the normal mode. This second clock pulse is given to the gate common connection point of the CMOS inverter 33 as a switching pulse.

Thereafter, according to the same operating principle as in the normal mode, a DC-DC conversion operation is performed by a pumping operation in the charge pump circuit based on the second clock pulse, and a negative voltage -VCC is derived as the output voltage Vout. You. At this time, since the frequency of the switching pulse is lower than that in the normal mode, the current supply capability (current capacity) of the power supply voltage conversion circuit is reduced. That is, as described above, since the current supply capability of the charge pump circuit is inversely proportional to the switching pulse frequency and the capacitance of the capacitor C11, the current supply capability decreases as the switching pulse frequency decreases.

As described above, in the power supply voltage conversion circuit using the charge pump circuit, the VCO 34 is used as the source of the switching pulse, and the frequency of the switching pulse is changed from that in the normal mode in most of the non-display area period. By lowering the power supply voltage conversion circuit to lower the current supply capability, it is possible to suppress the flow of unnecessary through current in the charge pump circuit during the non-display period in which the current consumption on the driver system side is small. The power consumption of the power supply voltage conversion circuit can be reduced, and the conversion efficiency can be improved by reducing the power consumption of the conversion circuit.

The booster DD converter shown in FIG. 6B has the same basic circuit configuration and circuit operation. That is, in FIG. 6B, the switching transistors (MOS transistors Qp13, Qn1)
3) is the MOS transistor Qn1 in the circuit of FIG.
2, Qp12 and diode D
11 is connected between the other end of the capacitor C11 and the power supply (VCC), and this point is different only in configuration from the circuit of FIG.

In terms of circuit operation, basically, FIG.
This is exactly the same as the circuit of FIG. The difference is that the output voltage Vout is a voltage value 2 × VC that is twice the power supply voltage VCC.
The only point at which C is derived. FIG. 7B shows FIG.
Signal waveforms A to E at nodes A to E in the circuit of FIG.
3 shows a timing chart.

The circuit configuration of the power supply voltage conversion circuit of the charge pump type according to the first and second configuration examples described above is merely an example, and the circuit configuration of the charge pump circuit can be variously modified. The present invention is not limited to the circuit configuration example.

In the above embodiment, the case where the present invention is applied to an active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and the electroluminescent (EL) element may be replaced with the electro-optical element of each pixel. The present invention can be similarly applied to other active matrix display devices such as an EL display device used as a display device.

Further, the active matrix type display device according to the present invention is not only used as a display for OA equipment such as a personal computer and a word processor, but also as a display for a television receiver. It is suitable for use as a display unit of a portable terminal such as a mobile phone or a PDA.

FIG. 8 is an external view schematically showing the configuration of a portable terminal to which the present invention is applied, for example, a portable telephone.

The mobile phone according to the present embodiment has a configuration in which a speaker section 42, a display section 43, an operation section 44, and a microphone section 45 are arranged in order from the upper side on the front side of an apparatus housing 41. In the mobile phone having such a configuration, the display unit 4
For example, a liquid crystal display device 3 is used as the liquid crystal display device 3, and the active matrix liquid crystal display device according to the above-described embodiment is used as the liquid crystal display device.

As described above, in a portable terminal such as a portable telephone, by using the active matrix type liquid crystal display device according to the above-described embodiment as the display section 43,
Since the liquid crystal display device can reduce the power consumption of the entire device, the power consumption of the terminal body can be reduced.

[0060]

As described above, according to the present invention,
In an active matrix display device or a portable terminal using the same, the power consumption of the power supply circuit can be reduced by reducing the current supply capability of the drive circuit in the power saving mode, so that the power consumption in the power saving mode is further reduced. Is possible.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a display area of a liquid crystal display device.

FIG. 3 is a block diagram illustrating an example of a specific configuration of an H driver.

FIG. 4 is a circuit diagram showing a first configuration example of a charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

5A and 5B are timing charts for explaining a circuit operation of the power supply voltage conversion circuit according to the first configuration example, where FIG. 5A shows a case of a negative voltage generation type and FIG. ing.

FIG. 6 is a circuit diagram showing a second configuration example of the charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

FIGS. 7A and 7B are timing charts for explaining a circuit operation of the power supply voltage conversion circuit according to the second configuration example, where FIG. 7A shows a case of a negative voltage generation type and FIG. ing.

FIG. 8 is an external view schematically showing a configuration of a mobile phone which is a mobile terminal according to the present invention.

[Explanation of symbols]

11: glass substrate, 12: display area, 13U, 13
D: H driver (horizontal drive circuit), 14: V driver (vertical drive circuit), 15: power supply circuit, 16: power saving mode control circuit, 16 ': partial mode control circuit, 23: unit pixel, 31: AND circuit , 32
... Pulse generation source, 33 ... CMOS inverter, 34 ... V
CO (voltage controlled oscillator)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680T 3/30 3/30 J F-term (Reference) 2H093 NA46 NC05 NC06 NC10 NC12 NC22 NC24 NC26 NC34 NC59 ND39 5C006 AF68 AF69 BB16 BC06 BF42 BF46 EC13 FA47 5C080 AA10 BB05 DD26 FF07 JJ02 JJ03 JJ04 JJ06 KK07

Claims (11)

[Claims] 1. A display area in which pixels having an electro-optical element are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area in a row unit, and a vertical drive circuit selected by the vertical drive circuit. A horizontal drive circuit for supplying an image signal to each pixel in a row, and converting a single DC voltage into a plurality of types of DC voltages having different voltage values and applying the converted voltage to at least the vertical drive circuit and the horizontal drive circuit, An active matrix display device comprising: a power supply circuit whose current supply capability is reduced in a power saving mode. 2. The power supply circuit is a charge pump type power supply voltage conversion circuit, and stops input of a clock signal serving as a reference of a switching operation of the power supply voltage conversion circuit or reduces a frequency of the clock signal in a power saving mode. 2. The active matrix display device according to claim 1, wherein the active matrix display device is lowered. 3. The power saving mode is a partial screen display mode in which information is displayed only in a partial area of the display area, and the power supply circuit has a reduced current supply capability during a screen non-display period. 2. The active matrix display device according to claim 1, wherein: 4. The power supply circuit is a charge pump type power supply voltage conversion circuit, and stops input of a clock signal serving as a reference for a switching operation of the power supply voltage conversion circuit or reduces a frequency of the clock signal in a power saving mode. 4. The active matrix display device according to claim 3, wherein the active matrix type display device is lowered. 5. The active matrix type display device according to claim 1, wherein said electro-optical element is a liquid crystal cell. 6. The active matrix display device according to claim 1, wherein said electro-optical element is an electroluminescence element. 7. In each pixel of the display area, an active element for driving the electro-optical element is formed of a thin film transistor, and at least a transistor circuit forming the power supply circuit is formed on the same substrate as the display area by the thin film transistor. The active matrix display device according to claim 1, wherein the active matrix display device is formed integrally. 8. A display area as a display section, in which pixels having electro-optical elements are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area in a row unit, and the vertical drive circuit. A horizontal drive circuit for supplying an image signal to each pixel of the row selected by the above, and converting a single DC voltage into a plurality of types of DC voltages having different voltage values to at least the vertical drive circuit and the horizontal drive circuit And a power supply circuit having a power supply circuit whose current supply capability is reduced in a power saving mode. 9. The portable terminal according to claim 8, wherein the power supply circuit is a charge pump type power supply voltage conversion circuit. 10. The mobile terminal according to claim 8, wherein the active matrix display device is a liquid crystal display device using a liquid crystal cell as the electro-optical element. 11. The mobile terminal according to claim 8, wherein the active matrix display device is an electroluminescence display device using an electroluminescence element as the electro-optical element.