JP2002171282A - Method and device for absorbing delay fluctuation at the packet arrival in packet communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress incompatibility in hearing which occurs in the sound output reproduced from an IP packet. SOLUTION: If a packet 10 is lost, a write control part 2 keeps a memory area in a dual port memory 4, where data of this packet 10 should have been written, empty and writes data of the next arriving packet 10 in a memory area following this empty area. When finding the existence of the empty area at the time of read, a memory table management part 3 transmits a report, which indicates that data in the dual port memory 4 is ineffective, to a data insertion part 6 which inserts data to an output packet 24, and the data insertion part 6 inserts data written in the position just before the empty area to the data part of the output packet 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for absorbing delay fluctuation when a packet arrives in packet communication, and more particularly to an RTP (Real-time Transport Protocol).
l) In the case of periodically outputting an input packet having a sequence number provided in, for example, while absorbing the delay fluctuation (variation in the time interval at which the packet arrives) at the time of arrival of the input packet, which occurs in the packet communication, The present invention relates to an apparatus and method for absorbing delay fluctuation at the time of packet arrival in packet communication for reducing the influence on output packets even when packet loss due to delay fluctuation occurs.

[0002]

2. Description of the Related Art At present, voice data is transferred to IP (Internet Pro
IP telephone services for packetizing and transmitting using a data communication network are becoming widespread. In the telephone service, since real-time communication is required, it is required that the delay time of the IP packet is small and that the delay time does not fluctuate.

[0003] However, when voice data is converted into IP packets and transmitted using a data communication network, the IP packet is generally transmitted to the final destination due to a change in congestion state in the network or a variation in delay time in the relay device. Fluctuation occurs in the time to reach the ground. Further, if the delay fluctuation is too large, there is a possibility that packet loss due to overflow of the reception buffer of the IP packet or the like may occur.

Conventionally, as a method for solving this problem, an ATM (Asyncronous Transfer Mode) using a FIFO (First-In First-Out) memory is disclosed in Japanese Patent Laid-Open No. 4-179341. ) A method of absorbing a delay fluctuation of a cell has been proposed.

In this method, when writing a reception cell into the FIFO memory, the counter content of the decoding clock signal of the timer is inserted into the header as the cell reception time, and the first reception cell arrives after the delay fluctuation absorption time. FIF
After that, when the difference between the cell transmission time and the cell reception time added to the header of the received cell read from the FIFO memory is smaller than the minimum delay time, the reference point is changed. And F
It controls the reading of the IFO memory.

Since the delay fluctuation of a received cell in an ATM multiplex transmission system has a distribution characteristic concentrated near a reference point of a minimum delay time, the reference point is quickly and automatically adjusted to an optimum position, and a reproduced voice in the meantime is adjusted. Since the output is not interrupted, it is possible to prevent the sound quality from deteriorating.

[0007]

However, in the above-mentioned conventional example, measures are taken against fluctuations in arrival time, but there is a problem that measures against cell loss are not taken.

That is, even if the above-described delay fluctuation absorption scheme for ATM cells is applied to an IP packet, if an IP packet loss occurs, the loss IP
The voice data in the packet remains missing,
The quality of the reproduced audio output may be degraded.

Accordingly, an object of the present invention is to provide a state in which voice data in a lost IP packet remains lost even when an IP packet input to the delay fluctuation absorbing device is lost due to an increase in delay fluctuation. It is an object of the present invention to prevent a sense of incongruity in an audio output reproduced from an IP packet output from a delay fluctuation absorbing device.

[0010]

In order to achieve the above object, a delay fluctuation absorbing apparatus according to the present invention generates a write pointer value using a sequence number of an input packet so that a packet can be transmitted before arrival. Is lost, the pointer value of the lost packet is skipped, and the packet data is written to the dual port memory of the next pointer value. At the time of a read operation periodically performed in the order of the pointer values, if there is no valid write data in the corresponding pointer value of the dual port memory due to packet loss, the memory table management is performed via the read control unit. The section notifies the data insertion section of the data invalidation. Further, the data insertion unit repeatedly inserts, into the data portion of the packet output from the delay fluctuation absorbing device, the audio data written in the pointer value immediately before the jump was performed during writing,
Minimize the effects of packet loss.

That is, the delay fluctuation absorbing apparatus of the present invention uses a sequence number of a packet to determine a memory area to be written in a dual port memory, and a sequence check means. A write control unit that leaves a memory area in the dual port memory where data is to be written as a blank area, and writes data of a packet that has arrived next in a memory area following the blank area; A memory table management unit for transmitting a data invalidation notification by the memory table management unit of the dual port memory to a data insertion unit that inserts data into an output packet when the blank area exists; The data insertion unit that has received the Inserts the data written to the position immediately before the pass, and a data insertion unit.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an apparatus and a method for absorbing delay fluctuation upon arrival of a packet in packet communication according to the present invention will be described in detail with reference to the drawings.

First, the overall configuration of the delay fluctuation absorbing device in packet voice communication will be described with reference to FIG.

In FIG. 1, a sequence check unit 1
Generates the write pointer control signal 11 from the sequence number information in the header part of the input packet 10 and sends it out together with the packet 12.

The write control unit 2 generates a write address signal 13 using the write pointer control signal 11, and uses the write control signal 15 (generally, a chip select signal and a write enable signal) to input a packet 10 (= Write data 1 stored in packet 12)
4 is written to the dual port memory 4. Further, it notifies the memory table management unit 3 of the write pointer control signal 11a.

The memory table management unit 3 divides the dual port memory 4 into packet units, and assigns pointer numbers (1 to n) to each of the divided units. Further, the main table management unit 3 has a data management table indicating whether or not there is valid data of the input packet 10 in the memory at the position corresponding to the pointer number. This data management table includes a write pointer control signal 1 that is notified each time a write / read operation to / from the dual port memory 4 is performed.
1a and the read pointer control signal 19.

For example, when the memory table management unit 3 receives the data write completion signal (11a-2 in FIG. 3 described later) included in the write pointer control signal 11a, the memory table management unit 3 sets the data management table of the target pointer to "valid data exists".
Set as In addition, a data read completion signal included in the read pointer control signal 19 (19-FIG.
When 2) is received, the data management table of the target pointer is set to “no valid data”.

Next, a write operation to the dual port memory 4 will be described. Dual port memory 4
It has a sufficient packet storage capacity to absorb fluctuations of the input packet 10. Here, about 200 milliseconds are required as a characteristic of ordinary fluctuation absorption.

In the sequence check section 1, a write pointer value is created from the write pointer control signal 11. The initial value of the write pointer value is “1”, and by adding “the difference between the sequence numbers of two consecutive input packet data” to the initial value, the write pointer value is updated for each write operation.

For example, if the write pointer value of the packet having the sequence number "124" is "3", and if the sequence number of the next packet is "125", the difference between the sequence numbers is "1". The write pointer value is updated to "4".

The packet having the sequence number "125" is lost, and the sequence number of the next packet is "12".
If it is "6", the difference between the sequence numbers is "2", so the write pointer value is updated to "5".

A write pointer control signal 11 newly created based on the updated write pointer value is transmitted to the write control unit 2. The write control unit 2 receives the write address signal 1 from the write pointer control signal 11.
3 and the write control signal 15 are generated, and the write data 1
4 is written to the dual port memory 4. By outputting the write pointer control signal 11a to the memory table management unit 3 after the completion of the writing, the memory table management unit 3
To update.

Next, a read operation from the dual port memory 4 by the read control unit 5 will be described. The read control unit 5 first reads the read pointer value using the read pointer control signal 19
Notify. Here, the read pointer value is a pointer to start reading, and its initial value is “1”.

The read control unit 5 performs control for reading sequentially from the initial value of the read pointer value. For this purpose, first, the read pointer value is sequentially changed from the initial value, and a read address signal 16 and a read control signal 18 corresponding to each read pointer value are generated.
Output to the dual port memory 4.

The memory table management unit 3 refers to the management table of the notified read pointer value and analyzes whether there is valid data in the internal memory of the dual port memory 4 corresponding to the read pointer value. Then, the result is notified to the read control unit 5 using the data validity identification signal 21.

If there is no valid data in the dual port memory 4 at this time, it is determined that the read pointer value has caught up with the write pointer value.
The read control unit 5 is notified of the read stop signal 20.
Also, updating of the read pointer value is stopped.

Since there is no valid data in the initial state before the valid data is written, the data read from the dual port memory 4 is stopped by the read stop signal 20 and is in a standby state. When the writing of the first packet to the dual port memory 4 is completed and the read stop signal 20 is no longer input to the read control unit 5, reading of the read data 17 from the dual port memory 4 is started.

When there is no valid data in the memory area of the read pointer value due to a packet loss or the like, the read control unit 5 is notified to the read control unit 5 using the data validity identification signal 21 that the read data 17 is invalid. I do.

Further, the read control unit 5 analyzes whether or not valid read data 17 is stored in the output packet 23 by using the data validity identification signal 21.
The data insertion unit 6 is notified by the data validity identification signal 22.

The data insertion section 6 stores data when the data validity identification signal 22 indicates “valid data exists”, assembles a packet using the valid data, and outputs the packet as a packet 24.

On the other hand, if the data validity identification signal 22 indicates “no valid data”, the input packet 2
3 is invalid, so instead of invalid data,
A packet is assembled using the latest valid data already stored, and is retransmitted as a packet 24.

FIG. 2 shows an image of the pointer table in the memory table management unit 3. The pointer table has one register corresponding to each position where the number of data stored in the dual port memory 4 is n. In the example of FIG. 2, the register following the n-th register is the first register, and is circulating. The registers indicated by the write pointer value and the read pointer value are respectively the first registers in the initial state. After the completion of the writing from the initial state, the read operation is started when the write pointer value becomes "1". After the completion of the reading, the read pointer value of the corresponding register is set to "0".

As described above, according to the present invention, the write pointer value is created by using the sequence number of the input packet, so that the pointer of the lost packet is skipped when writing to the dual port memory 4 and the next write pointer value is generated. The data is written to and read periodically according to the order of the read pointer values.

If there is no valid data in the memory of the corresponding read pointer value due to the packet loss, the memory table manager 3 sends “valid data not available” to the data inserter 6 via the read controller 5 to indicate the data validity The notification is made using the identification signal 22. The data insertion unit 6 that has received the notification can minimize the influence of packet loss by repeatedly inserting the latest valid voice data into the output packet.

The data to be written into the dual port memory 4 may be the entire packet data or only the voice data of the payload portion excluding the header portion.

FIG. 3 shows an example of a detailed functional diagram of the memory table management unit 3. The management table corresponding to the write / read pointer value is composed of RS latches 110-112. The state of “output Q =“ 1 ”” in which the RS latches 110 to 112 are set is “valid data exists”
The reset state of “output Q =“ 0 ”” indicates the state of “no valid data”.

Here, the write pointer control signal 11a
Is composed of a write pointer value 11a-1 and a write completion signal 11a-2.

The decoder 100 has a write pointer value 1
1a-1 is decoded, and a "1" signal is output only from the RS latch corresponding to the write pointer value. Then, at the timing when the write completion signal 11a-2 becomes “1”, the output signals from the AND circuits 140 to 142
Output Q of RS latch 110-112 which is a management table
Is set to "1", and the state becomes "valid data exists".

On the other hand, the read pointer control signal 19 is
Read pointer value 19-1 and read completion signal 19-
2.

The decoder 101 has a read pointer value of 1
9-1 is decoded, and RS corresponding to the read pointer is decoded.
The "1" signal is output only from the latch. Then, at the timing when the read completion signal 19-2 becomes "1", AN
The output signals from the RS latches 110 to 112, which are the management tables, are set to “0” by the output signals from the D circuits 150 to 152.
To be in the state of "no valid data".

In addition, all management tables (RS latch 1
By inputting the outputs of the OR circuit 130 to the OR circuit 130, a read stop signal 20 indicating the presence or absence of valid data in all memories is obtained as the output of the OR circuit 130.

Further, all management tables (RS latch 11
0 to 112) and the output of the decoder 101 are individually input to AND circuits 120 to 122,
As the output of each of the AND circuits 120 to 122, the presence or absence of valid data at the pointer position indicated by the read pointer value 19-1 (“1” = valid data exists,
(0 = no valid data) is obtained. By inputting the outputs of the AND circuits 120 to 122 to the OR circuit 131, the data validity identification signal 21 is obtained as the output of the OR circuit 131.

Next, another embodiment of the present invention will be described.

FIG. 4 shows an overall configuration diagram of a delay fluctuation absorbing device according to another embodiment. The difference between this configuration diagram and FIG. 1 which is the first embodiment is that the write inhibition signal 25 is notified from the memory table management unit 3 to the write control unit 2.

FIG. 5 shows an example of a detailed functional diagram of the memory table management unit 3 in the overall configuration diagram of FIG. In the following, only the part (the generation unit of the write inhibition signal 25) added to the memory table management function diagram (FIG. 3) in the first embodiment in FIG. 5 will be described. The operation of the other parts is the same as in FIG.

In FIG. 5, each output of the entire management table (RS latches 110 to 112) and the output of the decoder 100 are individually input to the AND circuits 160 to 162, so that they are output as the outputs of the AND circuits 160 to 162. , A signal indicating the presence or absence of valid data (“1” = valid data present, “0” = valid data not present) at the pointer position indicated by the write pointer value 11a-1 is obtained.
The output of each of the AND circuits 160 to 162 is connected to an OR circuit 17.
By inputting it to 0, a write inhibit signal 25, which is a control signal for inhibiting rewriting of already written data, is obtained as an output of the OR circuit 170.

In FIG. 4, the write control unit 2 to which the write inhibit signal 25 is notified from the memory table management unit 3
Discards the target packet and sets the dual port memory 4
Stop writing data to.

If valid data already exists in the internal memory of the dual port memory 4 corresponding to the write pointer value 11a-1, the write pointer value 1
This indicates that 1a-1 has caught up with the read pointer value 19-1 (= immediately before the buffer overflows) or that a packet with the same sequence number has been sent twice.

In the buffer overflow state,
The packet is discarded one by one by prohibiting the data writing to the dual port memory 4. However, the entire buffer is reset by equivalently reducing the delay amount of the delay fluctuation absorbing device, and all the packets are reset. The operation can be continued with the minimum data discard amount without discarding the packet data.

[0050]

The effect of the present invention is that the influence on the output can be reduced even if a packet is lost. This effect can be realized for the following reasons.

In the dual port memory 4, a write pointer control signal 11 for the memory is generated from the sequence number information of the input packet 10, and the data of the packet is written. Here, when one packet is lost, a memory area for one packet of audio data in which the lost packet was to be written is left empty, and when the next packet arrives, the pointer value of the destination is stored. The packet data is written to the memory area indicated by.

In reading data from the dual port memory 4, reading is normally performed in order according to the pointer value. However, if there is no data in the dual port memory 4 due to packet loss, the memory table management unit 3 notifies the read control unit 5 that the data at the corresponding address in the dual port memory 4 is invalid.

Further, by notifying the data insertion section 6 of the invalidity of the data, the audio data immediately before held by the data insertion section 6 is transmitted again. Since the audio data is analog continuous data, by retransmitting the immediately preceding audio data, it is possible to suppress a sense of discomfort in hearing.

As described above, according to the present invention, since the data of the immediately preceding packet is inserted into the packet loss portion, the influence on the output packet can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram for explaining an embodiment of an apparatus and a method for absorbing delay fluctuation at the time of packet arrival in packet communication according to the present invention.

FIG. 2 is an image diagram of a pointer table.

FIG. 3 is a configuration diagram for explaining details of a function of a memory table management unit;

FIG. 4 is an overall configuration diagram for explaining another embodiment of the present invention.

FIG. 5 is a configuration diagram for describing details of functions of a memory table management unit according to another embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sequence check part 2 Write control part 3 Memory table management part 4 Dual port memory 5 Read control part 6 Data insertion part

Claims (14)

[Claims] 1. A delay fluctuation absorbing method for absorbing delay fluctuation at the time of arrival of a packet in packet communication using a dual port memory, wherein the delay fluctuation absorbing method comprises the steps of: A sequence check step of determining a memory area to be written in the dual port memory, in the event that a packet is lost, leaving the memory area in the dual port memory where the data of the packet was to be written, A step of writing data of the arriving packet into a memory area following the blank area; and, if the blank area is present at the time of reading, a data insertion unit for inserting data into an output packet.
The memory table management unit of the dual port memory transmits a data invalidation notification, and the data insertion unit that receives the invalidation notification, the data written in the data portion of the output packet at the position immediately before the blank area, Inserting a delay fluctuation. 2. A delay fluctuation absorbing device comprising a dual port memory for absorbing delay fluctuation at the time of packet arrival in packet communication, wherein the delay fluctuation absorbing device uses a packet sequence number to generate the dual port memory. Sequence check means for determining a memory area to be written in the dual port memory, when a packet is lost, leaving a memory area in the dual port memory where data of the packet is to be written, Write control means for writing data of the packet arriving at the memory area following the blank area, and a data insertion unit for inserting data into an output packet when the blank area exists at the time of reading.
A memory table management unit of the dual port memory transmits a data invalidation notification, a memory table management unit, and a data insertion unit that receives the invalidation notification writes a data portion of an output packet to a position immediately before the blank area in a data portion of an output packet. And a data insertion means for inserting the inserted data. 3. The delay fluctuation absorbing device according to claim 2, wherein the sequence check means receives an arrival packet, and receives a write pointer control signal indicating a pointer position for writing the arrival packet; A delay fluctuation absorber characterized by being output. 4. The delay fluctuation absorbing apparatus according to claim 3, wherein said sequence check means generates said write pointer control signal from sequence number information of a header part of said packet. Absorber. 5. The delay fluctuation absorbing device according to claim 2, wherein said write control means receives said write pointer control signal and writes an address to which a packet output from said sequence check means is written. An address signal, a write control signal indicating whether or not to write the packet, a write pointer control signal indicating that valid data is present at the pointer position, and write data stored in the packet are output. A delay fluctuation absorber characterized by the above-mentioned. 6. The delay fluctuation absorbing device according to claim 3, wherein the write pointer control signal includes a write pointer value and a write completion signal. Characteristic delay fluctuation absorber. 7. The delay fluctuation absorbing device according to claim 6, wherein the write pointer value is updated by adding a difference between sequence numbers of two consecutive arrival packets to an initial value. And delay fluctuation absorber. 8. The delay fluctuation absorbing device according to claim 2, wherein the memory table management means receives the write pointer signal and a read pointer control signal indicating that valid data exists at the read pointer position. And a read stop signal for instructing to stop reading from the read pointer position and a data validity identification signal indicating whether or not valid data is present at the read pointer position are output. Absorber. 9. The delay fluctuation absorbing device according to claim 2, wherein the dual port memory includes: the write address signal, the write control signal, and a read address signal and a read control signal corresponding to the read pointer position. Is input and read data stored in an output packet from the delay fluctuation absorbing device is output. 10. The delay fluctuation absorbing device according to claim 2, wherein at the time of reading data, the read stop signal, the data validity identification signal, and the read data are input, and the read pointer control signal is A delay fluctuation absorbing device for performing read control for outputting a packet in which the read address signal, the read control signal, the data validity identification signal, and the read data are stored. 11. The delay fluctuation absorbing device according to claim 2, wherein the data insertion means includes: the data validity identification signal output from the read control means; and the packet storing the read data. , And the output packet from the delay fluctuation absorbing device is output. A delay fluctuation absorbing device comprising: 12. The delay fluctuation absorbing device according to claim 8, wherein the read pointer control signal is configured by a read pointer value and a read completion signal. Characteristic delay fluctuation absorber. 13. The delay fluctuation absorbing device according to claim 9, wherein the data written to the dual port memory is the entire packet data output from the sequence check means. . 14. The delay fluctuation absorbing device according to claim 9, wherein the data written to the dual port memory is audio data of a payload portion excluding a header portion from the entire packet data output from the sequence check means. A delay fluctuation absorbing device, characterized in that it is only a delay fluctuation absorbing device.