JP2007300575A - Packet buffer apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet buffer apparatus capable of easily achieving processing to discard a packet of which the time of stagnation within the apparatus exceeds a fixed time. <P>SOLUTION: The packet buffer apparatus includes: buffers 3-1, ..., 3-N; buffer management units 4-1, ..., 4-N; a destination determination unit 1 for an inputted packet; a write control unit 2 for writing the inputted packet into a buffer corresponding to a determined transmission destination; a read control unit 5 for reading out packets from the buffers 3-1, ..., 3-N; a buffer read storage unit 6 for changing a status of memory cells corresponding to read buffers from a non-read status to a read status; and a packet discard control unit 7 for outputting discard instruction signals 50-1, ..., 50-N for discarding packets stored in buffers corresponding to memory cells in the non-read status. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a packet buffer device that temporarily stores variable-length or fixed-length packets in a transmission device.

  In a network system such as a wireless or high-speed PLC, a method of transmitting data using a TDI (Time Division Multiple Access) method for transmitting and receiving data requiring real-time properties such as video or audio is being introduced. Specifically, for example, there is HiSWANA (ARIB STD-T70 1.0 version) standardized by ARIB (Association of Radio Industries and Businesses).

  Hereinafter, an outline of the TDMA system adopted in the HiSWANA standard will be briefly described. In the TDMA system adopted in the HiSWANA standard, each terminal in the network is managed by one terminal called a management terminal. The management terminal broadcasts packet data called a “Beacon signal” (hereinafter referred to as “BCH”) at a predetermined cycle (2 ms cycle in the HiSWANA standard) in order to manage time synchronization of the entire network. FIG. 10 shows transmission / reception timings of various data within one beacon cycle (hereinafter also referred to as “one frame”).

  When each terminal arranged in the network receives the BCH, it resets the reference time information in the terminal and starts preparation for receiving various control packets transmitted from the management terminal. After sending the BCH, the management terminal sends packet data for network system control (hereinafter referred to as “FCH”) including the data transmission schedule of each terminal connected to the network to each terminal connected to the network. Broadcast. Data transmission and reception schedules (data transmission / reception slot information (transmission / reception start timing information, data transmission / reception time information), etc.) of each terminal connected to the network are added to the FCH and transmitted. When each terminal receives the FCH, each terminal detects the timing at which the terminal receives data and the timing at which the terminal transmits data.

  Following the FCH transmission, the management terminal transmits a transmission request reception notification (hereinafter referred to as “ACH”) to the terminal. When transmission of each packet data of BCH, FCH, and ACH from the management terminal is completed, each terminal starts receiving and transmitting packet data based on the schedule notified by FCH. Hereinafter, a period during which data is transmitted and received between the terminals is referred to as “TCH”. In the TDMA scheme, the management terminal schedules data transmission slots only for terminals having data to be transmitted. Therefore, the terminal having the data to be transmitted needs to request the management terminal to allocate a slot for transmitting the data of the own terminal. In the TDMA system adopted in the HiSWANA standard, since a transmission request is accepted from each terminal, CSMA (Carrier Sense Multiple Access) for accepting the transmission slot request request (bandwidth allocation request) from each terminal at the end of one Beacon cycle. ) Period (hereinafter referred to as “RCH period”). The management terminal notifies the terminal that has received the transmission slot request request during the RCH period that the bandwidth allocation request has been received on the ACH within the next Beacon cycle.

  Data transmission / reception between the management terminal and the inter-network relay device to which the TDMA system based on the HiSWANA standard is applied will be described. 11 is a connection diagram between the management terminal and the inter-network relay device, FIG. 12 is a data transmission timing from the management terminal to the relay device # 1, and FIG. 13 is a data transmission timing from the relay device # 1 to the management terminal. . In FIG. 11, the communication between the management terminal and the relay apparatuses # 1 to #Y (Y is a positive integer) may be either a wireless system or a wired system. In downstream data communication from the management terminal to the relay apparatuses # 1 to Y (for example, when data is transmitted from the management terminal to the relay apparatus # 1), the management terminal transmits to the relay apparatus # 1 by the FCH 21 in FIG. The transmission start timing, data transmission time, etc. are notified by broadcast communication. The relay apparatus # 1 receives this FCH, detects the timing for receiving data from the management terminal and the data reception time, and receives data in the data transmission / reception period 22 based on this timing.

  In upstream data communication from the relay apparatus # 1 to the management terminal, when a transmission request from the relay apparatus # 1 to the management terminal is issued by the RCH 23 in FIG. 13, the management terminal relays the relay apparatus # at the ACH 24 of the next frame. 1 is notified that the transmission request has been received, and further, the FCH 25 of the next frame notifies the management terminal of the timing at which the relay apparatus # 1 can start transmission and the data transmission time. Relay device # 1 transmits data in a communication slot allocated within data transmission / reception period 26 based on the content notified by FCH 25.

  As described above, in a network system that employs the TDMA system, it is necessary to store the transmission data in the own device for a period from when the transmission data is generated until it is actually transmitted to the data transmission partner.

  Further, the description using FIGS. 12 and 13 shows an example in which all data stored in the management terminal or the relay apparatus can be transmitted to the transmission partner after one or a plurality of frame period periods. However, when the network is congested, it is not possible to transmit all the data to be transmitted, and data that cannot be transmitted may stay in the apparatus for a certain period of time. For example, in a packet that requires real-time performance, such as telephone voice, the transmission delay in the network exceeds the required standard, resulting in a decrease in information quality.

  In order to avoid such a situation, a packet that stays in the relay device for a certain period of time is discarded. As a conventional example of determining that the time spent in the relay apparatus has exceeded a certain time and discarding the excess packets, there are methods described in Patent Documents 1 and 2.

  In Patent Literature 1, an allowable delay time threshold value in a transmission waiting buffer is calculated from an in-device delay allowable time, and a difference is calculated by measuring a time queued in the transmission waiting buffer and a time read from the buffer. Thus, the dwell time in the transmission waiting buffer is obtained, the dwell time in the buffer is compared with the threshold value, and packets exceeding the threshold value are discarded.

  Further, in Patent Document 2, a time stamp value indicating an arrival time is given to an input packet, a packet output scheduled time is calculated by a relay device, and an arrival time threshold value is calculated from the set residence permission time. The time stamp value given to the packet is compared with the arrival time threshold value, and packets smaller than the threshold value are discarded preferentially.

  As described above, in the conventional example in which a packet in which the retention time in the relay device exceeds a certain time is discarded, the time inputted in the device is assigned to the packet and stored. The comparison is made between the residence time obtained from the difference between the time and the allowable delay time threshold, and in Patent Document 2, the arrival time threshold calculated based on the set residence allowable time is compared, The excess residence time in the device is determined to be discarded, and the excess packets are discarded.

JP 2000-165392 A JP 2002-185501 A

  However, the time at which the packet was input into the device is assigned to the packet and stored, and the time for which the packet stays in the device is compared with a threshold calculated based on the set allowable residence time. Needs to store the time input to the device for all input packets. In Patent Document 1, when reading from the transmission waiting buffer, the waiting time in the transmission buffer is calculated from the current time information and the time information input to the transmission waiting buffer, and compared with a threshold value. If the threshold is exceeded, the packet is discarded. If the waiting time exceeds the threshold value and multiple packets to be discarded are buffered in the transmission waiting buffer, the transmission waiting time is calculated by calculating the packet transmission waiting time in the order of buffering. It is necessary to search for a packet whose value is equal to or less than the threshold value, and processing time is required until a packet whose transmission waiting time is equal to or less than the threshold value is selected when reading from the transmission waiting buffer. In addition, in an apparatus in which real-time performance is important when reading from the transmission waiting buffer, it is difficult to apply when discarded packets are generated, for example, several tens.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and its purpose is to simplify the process of determining that the residence time in the apparatus has exceeded a certain time and discarding the packet. It is an object of the present invention to provide a packet buffer device that can be realized.

  The packet buffer device of the present invention is a device for temporarily storing and outputting input packets, and includes a plurality of buffers corresponding to transmission destinations of the input packets (and corresponding to the plurality of buffers). A plurality of buffer management units that manage information on packets buffered in the plurality of buffers, a destination determination unit that determines transmission destinations of the input packets, and the destinations of the plurality of buffers A write control unit for writing the input packet to a buffer corresponding to the transmission destination determined by the determination unit; a read control unit for reading and outputting the packet from the plurality of buffers; and a plurality of units corresponding to the plurality of buffers And when reading a packet from any one of the plurality of buffers, The state of the storage element corresponding to the buffer from which the reading was performed out of the number of storage elements, from the no-read state indicating that no packet read has been performed since the last initialization of the storage element, A buffer read storage unit for changing to a read-out state indicating that a packet read has been performed after the initialization, and an initialization signal for initializing the state of the storage element every predetermined time. A discard instruction signal for outputting to the storage unit, determining a state of the plurality of storage elements at predetermined time intervals, and discarding packets accumulated in the buffer corresponding to the storage element in a non-read state, And a packet discard control unit for outputting to the corresponding buffer management unit.

  As described above, when the packet buffer device of the present invention is used, a memory indicating whether or not a packet has been read from the buffers provided for the number of transmission destinations during the preset allowable residence time in the device. When the state of the element is in the no-read state, it can be determined that the retention time in the device of the packet accumulated in the buffer has exceeded the allowable time. There is an effect that a disposal process can be realized. Further, according to the packet buffer device of the present invention, it is not necessary to store each packet with a time stamp indicating the arrival time for calculating the residence time in the device, and whether the residence time has been exceeded Since there is no need to make a determination every time, the configuration of the packet buffer device can be simplified.

Embodiment 1 FIG.
FIG. 1 is a block diagram schematically showing a configuration of a packet buffer device according to Embodiment 1 of the present invention. As shown in FIG. 1, in the packet buffer device according to the first embodiment, a packet group in which transmission data transmitted from a plurality of terminals (not shown) is multiplexed is input and input through a data transmission path. A destination determination unit 1 that determines the transmission destination of each packet group for each packet, and each of the packets in the first to Nth (N is a positive integer) buffer based on the destination determined by the destination determination unit 1 A write control unit 2 for writing to any one of the first to Nth buffers 3-1,..., 3-N provided for each transmission destination in order to send each packet to any one of a plurality of transmission destinations; To manage buffering information of packets provided corresponding to the first to Nth buffers 3-1,..., 3-N and buffered in the first to Nth buffers 3-1,. 1st to Nth buffs Management units 4-1,..., 4-N, and a read control unit 5 that reads the packets buffered in the first to Nth buffers 3-1,. Have Further, the packet buffer device according to the first embodiment includes a plurality of storage elements (shown in FIG. 3 described later) corresponding to the plurality of buffers 3-1,. When a packet is read from any one of the buffers 1,..., 3-N, the state of the storage element corresponding to the read buffer among the plurality of storage elements is changed to the latest (current time) of the storage element. A buffer that changes from a no-read state indicating that no packet has been read since initialization to a read-only state indicating that a packet has been read since the most recent initialization. A buffer among the reading storage unit 6 and the first to Nth buffers 3-1,..., 3-N, where a packet has never been read since the most recent initialization ( You KazuSatoshi, and a packet discard control unit 7 to discard the packets stored in the buffer) without reading state.

  2 is one of the first to Nth buffer management units 4-1,..., 4-N (an integer satisfying 1 ≦ M ≦ N) shown in FIG. It is a block diagram which shows the structure of () schematically. Since each of the first to Nth buffer management units 4-1, ..., 4-N has the same structure and function, only the Mth buffer management unit 4-M will be described here. As shown in FIG. 2, the M-th buffer management unit 4-M stores the buffering information of the packets accumulated in the M-th buffer 3-M in the order of accumulation in the M-th buffer 3-M. 11 and a write pointer 12 that points to the address of the FIFO memory 11 that stores buffering information when the next packet arrives. Further, the Mth buffer management unit 4-M stores buffering information of a packet that is most recently read from the buffer and output to the data transmission path based on the buffering information stored in the FIFO memory 11. A value obtained by subtracting 1 from the value of the write pointer 12 by the read pointer 13 indicating the address and the discard instruction signal 50 (or 50-1,..., 50-N) from the packet discard control unit 7. And a switch 14 to be replaced. Here, the operation of replacing the value of the read pointer 13 with the value obtained by subtracting 1 from the value of the write pointer 12 is performed by setting the data indicated by the read pointer 13 to the previous row of the data indicated by the write pointer 12. M buffer 3-means to eliminate the data queue of M.

  FIG. 3 is a block diagram schematically showing the configuration of the buffer read storage unit 6 shown in FIG. As shown in FIG. 3, the buffer read storage unit 6 includes first to Nth storage elements 16-1,..., 16-N. The first to Nth storage elements 16-1,..., 16-N have the same configuration and function. Each of the first to Nth storage elements 16-1,..., 16-N receives a buffer read signal 20 (or 20-1,..., 20-N) for each storage element input from the read control unit 5. When it is received, a read-out state indicating that a packet has been read from the first to Nth buffers 3-1,. Also, each of the first to Nth storage elements 16-1,..., 16-N is initialized when receiving the initialization signal 30 for each storage element input from the packet discard control unit 7, and the first to Nth storage elements 16-1,. The non-reading state indicating that no packet has been read from the Nth buffers 3-1,.

  Next, the operation of the packet buffer device according to the first embodiment will be described. When a new packet arrives at the packet buffer device, the destination determining unit 1 shown in FIG. 1 determines the destination of the packet, and the packet is controlled by the write control unit 2 through the first to Nth buffers 3-1,. N is buffered in a buffer for accumulating the determined destination packet. At this time, the buffering information of the packet buffered at the position indicated by the write pointer 12 of the buffer management unit that manages the determined destination buffer among the first to Nth buffer management units 4-1,. Is written and the value of the write pointer 12 is incremented by one. The buffering information is, for example, information necessary for reading from the buffer in order to transmit the packet such as the start address of the buffer when the packet is stored in the buffer, the number of bytes of the packet, and the like. In a transmission system that handles fixed-length packets, the number of bytes of the packet is unique, and therefore it is not necessary to include the number of bytes of the packet in the buffering information. Thus, the necessary buffering information differs depending on the transmission system.

  FIG. 4 is a diagram illustrating an example of changes in the value of the read / write pointer 12 (solid line) and the value of the read pointer 13 (one-dot chain line) in the Mth buffer management unit 4-M. In FIG. 4, the value of the write pointer 12 (solid line) and the value of the read pointer 13 (one-dot chain line) strictly indicate a step-like change, but are approximated by a straight line in FIG. 4. As shown in FIG. 4, the value of the write pointer 12 of the Mth buffer management unit 4-M is incremented by 1 every time a packet is written to the Mth buffer 3-M. When the value of the write pointer 12 is repeatedly added and reaches the number of rows in the FIFO memory 11, the value returns to the top of the FIFO memory 11 as shown at time ta in FIG. 4. When the value of the write pointer 12 of the M-th buffer manager 4-M is increased until it becomes equal to the value of the read pointer 13 as shown at time tb in FIG. 4 (that is, the M-th buffer 3- The increase is stopped until the value of the read pointer 13 changes (until time tc in FIG. 4).

  When the read control unit 5 reads a packet from the Mth buffer 3-M, the read control unit 5 stores the packet in the address of the FIFO memory 11 indicated by the value obtained by adding 1 to the value of the read pointer 13 of the Mth buffer management unit 4-M. Based on the buffering information, the packet is read from the Mth buffer 3-M and output to the data transmission path. The value of the read pointer 13 of the Mth buffer management unit 4-M is incremented by 1 every time a packet is read from the Mth buffer 3-M. When the value of the read pointer 13 is repeatedly added and reaches the number of rows in the FIFO memory 11, the value returns to the top of the FIFO memory 11 as shown at time td in FIG. 4. When the value of the read pointer 13 of the Mth buffer management unit 4-M is increased to a value obtained by subtracting 1 from the value of the write pointer, as shown at time te in FIG. 4 (that is, the Mth buffer. The increase is stopped until the value of the write pointer changes (until time tf in FIG. 4).

  In addition, when the reading control unit 5 reads a packet, the reading control unit 5 has read from the buffer that stores the designated destination packet among the first to Nth buffers 3-1 to 3 -N. Is transmitted to the buffer read storage unit 6. The buffer read storage unit 6 obtains from the read control unit 5 information indicating which of the first to Nth buffers 3-1,... Of the N storage elements 16-1,..., 16-N, the storage element corresponding to the buffer from which the packet has been read is changed to a read-out state. The states of the first to Nth storage elements 16-1,..., 16-N of the buffer read storage unit 6 are input to the packet discard control unit 7. When the initialization signal 30 is received from the packet discard control unit 7, the first to Nth storage elements 16-1,. That is, the first to Nth storage elements 16-1,..., 16-N of the buffer read storage unit 6 are changed to the read state by the buffer read signal 20 issued by the read control unit 5, and the packet discard control unit 7 is a memory element that returns to the no-read state by the initialization signal 30 issued by 7 and holds the current state during other periods.

  The packet discard control unit 7 changes the state from the state of the first to Nth storage elements 16-1,..., 16-N of the buffer read storage unit 6 every P seconds from the state before P seconds to the present. It is determined whether or not a buffer read for transmitting a packet has been performed from each of the 1st to Nth buffers 3-1 to 3 -N.

  FIG. 5 is a diagram showing the value of the read pointer and the state transition of the Mth storage element 16-M when the Mth buffer 3-M is read once or more during P seconds. FIG. 5 shows operations of the M-th buffer 3-M and the M-th buffer management unit 4-M, but other buffers and buffer management units also have the same function. The Mth memory element 16-M initialized at time t11 in FIG. 5 is in a no-read state. When reading the packet from the Mth buffer 3-M, the read control unit 5 notifies the buffer read storage unit 6 that the packet has been read from the Mth buffer 3-M by the buffer read signal 20 (time t12). ). At this time, the value of the read pointer 13 of the M-th buffer management unit 4-M is a value obtained by adding 1 to RP from RP, that is, (RP + 1). At this time, the buffer read storage unit 6 changes the M-th storage element 16-M to the read-out state and holds the state.

  When the read control unit 5 notifies the buffer read storage unit 6 that the packet has been read from the Mth buffer 3-M by the buffer read signal 20, the Mth storage element 16-M has already been read. When the state is changed, the Mth storage element 16-M holds the read state (time t13, t14). At this time, the value of the read pointer 13 of the Mth buffer management unit 4-M is, for example, from (RP + 1) to (RP + 2) or from (RP + 2) to (RP + 3).

  The packet discard control unit 7 inputs the state of the Mth storage element 16-M every P seconds (for example, time t15) which is a predetermined time, and the Mth storage element 16-M is in a read state. In this case, it is assumed that reading from the M-th buffer 3-M has been performed at least once during P seconds, and packets stored in the M-th buffer 3-M are not discarded. Further, the packet discard control unit 7 returns the M-th storage element 16-M to the no-read state in order to determine whether or not the reading from the M-th buffer 3-M is performed in the next P seconds. An initialization signal 30 is sent to the buffer read storage unit 6.

  On the other hand, FIG. 6 shows the value of the write pointer 12, the value of the read pointer 13, and the value of the Mth storage element 16-M when the Mth buffer 3-M has never been read for P seconds. It is a figure which shows a state transition. At time t22, the Mth storage element 16-M remains in the no-read state, which is the state when it was initialized by the packet discard control unit 7 before P seconds (time t21). When the M-th storage element 16-M is in a non-reading state, the packet discard control unit 7 accumulates in the M-th buffer 3-M, assuming that the reading of the M-th buffer 3-M has not been performed for P seconds. It is determined that the packet staying in the buffer is longer than P seconds, a discard instruction signal 50-M is sent to the Mth buffer management unit 4-M, and the value of the read pointer 13 (FIG. 6). RP) is rewritten to be equal to the value obtained by subtracting 1 from the value of the write pointer 12 (WP-1 in FIG. 6). As a result, all the packets stored in the Mth buffer 3-M are discarded, and the number of packets stored in the Mth buffer 3-M becomes zero.

  The packet discard control unit 7 performs the same processing on all the first to Nth storage elements 16-1,..., 16-N of the buffer read storage unit 6, and the first to Nth buffers 3 Packets staying at −1,..., 3-N for a predetermined time or more are discarded as invalid packets.

  As described above, if the packet buffer device according to the first embodiment is used, whether or not a packet has been read from the buffers provided for the number of transmission destinations within a preset allowable residence time in the device. When the state of the storage element that indicates is in the no-read state, it can be determined that the residence time of the packet stored in the buffer has exceeded the allowable time, so the residence time in the device exceeds a certain time It is possible to realize a process of discarding the packet that has been discarded. Further, according to the packet buffer device of the first embodiment, it is not necessary to store a time stamp indicating the arrival time for each packet for calculating the residence time in the device, and whether the residence time has been exceeded. Since it is not necessary to determine for each packet, simplification of the configuration of the packet buffer device can be realized.

  Further, according to the packet buffer device according to the first embodiment, it is not necessary to determine for each packet whether or not the packet has exceeded the residence time at the time of packet transmission, and the packet is discarded according to the determination result and then stored in the buffer. Since there is no need to read the next packet that has been read, the buffer can be read quickly.

  In the above description, in the packet discard control unit 7, the interval for determining the state of the storage element in the buffer read storage unit 6 is set to P seconds. The allowable residence time may be set differently for each. As a result, a plurality of packets having different transmission request qualities, such as a low-priority class that can tolerate delay to some extent, a high-priority class that requires real-time performance such as telephone voice, and an intermediate class between a low-priority class and a high-priority class When request class packets coexist, they may be accumulated in individual buffers for each required quality, and the determination intervals of the storage elements of the buffer read storage unit 6 may be provided individually as P1, P2,. For example, the determination interval time of the storage element that stores the reading from the buffer that accumulates the high-priority class packet is shortened, and the reading from the buffer that accumulates the low-priority class packet is stored. A plurality of required qualities can be controlled by setting the determination interval time of the storage element to be long.

Embodiment 2. FIG.
FIG. 7 is a block diagram schematically showing the configuration of the packet buffer device according to the second embodiment of the present invention. In FIG. 7, the same or corresponding components as those shown in FIG. In the packet buffer device according to the second embodiment, the configuration of the first to Nth buffer management units 8-1, ..., 8-N (N is a positive integer) is the same as that of the packet buffer device according to the first embodiment. This is different from the first to Nth buffer management units 4-1,. In the packet buffer device according to the second embodiment, the write pointer value temporary storage instruction 60 (or 60) is sent from the packet discard control unit 9 described later to the first to Nth buffer management units 8-1,. −1,..., 60-N) is different from the packet buffer device according to the first embodiment.

  FIG. 8 is a block diagram schematically showing a configuration of an Mth buffer management unit 8-M (M is an integer satisfying 1 ≦ M ≦ N) of the packet buffer device according to the second embodiment. In FIG. 8, the same or corresponding components as those shown in FIG. The packet discard control unit 9 writes the write pointer value temporary storage instruction 60 (or 60-1,..., 60-N) to the first to Nth buffer management units 8-1,. ). Each of the first to Nth buffer managers 8-1,..., 8-N receives the write pointer value temporary storage instruction, and the value of the write pointer 12 at this time is stored in the temporary register 15. The packet discard control unit 9 also performs the period from P seconds before to the present from the state of the first to Nth storage elements 16-1,..., 16-N of the buffer read storage unit 6 every fixed time P seconds. It is determined whether or not there has been a buffer read for transmitting a packet from each of the first to Nth buffers 3-1,..., 3-N, and if there is no buffer read, the discard instruction signal 50 ( Or 50-1,..., 50-N).

FIG. 9 shows the value of the write pointer 12, the value of the read pointer 13, the value of the temporary register 15, and the Mth storage element when there has been no reading of the Mth buffer 3 -M for P seconds. It is a figure which shows the transition of the state of 16-M. Since the first to Nth buffer management units 8-1,..., 8-N have the same structure and function, only the Mth buffer management unit 8-M will be described here. In FIG. 9, WP ₀ , WP ₁ , WP ₁ +1, WP ₁ +2,..., WP ₂ , WP ₂ +1 indicate the values of the write pointer 12. At time t32, the Mth storage element 16-M remains in the no-read state, which is the state when it was initialized by the packet discard control unit 9 before P seconds (time t31). When the M-th memory element 16-M is in the no-read state, the packet discard control unit 9 assumes that the M-th buffer 3-M has not been read for P seconds, and stores it in the M-th buffer 3-M for P seconds. It is determined that the time during which packets accumulated until the previous time (time t31) stay in the buffer is P seconds or more, and a discard instruction signal 50-M is sent to the Mth buffer management unit 8-M. The buffer managing unit 8-M of the M, P seconds before and the value WP ₁ of the write pointer (time t31) is stored in the temporary register 15 receives the discard instruction signal 50-M, the value of the temporary register 15 The value of the read pointer 13 is rewritten so that the value obtained by subtracting ₁ from WP ₁ , that is, (WP ₁ −1) becomes the value of the read pointer 13. As a result, all the packets accumulated before P seconds ago in the M-th buffer 3-M are discarded, and the buffer residence time of all the packets accumulated in the M-th buffer 3-M is Less than P seconds.

  As described above, if the packet buffer device according to the second embodiment is used, whether or not a packet has been read from the buffers provided for the number of transmission destinations within a preset allowable residence time in the device. When the state of the storage element that indicates is in the no-read state, it can be determined that the residence time of the packet stored in the buffer has exceeded the allowable time, so the residence time in the device exceeds a certain time It is possible to realize a process of discarding the packet that has been discarded. Further, according to the packet buffer device of the first embodiment, it is not necessary to store a time stamp indicating the arrival time for each packet for calculating the residence time in the device, and whether the residence time has been exceeded. Since it is not necessary to determine for each packet, simplification of the configuration of the packet buffer device can be realized.

  In addition, if the packet buffer device according to the second embodiment is used, the buffer accumulation state is stored at regular intervals, accumulated for a certain time before the buffer that has not been read for a certain time, and stays in the buffer. By rewriting the buffer state as if the transmitted packet was transmitted, it is possible to store only the packets whose residence time in the apparatus is within the allowable time in the buffer.

  Furthermore, if the packet buffer device according to the second embodiment is used, it is not necessary to determine for each packet whether or not the packet has exceeded the residence time when the packet is transmitted, and the packet is discarded according to the determination result and then stored in the buffer. Since there is no need to read the next packet that has been read, there is an effect that the buffer reading can be performed quickly.

  Furthermore, in the packet buffer device according to the second embodiment, as described in the first embodiment, the packet discard control unit 9 determines the interval of the storage element in the buffer read storage unit 6 and the buffer management unit. The interval for temporarily storing the write pointer 12 may be set individually for each storage element, and the allowable residence time may be set differently for each buffer.

  In the second embodiment, points other than those described above are the same as those in the first embodiment.

It is a block diagram which shows roughly the structure of the packet buffer apparatus concerning Embodiment 1 of this invention. 6 is a block diagram schematically showing a configuration of an Mth buffer management unit of the packet buffer device according to Embodiment 1. FIG. FIG. 2 is a block diagram schematically showing a configuration of a buffer read storage unit shown in FIG. 1. 6 is a diagram illustrating an example of changes in values of a write pointer and a read pointer of an Mth buffer management unit of the packet buffer device according to Embodiment 1. FIG. In Embodiment 1, it is a figure which shows the transition of the state of the read pointer and buffer read-out memory element when there exists reading from the Mth buffer. In Embodiment 1, it is a figure which shows the transition of the state of a read pointer and a buffer read storage element when there is no read from the Mth buffer. It is a block diagram which shows roughly the structure of the packet buffer apparatus concerning Embodiment 2 of this invention. FIG. 10 is a block diagram schematically showing a configuration of an Mth buffer management unit of the packet buffer device according to the second embodiment. In Embodiment 2, it is a figure which shows the state transition of the read pointer, buffer read memory element, and temporary register when there is no read from the Mth buffer. It is a figure which shows roughly the structure of the data format in 1 frame in the transmission system which employ | adopts TDMA system, and the schedule data in FCH. 1 is a diagram schematically showing a configuration of a network system. It is a figure which shows transition within 1 frame period of the buffer amount accumulate | stored in the management terminal in the transmission system which employ | adopts TDMA system. It is a figure which shows transition of the buffer amount accumulate | stored in the relay apparatus in the transmission system which employ | adopts TDMA system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Destination determination part, 2 Write control part, 3-1, ..., 3-N 1st thru | or Nth buffer, 4-1, ..., 4-N, 8-1, ..., 8-N 1st thru | or 1st N buffer management unit, 5 read control unit, 6 buffer read storage unit, 7, 9 packet discard control unit, 11 FIFO memory, 12 write pointer, 13 read pointer, 15 temporary register, 16-1,..., 16-N 1st to Nth storage elements, 20 or 20-1,..., 20-N buffer read signal, 21 FCH, 22 data transmission / reception period, 23 RCH, 24 ACH, 25 FCH, 26 data transmission / reception period, 30 or 30- 1, ..., 30-N initialization signal, 40 or 40-1, ..., 40-N Buffer read / unread signal, 50 or 50-1, ..., 50-N Discard instruction signal, 60-1, ..., 60 N write pointer value temporary storage instruction signal.

Claims (6)

In a packet buffer device for temporarily storing and outputting input packets,
A plurality of buffers corresponding to transmission destinations of the input packets;
A plurality of buffer management units that are provided corresponding to the plurality of buffers and that manage information on packets buffered in the plurality of buffers;
A destination determination unit that determines a transmission destination of the input packet;
A write control unit for writing the input packet to a buffer corresponding to the transmission destination determined by the destination determination unit among the plurality of buffers;
A read controller that reads and outputs packets from the plurality of buffers;
The plurality of storage elements corresponding to the plurality of buffers, and when the packet is read from any one of the plurality of buffers, the buffer from which the reading is performed among the plurality of storage elements The packet reading has been performed after the initialization from the no-read state indicating that no packet reading has been performed since the last initialization of the storage element. A buffer read storage unit for changing to a read-out state indicating that,
An initialization signal for initializing the state of the storage element at every predetermined time is output to the buffer read storage unit, and the state of the plurality of storage elements is determined at a predetermined time to indicate a no-read state. A packet discard control unit that outputs a discard instruction signal for discarding a packet stored in the buffer corresponding to the storage element to the corresponding buffer management unit;   The buffer management unit that has received the discard instruction signal excludes all packets stored in the corresponding buffer before the time when the discard instruction signal is received from being read by the read control unit, and discards the packet. All packets stored in the corresponding buffer are discarded by performing a process in which a packet input to the corresponding buffer is read by the read control unit after the time point when the instruction signal is received. The packet buffer device according to claim 1. Each of the plurality of buffer management units includes:
A FIFO memory for storing the buffering information of the packets accumulated in the buffer in the order of accumulation;
A write pointer that points to the address of the FIFO memory for storing packet buffering information;
A read pointer indicating the address of the FIFO memory in which buffering information of the packet read from the buffer was stored;
In the process of discarding all packets by the buffer management unit, the value of the read pointer of the buffer management unit of the buffer determined to be discarded by the packet discard control unit is subtracted from the value of the write pointer. The packet buffer device according to claim 2, wherein the packet buffer device is rewritten to a value.   The buffer management unit that has received the discard instruction signal is a packet that has been accumulated in the corresponding buffer before the time when the discard instruction signal is received, and is accumulated in the buffer for a predetermined accumulation dwell time or longer. The packet buffer device according to claim 1, wherein the packet stored in the corresponding buffer is discarded by performing a process of excluding a continuing packet from a reading target by the reading control unit. Each of the plurality of buffer management units includes:
A FIFO memory for storing the buffering information of the packets accumulated in the buffer in the order of accumulation;
A write pointer that points to the address of the FIFO memory for storing packet buffering information;
A read pointer indicating the address of the FIFO memory in which the buffering information of the packet read from the buffer is stored, and a temporary register temporarily storing the value of the write pointer for each predetermined residence allowable time,
The process in which the buffer management unit discards packets accumulated in the buffer for a predetermined allowable residence time or longer is determined by the read pointer of the buffer management unit of the buffer determined to be discarded by the packet discard control unit. The packet buffer device according to claim 4, wherein the packet buffer device is performed by rewriting the value to a value obtained by subtracting 1 from the value of the temporary register.   6. The packet buffer device according to claim 1, wherein the predetermined time interval for determining the state of the plurality of storage elements is set to a different value for each of the plurality of storage elements.

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