JP2002150686A - Equalizing circuit and reproducing device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve an unstable operation like the divergence of the tap coefficient of an automatic equalizing circuit or a slow convergence of the tap coefficient in the period before clock synchronization at the tine of reproduction start. SOLUTION: At the time of reproduction start, a coefficient control circuit 90 gives a tap coefficient stored in a coefficient storage circuit 91 to an automatic equalizing circuit 60 as an initial value, and update of the tap coefficient is stopped to perform operation in a fixed equalization mode. When a synchronous detection circuit 83 detects that a clock has been synchronized, update of the tap coefficient is executed, and the mode is shifted to an automatic equalization mode. Further, the coefficient control circuit 90 stores the tap coefficient value, which is obtained when the number of code errors detected by an error detection circuit 71 is equal to or smaller than a prescribed value, into the coefficient storage circuit 91. When the mode is shifted to a special reproducing mode or the like, the preliminarily stored tap coefficient is set again, and update of the tap coefficient is stopped to perform operation in the fixed equalization mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizing circuit for A / D converting and equalizing an information signal reproduced from a recording medium and a reproducing apparatus using the same. The present invention relates to an equalizing circuit capable of performing a stable operation at the time of reproducing a discontinuous or burst signal and a reproducing apparatus using the same.

[0002]

2. Description of the Related Art A signal reproduced from a magnetic recording medium is A / A.
Examples of an equalizing circuit that performs D conversion and equalizes the signal include, for example, Japanese Patent Application Laid-Open Nos. 10-134513 and 10-269.
No. 701, 10-275422, 10-
As described in Japanese Patent Publication No. 275423, a transversal filter equalizing circuit having a plurality of taps is used, and an automatic equalizing circuit that equalizes while automatically updating tap coefficients has been proposed.

[0003]

However, in the above-mentioned conventional equalizing circuit, when the reproduction is started, the updating of the tap coefficient is started in a state where the A / D conversion clock is asynchronous, so that the clock is in a synchronous state. The tap coefficient diverges,
Or there is a problem that the convergence of the tap coefficient is slow,
No consideration was given to this. Also, no consideration has been given to stabilizing the operation during special reproduction, discontinuous or burst signal reproduction, and the like.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to provide an equalizing circuit which operates stably even at the start of operation, at the time of special reproduction, at the time of discontinuous or burst signal reproduction, and the use of the same. To provide a playback device.

[0005]

In order to achieve the above object, an equalizing circuit and a reproducing apparatus using the same according to the present invention provide a tap coefficient of a transversal type filter at the start of an equalizing operation (reproduction). Operate with the initial value fixed,
The synchronization detection circuit detects whether the A / D conversion clock is synchronized, and operates while updating the tap coefficient after the clock is synchronized. Further, in the present invention, a coefficient storage circuit that stores a tap coefficient value to be updated and an error detection circuit that counts the number of code errors of the equalized signal are provided, and the number of code errors counted by the error detection circuit is equal to or less than a predetermined value. When this happens, the tap coefficient stored in the coefficient storage circuit is reset, and thereafter, the equalization operation is performed by fixing the tap coefficient to the reset tap coefficient.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the reproducing apparatus according to the present invention. A signal reproduced from the recording medium 1 by the magnetic head 2 is amplified to a predetermined level by a reproduction amplifier 3, a high-frequency noise component is removed by a low-pass filter 4, and A / A
The signal is converted into a digital signal by the D conversion circuit 5, is equalized by the automatic equalization circuit 60 using a transversal filter, and is decoded by the decoding circuit 70. A / D conversion circuit 5
(Not shown, but also supplied to the automatic equalization circuit 60 and the decoding circuit 70) are supplied to the phase error detection circuit 80, the loop filter 81 and the voltage controlled oscillator 8
2 generated by a clock recovery circuit.

In this embodiment, the automatic equalizing circuit 60
A coefficient control circuit 90 for controlling the tap coefficient update processing, a coefficient storage circuit 91 for storing the tap coefficients, a synchronization detection circuit 83 for detecting clock synchronization / asynchronization, and a code error detection for a signal decoded by the decoding circuit 70. The feature is that an error detection circuit 71 for counting the number is provided, and the tap coefficient update processing of the automatic equalization circuit 60 is controlled by the following method.

When the mode of the reproducing apparatus changes from stop (STOP) to reproduction (PLAY), the coefficient control circuit 90
First, the tap coefficient value stored in the coefficient storage circuit 91 is given to the automatic equalization circuit 60 as an initial value,
The tap coefficient update process is stopped, and the operation is performed in the fixed equalization mode.

Next, when a clock synchronization detection is received from the synchronization detection circuit 83, a tap coefficient update process is executed, and a transition is made to an automatic equalization mode. By this control, the tap coefficient update process is not executed when the clock is asynchronous, so that the problem that the tap coefficient diverges or the convergence of the tap coefficient slows down in the tap coefficient update process after clock synchronization is solved.

When the number of code errors detected and counted by the error detection circuit 71 becomes equal to or smaller than a predetermined value, the coefficient control circuit 90 stores the tap coefficient value at that time in the coefficient storage circuit 91. The process of counting the number of code errors and storing the tap coefficient value is performed at a predetermined cycle. For example, in the case of a helical scan type reproducing apparatus using a rotating head, processing is performed in one track cycle. Then, the stored tap coefficient value is used as the next initial value.

Finally, the coefficient control circuit 90 stops the tap coefficient update processing, resets the previously stored tap coefficient values, and operates the automatic equalization circuit 60 in the fixed equalization mode. This last control is performed when the mode of the playback device is playback (PL
AY) to special playback (CUE / REV), or a playback signal is input in a discontinuous or burst state,
This is effective in the case where no input state continues for a long time.

FIG. 2 is a block diagram showing an example of the automatic equalizing circuit 60. In FIG. 2, 11 to 15 are delay circuits, 21
26 is a multiplication circuit, 30 is an addition circuit, 31 is a sign discrimination circuit, 32 is a subtraction circuit, 33 is a multiplication circuit, 41 to 46 are multiplication circuits, and 51 to 56 are LPFs.

The transversal filter is composed of delay circuits 11 to 15, multiplier circuits 21 to 26 and an adder circuit 30. The equalization input signal and the output signals of the delay circuits 11 to 15 are respectively multiplied by the multiplier circuits 21 to 26. Weighting is performed, and an addition circuit 30 adds and combines them to output an equalized output signal YDT.

The sign discriminating circuit 31 outputs the equalized output signal YDT
Is compared with a threshold level based on the reference value A to output a ternary code discrimination signal ZDT. The subtraction circuit 32 outputs an equalization error signal EDT by subtracting the code discrimination signal ZDT from the equalization output signal YDT. The multiplication circuit 33 multiplies the equalization error signal EDT by a predetermined coefficient −Δ to output an error signal ERR. Note that the reference value A and the coefficient −Δ are input from the coefficient control circuit 90. The tap coefficient updating circuit composed of the multiplication circuits 41 to 46 and the LPFs 51 to 56 multiplies the error signal ERR with the equalization input signal and the output signals of the delay circuits 11 to 15 by the multiplication circuits 41 to 46, respectively. Each is integrated by 56 and the tap coefficients are output to the multiplication circuits 21 to 26 of the transversal filter.

FIG. 2 shows an example in which the reproduction signal is adaptively equalized to a PR (1, 0, -1) signal by an automatic equalization circuit having 6 (even number) taps as disclosed in JP-A-10-134513. The same applies to the case where a reproduced signal is adaptively equalized to a PR (1, -1) signal by an automatic equalizing circuit having 5 (odd) taps described in the above.

FIG. 3 is a block diagram showing an example of the LPF 53. The same applies to the other LPFs 51 to 52 and 54 to 56.
During normal operation, the multiplication value XP3 (XD3 × ERR) is weighted by the multiplication circuit 531 by the coefficient Δ3, and
32 and a delay coefficient 533 to output a tap coefficient update value CD3. Like the coefficient Δ, the coefficient Δ3 is input from the coefficient control circuit 90, and the tap coefficient update value CD3 is also output to the coefficient control circuit 90 and stored in the coefficient storage circuit 91.

The switching circuit 534 switches whether to execute or stop the tap coefficient update processing in accordance with the mode signal MOD from the coefficient control circuit 90. When the tap coefficient update process is stopped, the previous value is output as the tap coefficient update value CD3. Further, the switching circuit 635 selects the initial value CA3 according to the load signal LOD from the coefficient control circuit 90, and outputs the initial value CA3 as the tap coefficient update value CD3 via the delay circuit 633. Thereby, the automatic equalization circuit 60 can be operated in the fixed equalization mode with an arbitrary tap coefficient.

As a period during which the automatic equalizing circuit 60 is operated in the fixed equalization mode, there is a discontinuous (burst) signal reproduction other than the reproduction start or the special reproduction. However, the operation may be performed in the fixed equalization mode only when there is no signal input, and in the automatic equalization mode when the signal is input. In addition, when a fixed data area is included even when the reproduction signal is continuous, only this area can be set to the fixed equalization mode, and the random data area can be operated in the automatic equalization mode. The coefficient control circuit 90 can also perform such control.

FIG. 4 is a block diagram showing another embodiment of the reproducing apparatus according to the present invention. Reference numeral 84 denotes a frequency error detection circuit for detecting a frequency error of the reproduced clock, 85 denotes an addition circuit, and the same reference numerals as those in FIG. 1 denote the same components. A feature of the present embodiment is that a frequency error detection circuit 84 is provided instead of the synchronization detection circuit 83, and the output of the frequency error detection circuit 84 and the output of the phase error detection circuit 80 are added by the addition circuit 85 and input to the loop filter 81. In that the configuration is

The frequency error detection circuit 85 detects a frequency error between a reproduction clock, which is an output signal of the voltage controlled oscillator 82, and a reference clock (for example, a fixed clock used during recording). FIG. 5 shows an example of the relationship between the clock frequencies. In FIG.
Fo is the center frequency, ΔF is the frequency deviation, and Fo ± Δ
In the frequency range of F, the error output is set to zero assuming synchronization,
If it exceeds the range, it is regarded as asynchronous and outputs a voltage corresponding to the error. The result of the synchronization / asynchronization determination is supplied to the coefficient control circuit 90, and is processed in the same manner as in FIG.

On the other hand, the error output of the frequency error detection circuit 84 is added to the error output of the phase error detection circuit 80 by the addition circuit 85 and is input to the loop filter 81. Thereby, the time until the reproduction clock is synchronized can be shortened. The center frequency Fo and the frequency deviation ΔF are set by the coefficient control circuit 90, and by changing the center frequency Fo, not only normal reproduction but also special reproduction can be supported. FIG. 6 is a diagram illustrating an example of the frequency characteristic of the loop filter 81. The coefficient control circuit 90 further controls the frequency characteristics of the loop filter 81. That is, the DC gain A and / or the cut-off frequency B are increased until the reproduced clock is synchronized to increase the response, and after the synchronization, the DC gain A and / or the cut-off frequency B are reduced and stabilized. As a result, the time until the reproduction clock is synchronized can be further reduced.

As described above, in the embodiments shown in FIGS. 1 and 4, the output signal of the automatic equalization circuit 60 is used as the input signal of the phase error detection circuit 80. However, the present invention is not limited to this. , The output signal of the A / D conversion circuit 5, in other words, the case where the input signal of the automatic equalization circuit 60 is used. Further, a magnetic recording medium has been described as an example of the recording medium 1, but it is needless to say that the present invention can be applied to an optical recording medium.

[0023]

As described above, according to the present invention, the operation of the automatic equalizing circuit can be stabilized even during the time until the clock is synchronized at the start of reproduction, so that the tap coefficient may diverge due to unstable operation during this period. Alternatively, the problem that the convergence of the tap coefficients is delayed can be solved.

When the reproduction signal is discontinuous, such as during special reproduction, the tap coefficient diverges at the discontinuous portion by operating the automatic equalization circuit as a fixed equalization circuit having an optimum tap coefficient. Can be prevented.

Further, it is possible to shorten the time until the clocks at the start of reproduction are synchronized. As a result, there is an effect that the reliability as a reproducing apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a reproducing apparatus according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of an automatic equalization circuit 60.

FIG. 3 is a configuration diagram illustrating an example of an LPF 53;

FIG. 4 is a block diagram showing another embodiment of the reproducing apparatus according to the present invention.

FIG. 5 is a diagram illustrating an example of an input / output relationship of a frequency error detection circuit 84;

FIG. 6 is a diagram illustrating an example of a frequency characteristic of a loop filter 81.

[Explanation of symbols]

Reference numeral 60: automatic equalization circuit, 70: decoding circuit, 71: error detection circuit, 80: phase error detection circuit, 81: loop filter, 82: voltage controlled oscillator, 83: synchronization detection circuit, 84
... Frequency error detection circuit, 85 addition circuit, 90 coefficient control circuit, 91 coefficient storage circuit.

Claims (4)

[Claims] 1. An equalizing circuit for A / D converting and equalizing a transmitted information signal, comprising: a transversal filter having a plurality of taps for equalizing the A / D converted information signal; An error calculation circuit that determines the sign of the information signal equalized by the type filter, and calculates a value corresponding to the amplitude error based on the information signal.From the output signal of the error calculation circuit and the output signal of each of the plurality of taps, A tap coefficient updating circuit for updating the tap coefficient of the above, and a synchronization detecting circuit for detecting the synchronization between the A / D conversion clock and the equalized information signal. After the synchronization detection circuit detects that the A / D conversion clock has been synchronized, the tap coefficient update circuit operates after fixing the tap coefficients of the respective taps to predetermined initial values. Equalizing circuit, characterized in that the operation to update each coefficient of the serial multiple taps. 2. An equalizing circuit for equalizing a transmitted information signal, comprising: a transversal filter having a plurality of taps for equalizing the information signal; An error calculation circuit that determines a sign and calculates a value corresponding to an amplitude error based on the code; and a tap coefficient update circuit that updates each tap coefficient from an output signal of the error calculation circuit and an output signal of each of the plurality of taps. A coefficient storage circuit that stores the plurality of tap coefficients updated by the tap coefficient update circuit at a predetermined cycle; and an error detection that counts the number of code errors of the equalized information signal at each of the predetermined cycles. When the number of code errors counted by the error detection circuit is less than or equal to a predetermined value, reset the tap coefficient stored in the coefficient storage circuit, After equalization circuit which is characterized in that the equalization operation by fixing the tap coefficients 該再 set. 3. A reproducing means for reproducing an information signal recorded on a recording medium, and an A / D converter for A / D converting the reproduced information signal.
A / D conversion circuit, an equalization circuit for equalizing the A / D-converted information signal, a decoding circuit for decoding the equalized information signal, and a clock generator for generating a clock for the A / D conversion circuit A transversal filter having a plurality of taps for equalizing the A / D-converted information signal; and a transversal filter for the information signal equalized by the transversal filter. An error calculation circuit that determines a sign and calculates a value corresponding to an amplitude error based on the code; and a tap coefficient update circuit that updates each tap coefficient from an output signal of the error calculation circuit and an output signal of each of the plurality of taps. And a synchronization detection circuit for detecting the synchronization between the A / D conversion clock and the equalized information signal. When the equalization operation is started, the synchronization of the plurality of taps is performed. Are fixed to predetermined initial values, respectively, and after the synchronization detection circuit detects that the A / D conversion clock is synchronized, the tap coefficient update circuit updates the coefficients of the plurality of taps, respectively. A playback device characterized by operating in the following manner. 4. A reproducing apparatus comprising: reproducing means for reproducing an information signal recorded on a recording medium; an equalizing circuit for equalizing the reproduced information signal; and a decoding circuit for decoding the equalized information signal. In the apparatus, the equalization circuit determines a code of the information signal equalized by the transversal filter, the transversal filter having a plurality of taps for equalizing the reproduced information signal, and determines an amplitude based on the information. An error operation circuit that calculates a value corresponding to an error; a tap coefficient update circuit that updates each tap coefficient from an output signal of the error operation circuit and an output signal of each of the plurality of taps; and the tap coefficient update circuit. A coefficient storage circuit for storing the coefficients of the plurality of taps to be updated in a predetermined cycle, and counting the number of code errors of the equalized information signal for each of the predetermined cycles. When the number of code errors counted by the error detection circuit becomes equal to or less than a predetermined value, the tap coefficient stored in the coefficient storage circuit is reset, and thereafter, the reset is performed. A reproducing apparatus wherein an equalizing operation is performed with tap coefficients fixed.