JP2002149492A - Method for controlling cache memory and storage sub- system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the hit rate of specified prior data highly regardless of the rate of a cache memory capacity to the data capacity of a whole storage device. SOLUTION: In a disk sub-system 102 interposed between a central processing unit 101 and a disk drive 103, a priority queue area 108 whose capacity is made variable and set to an upper limit value 111 and a general queue area 109 are set in a queue management table 107 of a cache control part 106 which manages the cache memory 105, and the management of the priority data whose priority is high in the cache memory 105 is operated in a priority queue area 108, and the management of the other general data is operated in the general queue area 109 so that the residence time of the priority data in the cache memory 105 can be made longer than that of the general data. Thus, it is possible to maintain the hit rate of the priority data highly regardless of the rate of the storage capacity of a disk drive 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control technique for a cache memory and a storage subsystem, and more particularly to a technique effective when applied to a storage subsystem or a data processing system having a cache memory.

[0002]

2. Description of the Related Art For example, a disk subsystem, which is a kind of external storage device operated under the control of a central processing unit, is generally provided with a cache memory for improving data transfer performance. In addition, data processing performance is greatly reduced due to access to a disk drive due to a cache miss. One way to improve data processing performance is to improve the cache hit ratio. Further, as a means for realizing an improvement in the cache hit ratio, an increase in a cache memory can be mentioned. However, in recent years, while the storage capacity of the data processing system has increased dramatically, the rate of increase in the cache memory capacity that can be implemented in the system is low, and the ratio of the cache memory capacity to the system capacity is decreasing. It is expected that this percentage will decrease in the future.

At present, data in a cache memory is generally stored in LRU (Least Recently Used).
ed) It is managed by one management table using the method.

[0004]

However, the cache hit ratio of data requested to be accessed by the central processing unit in the LRU management system using this one management table is as follows.
The value can only be proportional to the access frequency. In addition, as the processing data amount increases due to the increase in the capacity of the entire system as described above, the competition rate of use of the cache memory between data increases, so that even frequently accessed data can easily be erased from the cache memory. This may cause a reduction in data processing performance due to a cache miss.

Further, as disclosed in Japanese Patent Application Laid-Open No. Hei 6-168075, a specific area for simple double writing capable of high-speed data writing without a so-called write penalty is secured in a part of a storage area of a disk array device. At the same time, a specified area having the same size as the data capacity of the specified area that requires the specified high-speed processing is secured in the cache memory, and the area is exclusively used for the specified data. -There has been proposed a control method for processing at a hit rate.

However, in this method, the capacity of a specific area on the cache memory and the data capacity requiring high-speed processing are:
Since it is limited to 1: 1, a cache hit ratio of 100% can be obtained, but the data capacity that can be specified is limited by the mounted cache memory size.

An object of the present invention is to maintain a high cache hit ratio of high-priority data without being affected by a relative decrease in the cache memory capacity with respect to the total amount of data. To improve the data processing performance.

Another object of the present invention is to realize an optimum cache hit ratio according to the priority for each data having a different processing priority.

Another object of the present invention is to improve the cache hit ratio by managing the cache memory so that data requiring high-speed data processing is retained in the cache memory for a long period of time, thereby improving the cache hit rate. An object of the present invention is to realize high-speed data processing by minimizing a decrease in data processing performance due to the above.

Another object of the present invention is to realize a high-availability large data capacity by variably realizing a priority data capacity in a cache memory and a data capacity requiring high-speed data processing between 1: 1 and 1: N. It is to realize construction of a capacity data processing system.

[0011]

According to the present invention, there is provided a cache which is interposed between a first device and a second device and temporarily stores data transmitted and received between the first device and the second device. In the memory control method, cache management information for managing a cache memory is divided into at least two pieces of first and second management information, and a plurality of pieces of first and second management information are selectively used according to the priority of data. Thereby, the staying time of the higher priority data in the cache memory is made longer.

Further, the present invention includes a storage device, and a storage control device which controls transmission and reception of data between the storage device and a higher-level device and has a cache memory for temporarily storing data. In the storage subsystem, the cache management information for managing the cache memory is divided into at least two pieces of first and second management information, and a plurality of pieces of the first and second management information are selectively used according to the priority of data. And a control logic for extending the staying time of higher priority data in the cache memory.

More specifically, as an example, according to the present invention, when there is an access request from the central processing unit to the storage subsystem such as the disk subsystem for the priority data set by the system user, the disk subsystem After performing a cache hit / miss determination of priority data requested to be accessed for the entire queue management table in the cache control unit, a data transfer process based on the determination is performed, and at the same time, the segment position information of the priority data is cache-controlled. LR to priority queue area in department
Register by U method. On the other hand, in response to an access request to general data, a cache hit / miss determination is performed only for the general queue area in the queue management table in the cache control unit, and a data transfer process based on the determination is performed. At the same time, the segment position information of the general data is registered in the general queue area in the queue management table in the cache control unit by the LRU method.

When a priority standard is set by the system user, the cache control unit in the disk subsystem requests the cache processing unit from the central processing unit based on an access cycle of data satisfying the priority standard. Data that can be accessed at high frequency is extracted from the data that has high access frequency, and the segment position information of the data is registered as priority data in the priority queue area by the LRU method, thereby improving the cache hit rate and enabling high-speed data processing. Implement a processing system.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of a data processing system including a disk subsystem which is an example of a storage subsystem for implementing a cache memory control method according to an embodiment of the present invention.

The data processing system according to the present embodiment performs data processing and performs input / output interface control 1
The CPU 101 includes a central processing unit (CPU) 101 for inputting / outputting data to / from an external device via an external device 01a, and a disk subsystem 102 for controlling data transfer processing between the CPU 101 and a subordinate disk drive 103.

The disk subsystem 102 includes an input / output interface control unit 101a, a channel I / F control unit 1
04a to the disk drive 10
Data processing control unit 10 that processes a data transfer request to
4. Cache memory 1 for temporarily storing data exchanged between disk drive 103 and CPU 101
05, and a cache control unit 106 that controls data input / output to / from the cache memory 105.

The cache control unit 106 includes a queue management table 107 for managing data stored in the cache memory 105 and a slot information management table 110.

In the case of the present embodiment, a priority queue area 108 and a general queue area 109 are provided in the queue management table 107, and each area is separately queue-managed. Controls data input / output. Until the system user sets the upper limit value 111 of the priority data capacity, the cache memory 105 stores the general queue area 10.
9 is managed.

That is, as shown in the flowchart of FIG. 5, a service processor (not shown) for controlling the disk subsystem 102 from the outside, a CPU 101
When the disk subsystem 102 receives the preferential use designation command issued from (step 501), it is determined whether or not the command includes data designating the upper limit value 111 of the preferential data capacity (step 50).
2) If it is included, the upper limit value 111 of the priority data capacity is set or updated (step 503). At this time, if the upper limit value 111 of the priority data capacity is set to zero,
The capacity of the priority queue area 108 becomes zero, and normal cache control is performed only by the general queue area 109. If the capacity is other than zero, the priority queue area 108 becomes effective and the priority data cache Control is performed to increase the stay time in the memory 105 and maintain the hit rate higher.

Further, it is determined whether or not the command includes information for designating priority data (step 504).
If it is included, the specific information such as the specific drive number and logical address range of the disk drive 103 storing the data to be handled as priority data is stored in a control memory (not shown) of the cache control unit 106. (Step 505) Processing is performed to determine whether the data is priority data or general data, as described below, based on whether the data of the access request from the CPU 101 matches the condition.

First, an outline of data transfer processing when a system user sets priority data will be described with reference to FIG.

In response to a priority data request from the CPU 101, the data processing control unit 104 searches the queue management table 107 in the cache control unit 106 and
In the case of a hit, the data processing control unit 104 performs data transfer processing using the data in the cache memory 105, and simultaneously registers the segment position information in the priority queue area 108 of the queue management table 107 by the LRU method. In the case of a cache miss, the requested priority data is loaded from the disk drive 103, written to the cache memory 105, and the segment position information is registered in the priority queue area 108 by the LRU method.

In response to a general data request from the CPU 101, the data processing control unit 104 operates the general queue area 10 in the queue management table 107 in the cache control unit 106.
In the case of a cache hit, the data processing control unit 104 performs data transfer processing using the data in the cache memory 105, and simultaneously registers the segment position information in the general queue area 109 by the LRU method. In the case of a cache miss, it is checked whether there is an empty segment in the cache memory 105. If there is an empty segment, the general queue area 1
09, the segment position information is registered by the LRU method,
If there is no empty segment, the segment position information of the data to be discarded from the cache memory 105 is selected and discarded from the general queue area by the LRU method,
Thereafter, the requested general data is transferred to the disk drive 10.
3 is loaded (copied) onto the cache memory 105, and the segment position information is stored in the general queue area 109.
Is registered by the LRU method.

The flow of processing at the time of a cache hit / miss at the time of a priority data request and the transition of a queue in this embodiment will be described with reference to the flowchart of FIG. In this case, whether the data is priority data or not is determined by a condition set in advance by the system user (for example, whether the storage logical address of the data in the disk drive 103 is within a specified address range, whether the data is stored in a specific disk drive). Is determined based on whether or not the data matches the data.

In response to a priority data request (step 301) from the CPU 101, a cache hit / miss determination (step 302) is performed. In the case of a cache hit, the general queue area 109 or the priority queue area 108 (Step 310), and the priority queue area 10
8, in the case of a cache hit, the segment position information of the requested priority data is registered in the priority queue area 108 by the LRU method (step 311).
In the case of a cache hit in the general queue area 109, it is further determined whether or not there is free space in the priority queue area 108 (step 307). Is registered by the LRU method (step 311). If there is no free space in the priority queue area 108, the segment position information of the data to be moved to the general queue area 109 is stored in the priority queue area 10 (step 311).
8 is selected by the LRU method (step 308) and registered at the head of the general queue area 109 (step 30).
9) The segment position information of the requested priority data is registered in the priority queue area 108 by the LRU method (step 311), and the data transfer processing (step 312) is performed, and the processing is completed.

In the case of a cache miss, it is determined whether there is an empty segment in the cache memory 105 (step 303). If there is an empty segment, the requested priority data is transferred to the disk drive 103.
, And writes it to the cache memory 105 (step 306). However, the cache memory 10
In the case where there is no empty segment in No. 5, data to be discarded from the cache memory 105 is selected from the general queue area 109 by the LRU method (step 30).
4) The segment position information of the selected data is deleted from the general queue area 109 (step 305), the requested priority data is loaded from the disk drive 103, and written on the cache memory 105 (step 306). At the same time, it is determined whether there is a free space in the priority queue area 108 (step 307). If there is a free space, the segment position information of the requested priority data in the priority queue area 108 is registered by the LRU method (step 311). If there is no free space in the priority queue area 108, the segment position information of the data to be moved to the general queue area 109 is stored in the priority queue area 1
08 is selected by the LRU method (step 308), moved to the head of the general queue area 109 (step 309), and the segment position information of the requested priority data is registered in the priority queue area 108 by the LRU method (step 311). ), Data transfer processing (step 31)
2) is performed, and the process ends.

Next, an outline of data processing when the disk subsystem of this embodiment automatically determines priority data will be described with reference to FIGS. 1 and 2. FIG. FIG. 2 shows an example of the data structure of the slot information management table 201 in the cache control unit 106, which has a number of slot information 202 corresponding to the number of slots (segments). Further, the slot information 202 includes the time area 20
3 and information of the count area 204.

If the priority queue area 108 has not reached the upper limit 111 of the priority data capacity, the CPU
The segment position information of the data for which an access request has been made from 101 (hereinafter referred to as “request data”) has a cache hit /
Regardless of the mistake, it is registered at the head of the priority queue area 108 and is treated as priority data. Further, the slot information management table 20 corresponding to the registered segment positions
The value indicating the current time is put in the time area 203 of the slot information 202 in 1 and the value of the count area 204 (the count value 204a) is cleared to zero. The above process is repeated until the priority queue area 108 reaches the upper limit value 111 of the priority data capacity.

When the requested data hits the cache in the general queue area 109 when the priority queue area 108 has reached the upper limit value 111 of the priority data capacity, the slot information 20 corresponding to the requested data is obtained.
The count value 204a of the count area 204 in 2 is incremented, and this count value 204a is compared with a priority data threshold N (hereinafter, threshold).

When the count value 204a exceeds the threshold value, the time area 203 in the slot information 202
, The current time, and the count value 204a to determine the access period (T), and furthermore, the priority data scheduled to be moved from the priority queue area 108 to the general queue area 109 is LR.
In the U method, the access period (t) is obtained from the slot information 202 corresponding to the priority data and the access period (t) is obtained and compared in the same manner as described above. In the short case, the segment position information of the request data is registered in the priority queue area 108 by the LRU method, and the segment position information of the priority data selected earlier is stored in the general queue area 10.
9 by the LRU method. Also, a value indicating the current time is entered in the time area 203 of the slot information 202 corresponding to the segment position information registered in the general queue area 109, and the count value 204a is cleared to zero. Conversely, when the access period (T) of the request data is longer than the access period (t) of the priority data, the segment position information of the request data is transferred to the general queue area 109 by the L.
Registered by the RU method, a value indicating the current time is put in the time area 203 of the corresponding slot information, and the count value 2
04a is cleared to zero.

When the count value 204a is equal to or less than the threshold value, the segment position information of the request data is registered in the general queue area 109 by the LRU method.

If the request data has a cache hit in the priority queue area 108, the slot information 2
The count value 204a of 02 is incremented, and the segment position information is registered in the priority queue area 108 by the LRU method.

In the case of a cache miss, the segment position information is registered in the general queue area 109 by the LRU method, the value indicating the current time is entered in the time area 203 of the corresponding slot information 202, and the count value 20
4a is cleared to zero.

The slot information 202 corresponding to the segment position information of the priority queue area 108 updates the time area 203 at the cycle T and clears the count value 204a to zero, thereby changing the access cycle information of the priority data to the change of the access state. Can be made to correspond.

A detailed example of the above-described automatic determination processing of priority data is shown in the flowchart of FIG. Hereinafter, the flowchart of FIG. 4 will be briefly described.

When the request data is received, it is determined whether or not the upper limit value 111 of the priority data capacity is other than zero and the priority queue area 108 exists, and whether or not the priority data should be automatically determined (step 401). Is not automatically discriminated, the segment position information is stored in the general queue area 109 (step 402), the data transfer process (step 428) is performed, and the process ends.

When the upper limit value 111 of the priority data capacity is not zero and the priority queue area 108 is set to be valid and priority data is to be automatically determined and processed, a cache hit / miss determination of request data (step 403). In the case where a cache miss has occurred, the request data is determined to be general data, the request data is loaded into the cache memory 105 (step 404), and the value indicating the current time is stored in the time area 203 of the slot information 202. Is entered (step 405), and the count value 204a of the count area 204 is cleared (step 4).
06), the segment position information is registered in the priority queue area 108 or the general queue area 109 according to the empty state of the priority queue area 108 (step 407) (steps 408 and 409), and the data transfer processing is performed (step 428).

In the case of a cache hit,
The queue area in which a cache hit has occurred is determined (step 410). If a cache hit has occurred in the priority queue area 108, the count value 204a of the count area 204 of the slot information 202 is incremented (step 426), and the priority queue area 108 To LR
After updating by the U method (step 427), a data transfer process is performed (step 428).

When a cache hit occurs in the general queue area 109, the count value 204a of the slot information 202 is incremented (step 415).
It is determined whether or not the count value (a) exceeds the threshold value (step 416). If not, the segment position information is registered in the general queue area 109 (step 42).
5) Perform data transfer processing (step 428).

If it exceeds, the access cycle (T) is further obtained from the value of the time area, the current time and the count value 204a (step 417), and the priority queue area 10
8, priority data (b) to be discarded is selected by the LRU method (step 418), and the selected priority data (b)
Is obtained in the same manner as described above (step 419). The two access periods thus obtained are compared (step 420). If the access period (t) of the priority data (b) is shorter, a value indicating the current time is stored in the time area 203 of the slot information 202 of the request data. (Step 423), the count value 204a of the count area 204 is cleared to zero (step 424), the segment position information is registered in the general queue area 109 (step 425), and the data transfer process is performed (step 42).
8).

If the access period (T) of the request data is shorter, the segment position information of the request data is registered in the priority queue area 108 (step 421), and the segment position information of the priority data (b) selected earlier is registered. Is registered in the general queue area 109 (step 422), and data transfer processing is performed (step 428).

As described above, according to the present embodiment, the priority queue area 108 and the general queue area 109 are separately set in the queue management table 107 for managing the cache memory 105, so that higher-speed processing can be performed. The required priority data is managed in the priority queue area 108, so that the stay time becomes longer. For example, the ratio is affected by the ratio of the entire data storage capacity of the disk drive 103 to the capacity of the cache memory 105. Thus, the hit rate of the specific priority data in the cache memory 105 can be maintained higher than other general data.
In other words, various hit rates can be maintained and managed according to the priority of data.

As a result, even when the storage capacity of the cache memory 105 is smaller than the entire storage capacity of the disk drive 103 in the disk subsystem, or in a system that performs a large amount of data processing, data desired by the system It is possible to increase the cache hit ratio for frequently-used data.

Further, the ratio of the priority data capacity on the cache memory 105 to the data capacity requiring high-speed data processing can be freely set between 1: 1 and 1: N, and the high performance and large capacity with high availability Can be constructed.

The invention described in the claims of the present application is expressed in another way as follows.

<1> In a data processing system composed of a central processing unit and a disk subsystem, a cache memory which is connected to the central processing unit and temporarily holds data requested to be accessed by the central processing unit; In a disk subsystem composed of a cache control unit for controlling the data and a disk drive for storing data, of data requested to be accessed by the central processing unit, data requiring high-speed data processing (priority data) ) And other data (general data) on the cache memory are managed separately by the cache control unit.
It has a function to perform high-speed data processing by improving cache hit ratio by realizing long-term retention of priority data in cache memory and reducing access to disk drives due to cache misses. Data processing system.

<2> The priority data is set by the system user, and the position (segment position) in the cache memory where the set priority data is stored is stored in the queue management area of the priority data in the queue management table. (1) The data processing system according to item <1>, wherein the data processing system is managed in (priority queue area).

<3> Among the data requested from the central processing unit, the disk subsystem automatically determines data having a high request frequency according to the priority criteria specified by the system user, and stores the segment position information in the priority queue. The data processing system according to item <1>, wherein the data processing system is registered in an area.

<4> The data processing system according to item <1>, wherein the system user determines an upper limit of the priority data capacity occupying the cache memory capacity.

<5> When the set priority data capacity exceeds the upper limit of the priority data capacity, the segment position information of the priority data to be discarded from the priority queue by the LRU method is transferred to the general data queue management area (general data). Item <1 characterized by being registered at the head of the queue area)
> The data processing system described in the above.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is.

For example, in the above description, the case where the priority of data in the cache memory is managed in two stages of the priority queue area and the general queue area has been described.
The present invention includes the setting and management of the queue area at more than one stage.

[0055]

According to the present invention, a cache memory is provided by maintaining a high cache hit ratio of high-priority data without being affected by a relative decrease in the cache memory capacity with respect to the total data amount. And the data processing performance of the system can be improved.

According to the present invention, an effect is obtained that an optimum cache hit ratio can be realized according to the priority for each data having different processing priority.

According to the present invention, the cache hit rate is improved by managing the cache memory so that data requiring high-speed data processing is retained in the cache memory for a long period of time. An effect is obtained that high-speed data processing can be realized by minimizing a decrease in data processing performance.

According to the present invention, the priority data capacity in the cache memory and the data capacity requiring high-speed data processing are variably realized in the range of 1: 1 to 1: N, so that large-capacity data with high availability can be obtained. The effect that the construction of the processing system can be realized is obtained.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an example of a configuration of a data processing system including a disk subsystem as an example of a storage subsystem that implements a cache memory control method according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of control information held in a storage subsystem that executes a cache memory control method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an example of an operation of a storage subsystem that executes a cache memory control method according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating an example of an operation of a storage subsystem that executes a cache memory control method according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating an example of an operation of a storage subsystem that implements a cache memory control method according to an embodiment of the present invention.

[Explanation of symbols]

101 central processing unit (CPU) (first device), 102
... Disk subsystem (storage subsystem) 103
··· Disk drive (second device) · 104 · Data processing control unit · 105 · Cache memory · 106 · Cache control unit · 107 · Queue management table · 108 · Priority queue area (first management information) · 109 · General queue area (Second management information), 110: slot information management table, 111: upper limit of priority data capacity, 201: slot information management table, 202: slot information, 203:
Time area in slot information, 204: count area in slot information.

Claims (5)

[Claims] 1. A method of controlling a cache memory interposed between a first device and a second device and temporarily storing data exchanged between the first device and the second device. Partitioning the cache management information for managing the cache memory into at least two pieces of first and second management information, and selectively using a plurality of the first and second management information according to the priority of the data. Wherein the staying time of the data having higher priority in the cache memory is made longer. 2. The cache memory control method according to claim 1, wherein the higher priority first data is managed by the first management information, and the lower priority second data is managed by the second management data.
The amount of the first data occupying in the cache memory is changed by managing with management information and changing a ratio of the first management information and the second management information in the cache management information. How to control the cache memory to use. 3. The cache memory control method according to claim 1, wherein a ratio between the first management information and the second management information in the cache management information is set by an external instruction. Operation, a second operation for identifying the first data having the higher priority according to a determination method instructed from outside, automatically determining the data having a higher request frequency, and assigning the data to the priority A third operation to be treated as the first data having a higher degree; when the specific first data managed by the first management information is evicted from the cache memory, the first operation is performed.
By causing the cache management information relating to the first data of the management information to be passed to the highest priority position of the second management information, the fourth data that causes the first data to stay in the cache memory as the second data A method of controlling a cache memory, wherein at least one of the following operations is performed. 4. A storage sub-unit comprising: a storage device; and a storage control device having a cache memory for controlling transmission and reception of data between the storage device and a host device and for temporarily storing the data. In the system, the cache management information for managing the cache memory is divided into at least two pieces of first and second management information, and a plurality of pieces of the first and second management information are determined according to the priority of the data. A storage logic comprising a control logic for making the staying time of the data having higher priority in the cache memory longer by selectively using the data. 5. The storage subsystem according to claim 4, wherein the control logic manages the higher priority first data by the first management information, and stores the lower priority second data. The second
A first function of managing the management information and changing a ratio of the first management information and the second management information in the cache management information to change an amount of the first data occupying the cache memory; A second function of setting a ratio between the first management information and the second management information in the cache management information in response to an instruction from the outside; A third function of identifying the first data having a higher priority; a fourth function of automatically determining the data having a higher request frequency and treating the data as the first data having a higher priority; When the specific first data managed by the management information is evicted from the cache memory, the first
Fifth, causing the first data to stay in the cache memory as the second data by causing the cache management information relating to the first data of the management information to be passed to the highest priority position of the second management information. A storage subsystem having at least one function of: