JPH07129464A - Information processor - Google Patents

Abstract

PURPOSE:To improve use efficiency for a cache memory by changing cache memory control information corresponding to the character of an application program to be executed. CONSTITUTION:This device is provided with a main memory 608 for storing information related to an instruction to be executed and data to be processed, instruction processing unit 502 for processing the information according to the information stored in the main memory 608, cache memory 300 for storing a part of information stored in the main memory 608, method register 100 for storing optimum cache memory control information according to the contents of the application program, and memory control unit 400 for controlling the transfer of information between the main memory 608 and the cache memory 300 according to the cache memory control information stored in the method register 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to an information processing apparatus suitable for controlling transfer of information between a main storage device and a cache memory.

[0002]

2. Description of the Related Art In a conventional information processing apparatus, in order to prevent performance degradation due to access to a large capacity but slow main memory, performance is improved by using a small capacity but high speed cache memory. The method of raising is adopted. In a conventional information processing apparatus of this type, a main memory device and a memory control unit are connected by a bus line, a memory control unit and an instruction processing unit are connected by a bus line, and a memory control unit and a cache memory are further connected. Is adopted to connect with a bus line. When transmitting commands and data in this type of apparatus, a store-through method, a copy-back method, etc. are adopted.

In the store-through method, when writing data, after writing the data in the cache memory, the data is also written in the main storage device. On the other hand, in the copy-back method, at the time of writing data, while the data written in the cache memory remains in the cache memory, the writing of data to the main storage device is not executed.

Further, when necessary instructions or data are not present in the cache memory when reading the instructions or data,
A method is adopted in which necessary instructions or data are read from the main storage device and written in the cache memory.
In this case, if there is data that has not been written in the main storage device in the write area of the cache memory, the data is written in the main storage device. In order to efficiently transfer data between the cache memory and the main storage device, information composed of several adjacent instructions or data is transferred in block units. Note that the fetch-on-write method and the write-around method are used when writing data.

On the other hand, in an information processing apparatus having a plurality of processors each having an instruction processing unit, a memory control unit and a cache memory, and each processor sharing a single main memory device, when the block size is not optimal. In order to prevent the cache memory usage efficiency from decreasing, a method of dynamically adjusting the block size is adopted. That is, a size register for storing the size of each block and a history register for storing history information of access to each block are provided in the cache memory of each processor, and the memory control unit of each processor responds to a request from the instruction processing unit. When the cache memory is accessed by the cache memory, whether the access is to the first half or the second half of the corresponding block is recorded in the history register. When writing data, check the history registers of all the processors owned by the cache memory for the data at that address, and find the processor that accessed both the first half and the second half of the block. For example, the counter corresponding to the block is decremented by -1, and if there is a processor that has accessed only the first half or the second half, the counter is incremented by -1 and recorded in the history register. When the counter value exceeds a certain value, it is determined that the block size is too large, and when the data transfer between the cache memory is performed, the block is divided and the value of the size register is updated. . On the other hand, when the value of the counter becomes smaller than a certain value, it is determined that the size of the block is too small, and when the data transfer between the cache memory and the cache memory is performed, the block is connected to the adjacent block,
Update the size register value. In this way, the size of each block is adjusted to an optimum value using the history information of access to the cache memory.

[0006] Examples of the information processing apparatus of this type include JP-A-62-197842 and JP-A-4-336340.

[0007]

In the conventional information processing apparatus, when the amount of instruction or data is large, the required instruction or data cannot be stored in the cache memory, and the instruction or data is stored between the main storage device and the cache memory. Frequent data transfers. In particular, when processing huge array data for scientific and technological calculations, when processing the first half of the array, the cache memory contains the latter half of the array, and when processing the latter half of the array, the cache memory contains It often happens that the first half of the array is included. In such a case, the data required for any processing does not exist in the cache memory, and therefore, it is necessary to always transfer the data to and from the main storage device, so that the usage efficiency of the cache memory is extremely high. descend.

Further, in the conventional apparatus, when executing the application program, sufficient consideration is not given to whether or not the cache memory is used. That is, generally, when executing any application program, there are instructions or data that are frequently used and instructions or data that are not frequently used. In such a case, if an infrequently used instruction or data is unconditionally written in the cache memory, an infrequently used instruction or data may be expelled from the cache memory, which may reduce the efficiency of use of the cache memory. Furthermore, when data transfer is performed between the main storage device and the cache memory, the size of the block serving as the transfer unit may not be optimum for the application program to be executed. That is, in general, efficient transfer can be achieved by transferring a large amount of data at a time, and therefore performance is improved by increasing the block size. However, if independent variables are lined up and it is unlikely that adjacent data will be used consecutively, then if the block size is large, data that is unlikely to be used in the near future will be transferred together, and performance will be rather increased. Is reduced. This is also the case when transferring instructions. For example, when executing an application program in which branch instructions occur less frequently, there is a high possibility that instructions with consecutive addresses will be executed. Therefore, it is better to increase the block size. Conversely, the frequency of occurrence of branch instructions is high. In this case, it is better to reduce the block size. As described above, when an instruction or data is transferred between the main memory device and the cache memory, unless the block size is adjusted to the optimum state, the use efficiency of the cache memory is reduced.

When adjusting the block size,
In the method of storing the size and history information of each block,
There is also a problem that the physical quantity of hardware increases, the processing of the memory control unit becomes complicated, and the processing speed decreases.

An object of the present invention is to provide an information processing apparatus capable of improving the efficiency of use of the cache memory by changing the control method of the cache memory according to the contents of the application program to be executed.

[0011]

In order to achieve the above object, the present invention provides, as a first device, a main storage means for storing information on an instruction to be executed and data to be processed, and the main storage means. Command processing means for processing the data stored in the main storage means, a cache memory for storing a part of the information stored in the main storage means, and a cache memory according to an application program. Information including control information storage means for storing control information, and memory control means for controlling transfer of information between the main storage means and the cache memory according to cache memory control information stored in the control information storage means The processing device is configured.

As a second device, a main storage means for storing an instruction to be executed and information on data to be processed, and data stored in the main storage means in accordance with the instruction stored in the main storage means. Command processing means for processing, cache memory for storing a part of the information stored in the main storage means, control information storage means for storing a plurality of cache memory control information according to an application program, and the control information storage Configuring an information processing apparatus including memory control means for controlling transfer of information between the main storage means and the cache memory according to designated cache memory control information of the cache memory control information group stored in the means Is.

In each of the above devices, the cache memory has a plurality of memory areas corresponding to a block size indicating a transfer unit of information, and write control means for storing the information in a designated memory area according to the block size. The cache memory control information stored in the control information storage means can be configured to include information regarding a block size suitable for transfer as a block size indicating a transfer unit of information.

The memory control means has a prefetch control means for predicting an address of information required in the future and controlling transfer of information according to the prediction result. The cache memory control information stored in the control information storage means is: The prefetch control means may include information specifying the transfer amount of information to be transferred at one time.

As the memory control means that responds to the read request, the memory control means exchanges information with the cache memory when the information read request is received from the instruction processing means, and the specified information exists in the cache memory. And a transfer control unit that controls transfer of information according to the determination result of the determination unit and the cache memory control information stored in the control information storage unit, and is stored in the control information storage unit. The generated cache memory control information can be configured to include information indicating whether or not the designated information should be transferred from the main storage means to the cache memory when the designated information does not exist in the cache memory.

As memory control means for responding to a write request, the memory control means exchanges information with the cache memory when the information write request is received from the instruction processing means, and the specified information exists in the cache memory. And a transfer control unit that controls transfer of information according to the determination result of the determination unit and the cache memory control information stored in the control information storage unit, and is stored in the control information storage unit. The generated cache memory control information can be configured to include information indicating whether or not the designated information should be transferred from the main storage means to the cache memory when the designated information does not exist in the cache memory. Further, the memory control means, when receiving the information write request from the instruction processing means, transfers the specified information to the cache memory, and stores the information according to the cache memory control information stored in the control information storage means. And a cache control information stored in the control information storage means, which has a transfer control means for controlling transfer.
Indicates whether the specified information to be stored in the cache memory should be written to the main memory, or whether the specified information stored in the cache memory is prohibited from being written to the main memory. It can be configured to include information.

Further, the control information storage means has a storage area group for respectively storing the cache memory control information divided into a plurality of parts, and the instructions divided according to the frequency of branch instructions are stored in the storage area group. Data is stored in any of the storage areas of the above, and the data divided according to the frequency of use is stored in the storage area different from the instruction in the storage area group. can do. Further, the control information storage means has a plurality of storage areas for respectively storing different cache memory control information,
A plurality of address range determining means for receiving an address from the instruction processing means for determining whether or not the address is within the range of addresses set corresponding to each storage area, and an affirmative determination from the designated address range determining means. And a plurality of information output means for selecting and outputting cache memory control information from a designated storage area on condition that a result is obtained and a negative determination result is obtained from other address range determining means. can do.

In the first or second device, the cache memory is composed of a plurality of memories having different response speeds, and the memory control means controls transfer of information between the main storage means and one of the cache memories. It can be configured by controlling transfer of information between each cache memory. Further, the cache memory is composed of an instruction cache memory and a data cache memory, and the control information storage means includes an instruction control information storage means for storing instruction control information among the cache memory control information and a cache memory control information. The memory control means controls transfer of information between the instruction cache memory and the main storage means, and the data control information storage means for storing the data control information. It may be configured by controlling transfer of information.

[0019]

According to the above-mentioned means, when the optimum cache memory control information is stored in the control information storage means according to the application program, the main storage means and the cache are stored in accordance with the cache memory control information stored in the control information storage means. The transfer of information between memories is controlled.
Therefore, the memory control means can perform optimum information transfer control according to the application program to be executed.

Further, when controlling the transfer of information between the main storage means and the cache memory, when a plurality of cache memory control information is stored in the control information storage means, the optimum cache memory control information according to each application program is obtained. And the transfer of information between the main storage means and the cache memory can be controlled according to the selected cache memory control information.

When storing the optimum cache memory control information, it is possible to store it in consideration of the access tendency of the application program and various parameters of the hardware. In this case, as the cache memory control information, the block size indicating the transfer unit of information, the information about the block size suitable for the transfer, the information specifying the transfer amount of the information to be transferred at one time by the prefetch control unit, or the cache memory Information indicating whether or not the designated information should be transferred from the main storage means to the cache memory when the designated information does not exist in the
Further, when writing information, should the designated information to be stored in the cache memory also written to the main storage means, or write the designated information to the main storage means while the designated information stored in the cache memory is valid. It is possible to store information indicating whether to prohibit.

By setting the optimum cache memory control information based on these pieces of information, the application program can be efficiently executed.

For example, when executing a program with many branch instructions or a program that randomly accesses discrete variables, the block size and the number of prefetches are reduced. On the other hand, when executing a program with a small number of branch instructions or a program that continuously accesses an array, the block size and the number of prefetches are increased.

If the capacity of the cache memory is small and the time required to transfer information from the main storage means to the cache memory is short, the block size and the number of prefetches are reduced. On the other hand, if the cache memory has a large capacity and the time required to transfer information from the main storage unit to the cache memory is long, the block size and the number of prefetches are increased.

When the cache memory control information is set according to the optimum condition, the optimum amount of data can be transferred,
It is possible to prevent performance deterioration due to unnecessary data transfer.

Further, it is possible to prevent an infrequently used instruction or data from being written in the cache memory, and prevent an infrequently used instruction or data from being expelled from the cache memory. The usage efficiency of is improved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention. In FIG. 1, the information processing apparatus includes an instruction processing unit 502, a memory control unit 400, a cache memory 300, a method register 100, and a main storage device 6.
08 is configured. A main memory device (hereinafter, referred to as main memory) 608 is configured as a main memory unit that stores information regarding instructions to be executed and data to be processed, and memory control is performed via a control bus 816 and a data bus 818. It is connected to the unit 400. The cache memory 300 is configured to store a part of the instructions and data stored in the main memory 608, and is connected to the memory control unit 400 via the control bus 810 and the data buses 812 and 814. The instruction processing unit 502 is configured as an instruction processing unit that processes the data stored in the main memory 608, and has a control bus 80.
2, 804 to the method register 100, and the control bus 804 and the data bus 806 to the memory control unit 400. The method register 100 is configured as a control information storage unit that stores cache memory control information according to an application program, and is connected to the memory control unit 400 via a control bus 808. The memory control unit 400 is configured as a memory control unit that controls transfer of information between the main memory 608 and the cache memory 300 according to the cache memory control information stored in the method register 100.

The instruction processing unit 502 includes a control bus 8
04 and the data bus 806, it receives an instruction from the memory control unit 400 and executes a process according to the instruction. If the instruction executed at this time is an instruction that requires reading or writing of data with respect to the main memory 608, a request for reading or writing of data is issued to the memory control unit 400 via the control bus 804, Required data is transferred via the data bus 806. On the other hand, when the executed instruction is an instruction to write to the method register 100, the control bus 8
The designated data is written to the method register 100 via 02. In the method register 100, the instruction processing unit 502 is arranged in the memory control unit 400 via the control bus 804.
The address of the command or data requested to the memory control unit 400 is received via the control bus 808 and the cache memory control information corresponding to the address is received.
Transfer to. At this time, the memory control unit 400
According to the cache memory control information received via the control bus 808, the transfer of instructions or data between the instruction processing unit 502, the cache memory 300 and the main memory 608 is controlled. That is, the cache memory 30
0 indicates the memory control unit 4 via the control bus 810.
00 to output the corresponding instruction or data to the data bus 814. In addition, the control bus 8
When a write instruction is given via 10, the instruction or data received via the data bus 812 is written to the designated location. Further, the main memory 608 receives a read or write request of an instruction or data via the control bus 816. When a command or data read request is received, the necessary command or data is output to the data bus 818. On the other hand, when a data write request is received, necessary data is received via the data bus 818, and this data is written in a designated location.

FIG. 2 is a diagram showing a first embodiment of the method register 100. In FIG. 2, the method register 100 is provided with a register 112 for storing optimum cache memory control information, and the storage area of this register 112 is divided into a plurality of areas. That is, the register 112
Storage area of the block size (BKS) 102, number of prefetches (NPF) 104, and caching selection (C
/ N) 106, copy back selection (C / S) 108, and fetch-on-write selection (F / W) 110 are stored. Block size 102
Specifies a block size indicating a transfer unit when transferring an instruction or data between the main memory 608 and the cache memory 300. Prefetch number 10
The number 4 designates the number of blocks of instructions or data to be prefetched when performing hardware prefetching. The caching selection 106 specifies whether or not to transfer the block to the cache memory 300 when the instruction or data necessary for reading the instruction or data is not present in the cache memory 300. The copy-back selection 108 is designed to specify which of the copy-back method and the store-through method is selected when writing data. The fetch-on-write selection 110 specifies whether to select the fetch-on-write method or the write-around method when the cache memory 300 does not have the necessary data for writing the data.

The method register 100 in the above configuration is
When the write request 824 is received from the instruction processing unit 502, the write data 822 is written in the register 112. Then, the data written in the register 112 is transferred to the memory control unit 400 via the control bus 808. In this case, in this embodiment, since only one cache memory control information can be stored in the method register 100, the same cache memory control information is used for control regardless of the value of the address received via the control bus 804. It will be output to the bus 808.

FIG. 3 is a diagram showing a first embodiment of the cache memory 300. In FIG. 3, the cache memory 3
00 has three memories 311 to 313 corresponding to different block sizes as a plurality of memory areas corresponding to the block size indicating the transfer unit of information, and data specified in each memory according to the block size. A control circuit 302 is provided as a write control means for storing the. Further, selection circuits 304 and 306 for selecting designated data from the memories 312 and 313 are provided.

The memories 311 to 313 each have an area for storing information of a plurality of blocks, and each block has a tag area 321 to 323 and a data area 331, 3 respectively.
It is composed of 41 to 342 and 351 to 354. The tag area stores the upper bits of the address corresponding to the block, and the data area stores the instruction or data corresponding to the block. And the memory 31
1 to 313 select one block from a plurality of blocks included in each memory according to the lower bits 846 to 848 of the address 834 received via the control bus 810, and tag information 861 to 863 of the block and Command or data 866-868 is transferred to the data bus 814
Output to. At this time, since the memory 312 includes two instructions or data in each block, the selection circuit 304 selects and outputs the instruction or data corresponding to the address 834. Similarly, since the memory 313 includes four instructions or data in each block, the selection circuit 306 selects and outputs the instruction or data corresponding to the address 834. Then, when the values of the tag information 861 to 863 output from the memories 311 to 313 match the upper bits of the address 834, the requested instruction or data corresponds to the memory 311.
˜313 exists, and when they do not match, it does not exist. In addition, this determination, as described later,
This is performed by the memory control unit 400.

On the other hand, the control circuit 302 controls the write request 83.
2 is fetched, and write control signals 841 to 843 for the memories 311 to 313 are output. When the write control signals 841 to 843 are fetched, the memory 3
11 to 313 fetch the tag information 851 to 853 and the instruction or data 856 to 858 from the data bus 812, and store them in the block designated by the lower bits 846 to 848 of the address 834.

FIG. 4 is a block diagram of the memory control unit 400. In FIG. 4, a memory control unit 400
Is a transfer control circuit 402, a prefetch control circuit 404,
Selection circuit 406, address conversion circuit 408, cache memory interface 410, hit determination circuit 41
2, data buffer 414, main memory interface 4
16 is provided. The selection circuit 406 outputs the address 874 output from the instruction processing unit 502 and the address 87 output from the prefetch control circuit 404.
Either one of the eight addresses is selected. Then, when the instruction or data is transferred according to the request of the instruction processing unit 502, the address 874 is selected. On the other hand, when performing the prefetch process in which the instruction processing unit 502 predicts an instruction or data required in the future and transfers it in advance, the address 878 is selected.
The address selected by the selection circuit 406 is transferred to the address conversion circuit 408 as the address 880. The address conversion circuit 408 performs address conversion on the address 880 and outputs the converted address 886. The address 880 at this time is an address used when the instruction processing unit 502 accesses an instruction or data, and is called a normal (logical address). On the other hand, the address 886 after the address conversion is
It is an address used when accessing the main memory 608 and is usually called (physical address).

The address 886 output from the address conversion circuit 408 is the cache memory interface 41.
0 and transferred to the main memory interface 416. The control information 882 from the transfer control circuit 402 is input to the cache memory interface 410. Upon receiving the request 872 from the instruction processing unit 502, the transfer control circuit 402 controls the cache memory interface 410 or the main memory interface 416 to transfer necessary instructions or data. The hit determination circuit 412 also compares the tag information 861 to 863 received from the cache memory 300 via the data bus 814 with the upper bits of the address to determine whether the required instruction or data exists in the cache memory 300. It is designed to judge. The prefetch control circuit 404 receives the address 874 from the instruction processing unit 502 and predicts the address of an instruction or data that will be needed in the future. And as a result,
When it is determined that the instruction or data needs to be transferred from the main memory 608 to the cache memory 300, the transfer request 876 is output to the transfer control circuit 402, and at the same time, the address 878 of the instruction or data to be transferred is output. Has become. The data buffer 414 is configured as a register that temporarily stores the instruction or data being transferred when the instruction or data is transferred.

Here, in the prefetch control circuit 404, many methods are conceivable as a method of predicting an address of an instruction or data which will be needed in the future. For example, one method is that the next block of the instruction or data requested by the instruction processing unit 502 is the cache memory 30.
It is a method of checking whether it exists in 0, and if not, transferring the block to the cache memory 300 in advance. In this case, usually, there is a high probability that the next address of the accessed instruction or data will be accessed in the near future. Therefore, even with such a simple method, some effect can be expected. However, in this method, it is necessary to check whether or not the next block exists in the cache memory 300 for all the requests from the instruction processing unit 502, and the number of accesses to the cache memory 300 may increase more than necessary. is there. Therefore,
As a method for solving such a problem, it is necessary to check whether or not the next block exists in the cache memory 300 only when the necessary instruction or data in the request from the instruction processing unit 502 does not exist in the cache memory. Methods can also be used. In this case, the cache memory 3
Since there is a high probability that the next block of an instruction or data that is not in 00 is not in the cache memory 300, prefetching can be efficiently performed using this method.

However, the above two methods are not necessarily effective in the case of accessing data distributed at regular intervals such as array data. Even in such a case, as a method of effectively performing prefetch, a method of storing an address difference between a plurality of accesses and predicting an address to be accessed next based on the difference can be used. If this method is used, a complicated prediction circuit is required, but more accurate prediction can be performed.

Next, the operation when the memory control unit 400 receives a command or data read request from the command processing unit 502 will be described with reference to FIG.

First, when the memory control unit 400 receives a command or data read request, it is determined whether or not the necessary command or data is in the cache memory 300 (step 702). When it is determined by the hit determination that the necessary instruction or data exists in the cache memory 300, the instruction or data output from the memory whose tag information matches the upper bit of the address is received via the data bus 814, This data is transferred to the instruction processing unit 502 (step 70).
6). This is cache read.

On the other hand, as a result of hit determination in step 702, the necessary instruction or data is found in the cache memory 30.
When it is determined that the value is not 0, the value of the caching selection (C / N) 106 in the cache memory control information received from the method register 100 is checked. When the value of the caching selection 106 is 1, the main memory 60
The instruction or data specified by the block size (BKS) 102 is read from the memory 8 and this data is stored in the memory 311.
Write to the memory corresponding to the value designated by the inner block size 102 of 313 to 313. At this time, at the same time, the instruction or data for the address requested by the instruction processing unit 502 is transferred to the instruction processing unit 502 (step 7).
08). This is block transfer.

Here, when performing the block transfer 708,
Care must be taken when the size of the instruction or data read from the main memory 608 is large. For example, when the size to be read is the size of one block in the memory 313, the instruction or data corresponds to four blocks in the memory 311, but the hit determination is made only for one of the blocks. Therefore, from the main memory 608 to the memory 313
When the instruction or data is transferred to the memory, the memory 311 and the memory 313 may include the instruction or data of the same address. If the copy-back method is adopted here, the value stored in the main memory 608 may not be the latest value in the copy-back method.
The value transferred to 13 may not be the latest value. Therefore, when transferring data to and from the cache memory 300, such a case is taken into consideration, and when a plurality of memories include data of the same address, a memory having a smaller block size is used. You need to transfer data between.

On the other hand, when transferring instructions, even if a plurality of memories include an instruction of the same address,
Since the values stored in both are the same, the instruction may be read from either memory. There is also a method of preventing instructions or data having the same address from being included in a plurality of memories. According to this method, when an instruction or data is transferred from the main memory 608 to the memory 312 or 313,
It is necessary to check whether there is an instruction or data having the same address in a memory having a smaller block size. If there is a corresponding instruction or data, the instruction or data in the memory with the smaller block size is invalidated, and if any of the invalidated data is not written in the main memory 608, Transfer the data to the memory with the larger block size. By performing such processing, it is possible to prevent the two memories from containing instructions or data having the same address.

In step 704, the caching selection 106
When it is determined that the value of is 0, only the instruction or data corresponding to the requested address of the instruction processing unit 502 is read from the main memory 608 and transferred to the instruction processing unit 502 (step 710). This is word transfer.

When the cache read in step 706 and the block transfer in step 708 are completed, a process for checking the prefetch number (NPF) 104 is performed (step 712). At this time, if the prefetch number 104 is larger than 0, the prefetch control circuit 404 starts the prefetch process (step 714). This is the prefetch activation. The amount of instruction or data to be transferred at the time of prefetch is determined based on the block size 102 and the number of prefetches 104. When the prefetch control circuit 404 starts the prefetch processing, the transfer control circuit 402 can accept the next request from the instruction processing unit 502, and therefore the processing of the prefetch control circuit 404 and the processing of the instruction processing unit 502 are performed in parallel. be able to.

Next, the operation when the memory control unit 400 receives a data write request from the instruction processing unit 502 will be described with reference to FIG.

First, when the memory control unit 400 receives a data write request, the hit determination process is executed as in the read (step 702). As a result of this hit determination, when it is determined that the data of the address to be written exists in the cache memory 300, the data is written to the memory whose tag information matches the upper bits of the address (step 726). This is cache writing.

On the other hand, as a result of the hit determination in step 702, when it is determined that the data of the address to be written is not in the cache memory 300, the fetch-on in the cache memory control information received from the method register 100 is turned on. Check the value of the write selection (F / W) 110. If the value of the fetch-on-write selection 110 is 1, the block size (BK
S) The data of the block size designated by 102 is read, and the data of the address requested by the instruction processing unit 502 is replaced with the data received from the data bus 806. After that, the designated data is written in the memory corresponding to the value designated by the block size 102 among the memories 311 to 313 (step 728). This is block transfer.

When the value of the fetch-on-write selection 110 is 0, the data requested by the instruction processing unit 502 is directly written in the main memory 608, and the processing is terminated (step 736). This is main memory writing.

When the cache write or block transfer processing is completed, the prefetch number (NPF) 104 is checked (step 712), and if necessary, prefetch activation (step 714) is performed. Then, when the prefetch activation is completed, the value of the copyback selection (C / S) 108 is checked. When the value of the copy-back selection 108 is 1, the processing is ended as it is, and when it is 0, the main memory is written and then the processing in this routine is ended.

In the information processing apparatus having the above configuration, in order to efficiently execute the application program, it is necessary to write the optimum cache memory control information for the program into the method register 100. In this case, in general, the optimum cache memory control information depends on both the access tendency of the application program and various parameters of the hardware. Therefore, the optimum cache memory control information is set in the method register 100 in consideration of these. Need to write.

For example, when executing a program having many branch instructions or a program randomly accessing discrete variables, it is better to reduce the block size 102 and the prefetch number 104. On the other hand, when executing a program with a small number of branch instructions or a program that continuously accesses an array, it is better to increase the block size 102 and the prefetch number 104.

If the capacity of the cache memory is small, or if the time required to transfer an instruction or data from the main memory 608 to the cache memory 300 is short, the block size 102 and the prefetch number 104 should be reduced. Is good. On the contrary, if the capacity of the cache memory 300 is large, or if the time required to transfer an instruction or data from the main memory 608 to the cache memory 300 is long, it is better to increase the block size 102 and the prefetch number 104. . Therefore, when starting the application program, the optimum cache memory control information is determined in consideration of these conditions, and the information according to this determination is written in the method register 100 to efficiently execute the application program. Can be executed.

When a plurality of application programs are processed in parallel in a time division manner, when the processing of one program is interrupted and the processing of another program is restarted, the method register 100 stores the restarted program. By writing the optimum cache memory control information to, it becomes possible to perform the optimum control while executing any program.

Next, another embodiment of the present invention will be described.

FIG. 7 is a diagram showing a second embodiment of the method register 100. In FIG. 7, the method register 100 is
Register 1 for storing a plurality of cache memory control information
31 to 13n. A control circuit 112 is provided to store designated control information in each register, and a decoder 124 and a selection circuit 126 are provided to select designated control information from each register. That is, the control circuit 112 controls the instruction processing unit 5
02, the write request 902 is received, and the write control signal 906 is output to the designated register. Then, the write data 904 is stored in the register designated to be written by the write control signal 906.

On the other hand, the decoder 124 uses the control bus 80.
Select signal 9 using a predetermined bit of the address received from instruction processing unit 502 via
08 is generated. The selection circuit 126 selects one control information from the cache memory control information stored in the registers 131 to 13n according to the selection signal 908 from the decoder 124, and outputs this information to the control bus 808.

FIG. 8 is a diagram for explaining correspondence between an address and cache memory control information when the method register 100 of FIG. 7 is used and a method of using the method register 100.

In FIG. 8, when the cache memory control information is stored in the method register 100, the address 32 bits are divided into three parts of 9 bits, 3 bits and 20 bits from the higher order. Then, the decoder 124 uses the 3 bits of the A portion of this address to select the selection signal 90.
Generate 8. In this case, the entire address space is divided into 512 spaces each having a size of 8 Mbytes, and each space is divided into four areas corresponding to A values of 0, 1, 2 to 3 and 4 to 7. . The size of each area is 1 Mbyte, 2 Mbyte, and 4 Mbyte. The size and arrangement of each space and each area are determined by the configuration of the decoder 124. And the method register 100 is 4
Four registers are provided to specify different cache memory control information for each of the two areas.

Next, a method of executing an application program by the information processing apparatus having the method register 100 shown in FIG. 7 will be described.

First, there are two possible methods for writing the cache memory control method to the method register 100. One is a method of writing the optimum cache memory control information for each application program when starting or resuming the execution of the application program, as in the case of using the method register 100 of FIG. In this case, by dividing the instruction and data of the application program into a plurality of parts and allocating each part to a different area in FIG. 8, different cache memory control information can be specified for each.

That is, usually, even for instructions or data included in the same application program, the access tendency differs depending on the address. Therefore, by allocating instructions or data of different characteristics to different areas and specifying the optimum cache memory control information corresponding to each area, it is more efficient than when the same cache memory control information is specified for the entire program. You have good control.

The second method is to use the same cache memory control information in a plurality of application programs. In this method, in advance, assuming application programs that may be executed in the future, determine a plurality of cache memory control information that is considered to be optimal for those programs after considering various parameters of the hardware, This is written in the method register 100. In this case, Table 1 below shows examples of values set in the method register 100.

[0064]

[Table 1]

In the example of Table 1, since the areas 1 and 2 have a small block size (BKS), allocating an instruction or data with a small number of accesses to consecutive addresses reduces unnecessary instruction or data transfer, resulting in poor performance. Is improved. Furthermore,
Since the cache selection (C / N) and the fetch-on-write selection (F / W) in area 2 are 0, if an instruction or data with a low access frequency is assigned, the access frequency will be increased when the instruction or data is accessed. Highly efficient instructions or data are not pushed out of the cache memory, and the performance is improved. Further, since the areas 3 and 4 have a large block size (BSK) and the number of prefetches (NPF), if an instruction or data that frequently accesses consecutive addresses is allocated, the instruction or data that will be needed in the future is stored in the cache memory in advance. It is possible to transfer it, and the performance is improved.

In the case where a large number of unit data of a fixed size are continuous, as in a database, it may be desirable to allocate the block size value to an area equal to the size of the unit data. In general, large array data tend to access many consecutive addresses, and small array data and non-array data tend to access few consecutive addresses. It is advantageous to set it.

The values in Table 1 are set values for an information processing apparatus having a relatively small capacity of the cache memory 300, and are set to small block sizes. If the value is set in an information processing device having a large cache memory capacity, a larger block size improves the performance.

On the other hand, when each application program is started, the optimum cache memory control information is obtained for each part of the instruction or data of the program, and the instruction or data is written in the area where the control information closest to the cache memory control information is written. Allocate data. FIG. 8 shows a specific example of instruction or data allocation at this time.

In FIG. 8, in program 1, an instruction having a high frequency of branch instructions (instruction 1) is assigned to area 1, and an instruction having a medium frequency of branch instructions (instruction 2) is assigned to area 3. In addition, data (data 1) that is used less frequently is stored in area 2.
Array data (data 2) having a high possibility of access to consecutive addresses is assigned to the area 4.

On the other hand, in the program 2, since the frequency of branch instructions is high regardless of the address, all the instructions are assigned to the area 1. Also, array data of small size (data 1) is assigned to area 3, and data of large size (data 2) that frequently accesses consecutive addresses is assigned to area 4. In this way, the application program
By changing the allocation of instructions and data, it is possible to perform optimum control without changing the set value of the method register 100 even when executing a plurality of application programs having different properties. Therefore, when such a method is used, it is not necessary to rewrite the value of the method register 100 when, for example, the execution of the program 1 is interrupted and the execution of the program 2 is restarted. When dividing and processing in parallel, the programs can be switched at high speed.

FIG. 9 is a diagram showing a third embodiment of the method register 100. Method register 100 in this embodiment
Has a plurality of storage areas for respectively storing different cache memory control information, and an address is set corresponding to each storage area in order to select the cache memory control information stored in each storage area. It is determined whether or not it is within the range of the specified address, the designated cache memory control information is selected from the designated storage area according to the determination result, and the selected cache memory control information is output. That is, the method register 100 is the control circuit 2
02 and a plurality of storage circuits (for example, registers) 211 to 21n. The storage circuits 211 to 21n are provided with registers 241 to 24n for storing cache memory control information and registers 221 to 22 for storing a lower limit address.
Registers 231 to 23m for storing m and the upper limit address are provided. Then, when the control circuit 202 receives the write request 912 via the control bus 802, the control circuit 202 outputs the write control signal 916 in order to write the data in the designated storage circuit. And the register 221
-22m, registers 231-23m, registers 241-
The 24n, when instructed to write by the write control signal 916, takes in the write data 914 and stores it.

On the other hand, each of the memory circuits 211 to 21m stores cache memory control information corresponding to a designated address range. The memory circuit 21n also stores cache memory control information when the address is not within the range specified by the memory circuits 211 to 21m. That is, the register 24n of the memory circuit 21n stores cache memory control information corresponding to an address in a range not designated by the address of another memory circuit.

Next, as the operation of this method register, the operation of the memory circuit 211 will be described first. Memory circuit 2
The comparator 251 of 11 includes a register 22 and a predetermined bit of an address received via the control bus 804.
The lower limit address stored in 1 is compared, and if it is equal to or higher than the lower limit address, the comparison result 921 is set to 1, and if not, it is set to 0. On the other hand, the comparator 261 compares a predetermined bit of the address with the upper limit address stored in the register 231, and when the address is smaller than the upper limit address, sets the comparison result 931 to 1, and otherwise sets it to 0. The comparison result of each comparator 251 and 261 is input to the logical product circuit 271. Then, the AND circuit 271 sets the address coincidence signal 941 to 1 when both the comparison result 921 and the comparison result 931 are 1, and otherwise sets it to 0. That is, when the address is within the specified range, the address match signal 941 is output. Then, this signal is input to the output buffer 281. The output buffer 281 outputs the cache memory control information stored in the register 241 to the control bus 808 when the address match signal 941 is 1, and outputs nothing when the address match signal 941 is 0.

Next, the operation of the memory circuits 212 to 21m will be described. The difference between the memory circuit 211 and the memory circuits 212 to 21m is that there are AND circuits 292 to 29m for priority determination. The AND circuit 292 outputs the address match signal 9
The output permission signal 952 is set to 1 when 41 is 0 and the address coincidence signal 942 is 1, and is set to 0 otherwise. This prevents both the output buffer 281 and the output buffer 282 from simultaneously outputting the cache memory control information to the control bus 808 when the address match signal 941 and the address match signal 942 are both 1. . Similarly, the logical product circuit 29m sets the output permission signal 95m to 1 when only 94m of the address coincidence signals 941 to 94m are 1 and the rest are all 0, and otherwise 0. This prevents the two output buffers from outputting the cache memory control information to the control bus 808 at the same time.

The memory circuit 21n has an address of the memory circuit 2
If the value is not within the range specified by 11-21m,
It is a circuit for outputting cache memory control information. That is, the AND circuit 29n for priority determination sets the output permission signal 95n to 1 when the address coincidence signals 941 to 94m are all 0, and sets it to 0 otherwise. In this case, AND circuits 292 to 29n for priority determination
Since the lower limit address registers 221 to
No matter what value is set in the register 22m and the upper limit address registers 231 to 23m, the outputs of two or more output buffers do not collide on the control bus 808.
One cache memory control information is always the control bus 8
08 is output. Therefore, the degree of freedom in setting the upper limit address and the lower limit address increases.

Further, as another example, it is also possible to configure one in which the AND circuits 292 to 29m for priority determination and the memory circuit 21n are removed from FIG. In this case, it is necessary to set the upper limit address and the lower limit address so that only any one of the output buffers 281 to 28m outputs the control information at all times. The physical quantity is reduced and the storage circuits 211 to 21
There is an advantage that the processing of m is speeded up.

Also, when the method register 100 of FIG. 9 is used, all addresses are divided into a plurality of spaces and each space is divided into a plurality of areas, as in the case of using the method register 100 of FIG. Alternatively, the cache memory control information can be designated for each area. In addition to this,
Since the size and arrangement of each area can be changed by rewriting the upper limit address and the lower limit address, the degree of freedom in setting the cache memory control information is improved as compared with the case where the method register 100 of FIG. 7 is used. .

FIG. 10 is a diagram showing a fourth embodiment of the method register 100. Method register 100 in this embodiment
Is characterized by including a part of a circuit for converting a logical address to a physical address, and is configured by including a control circuit 142, a memory circuit 144, and a comparator 146.

The memory circuit 144 has n entries 151 to 151.
Each entry stores a tag, a physical address, and cache memory control information. Conversion from a logical address to a physical address is performed in units of a certain size area called a page,
Each entry is set corresponding to one page.
The memory circuit 144 selects one of the entries 151 to 15n by using a predetermined bit of the address received via the control bus 804, and selects the tag and the physical value stored in the selected entry. The address and cache memory control information are output. In this case, the number of bits of the address used for selecting the entry is p
Then, there is a relation that the power of 2 is equal to the number n of entries. Further, the comparator 146 compares the high-order bit of the address with the tag output from the storage circuit 144, and sets the address match signal 968 to 1 when both match and sets to 0 otherwise. The control circuit 142 uses the control bus 80.
2 to receive the write request 962 and output the write control signal 966 according to this request. Memory circuit 1
Upon receiving the write control signal 966, the 44 stores the write data 964 in the designated entry.

Next, a method of executing an application program in the information processing apparatus having the method register 100 shown in FIG. 10 will be described.

First, the following processing is performed before the execution of the application program is started.

(1) Allocate logical addresses to all instructions and data of the program. (2) The optimum cache memory control information is obtained for each page of the logical address, and an address correspondence table that associates the logical address with the physical address and the cache memory control information is created. (3) Select a page that is expected to be used in the near future,
Write those pages to the method register 100. After the above processing is completed, execution of the application program is started. In this case, the address match signal 968 becomes 1 when the necessary instruction or data is registered in the method register 100, and becomes 0 when it is not registered. When the address match signal 968 is 1, the physical address and the cache memory control information read from the method register 100 are valid, and therefore the processing is continued.

On the other hand, when the address match signal 968 is 0, the physical address and the cache memory control information are read from the above-mentioned address correspondence table, and this is read by the method register 1
After writing to 00, the processing is continued. At this time,
When the method register 100 shown in FIG. 0 is used, the cache memory control information can be designated in a unit of a relatively small area such as a page.
As compared with the case where a relatively large area is designated as a unit such as 0, the use efficiency of the cache memory is improved. Further, since it is only necessary to add the area for storing the cache memory control information to the memory circuit for address conversion, it is possible to reduce the increase in the amount of hardware. Further, even when the process of rewriting the cache memory control information is performed, the process can be performed together with the process for address conversion, so that an increase in processing time can be suppressed.

FIG. 11 shows a second cache memory 300.
It is a figure which shows an Example. The cache memory 300 according to the present embodiment is characterized by having a plurality of storage areas for storing different block sizes. That is, the memory 364 is provided with n basic blocks 371 to 37n, and each basic block is provided with an area for storing a tag, data and size. If the value set in the size area is the same as the capacity of the data area, one basic block constitutes one block, and if it is larger than the capacity of the data area, a plurality of adjacent basic blocks Indicates that they form one block. Then, the memory 364 has the address 9
Basic block 37 using 74 predetermined bits
One block is selected from 1 to 37n, and the tag, data and size stored in the selected basic block are output. In this case, assuming that the number of bits of the address used for selecting the basic block is p, there is a relation that the power of 2 is equal to the number n of basic blocks. The control circuit 362 also receives a write request 972 from the control bus 810 and outputs a write control signal 976 to the memory 364 in accordance with this request. Memory 3
64 receives the write control signal 976, the memory 3
64 indicates a data bus 812 in the designated basic block.
Write the write data input via.

Next, a method of transferring an instruction or data from the main memory 608 to the cache memory 300 in the information processing apparatus having the method register 100 of FIG. 11 will be described. In this case, the capacity of the data area of the basic block may be any power of 2 (1 byte, 2 bytes, 4 bytes, 8 bytes, ...), but here it is 4 bytes. The block size is a power of 2 times the size of the basic block (1 time, 2 times, 4 times, 8 times, ...).

1 if the block size is 4 bytes
One basic block becomes one block. When the block size is 8 bytes, two adjacent basic blocks are one block, and two basic blocks are selected so that the address of the leading basic block is on an 8-byte boundary. The same applies when the block size is 16 bytes or more, and adjacent basic blocks are selected so that the block start address becomes the block size boundary. Basic blocks belonging to the same block have the same value stored in the tag area and the size area.

On the other hand, when transferring an instruction or data to the cache memory, first of all, the method register 100
Check the value of block size (BKS) read from
Select the number of basic blocks that corresponds to the block size. At this time, in the selected basic block, the main memory 6
If there is data to be transferred in 08, the necessary data is transferred. At this time, the value of the size area of the basic block that needs to be transferred is checked, and when adjacent basic blocks store the same block of data, they are collectively transferred to the main memory 608. By performing such processing, the transfer efficiency is improved as compared with the case where each basic block is transferred separately.

When the data transfer to the main memory 608 is completed, necessary instructions or data are transferred from the main memory 608 to the selected basic block. At that time, the block size value read from the method register 100 is written in the size area of each basic block.

Next, a second embodiment of the present invention will be described with reference to FIG.

This embodiment is characterized in that two types of cache memories having different response speeds are provided and two method registers are provided corresponding to the memories.

That is, the primary cache memory 520 and the secondary cache memory 522 are provided as the cache memory, and the method register 51 is used as the method register.
4, 516 are provided. Primary cache memory 5
20 is a high-speed memory that corresponds to the cache memory 300 of FIG. 1 and can immediately respond to a request from the instruction processing unit 512, but has a small capacity. On the other hand, the secondary cache memory 522 cannot immediately respond to the request of the instruction processing unit 512, but is faster than the main memory 608 and has a capacity larger than that of the primary cache memory 520. The method register 514 is used by the primary cache memory 52.
0 and the secondary cache memory 522 store control information when transferring an instruction or data, and the method register 516 stores the secondary cache memory 522 and the main memory 608.
It stores the control information when transferring instructions or data to and from.

In the present embodiment, since the secondary cache memory 522 having a large capacity is added, even when there is no necessary instruction or data in the primary cache memory 520, when there is data in the secondary cache memory 522, Since the data can be transferred from there, the data can be transferred at a higher speed than in the case of transferring from the main memory 608, and the performance can be improved.

FIG. 13 is a block diagram showing the third embodiment of the present invention. In this embodiment, two cache memories for instructions and data are provided as cache memories, and
It is characterized in that two method registers are provided corresponding to each cache memory. That is, as the cache memory, the instruction cache memory 540 and the data cache memory 542 are provided, and the method register 534,
536 is provided.

The instruction cache memory 540 stores only instructions, and the data cache memory 542 stores only data. In this case, it is not necessary to transfer the instruction from the instruction cache memory 540 to the main memory 608 because the instruction is only read. The control bus 982 and the data bus 984 are used when transferring an instruction, and the control bus 986 and the data bus 988 are used when transferring data. On the other hand, the method register 534 stores control information when transferring an instruction from the main memory 608 to the instruction cache memory 540, and the method register 536 transfers data between the data cache memory 542 and the main memory 608. It stores the control information at the time.

In this embodiment, since the instruction cache memory 540 and the data cache memory 542 can be accessed simultaneously, the instruction read request and the data read or write request from the instruction processing unit 532 are executed in parallel. Therefore, the performance is improved as compared with the case where the same cache memory is used for the instruction and the data.

[0096]

As described above, according to the present invention,
The transfer efficiency of the cache memory is improved because the transfer of information between the cache memory and the main memory is controlled according to the optimum cache memory control information obtained by considering the properties of the application program and various hardware parameters. Therefore, the processing performance of the information processing apparatus can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention.

FIG. 2 is a block diagram showing a first embodiment of a method register.

FIG. 3 is a block configuration diagram showing a first embodiment of a cache memory.

FIG. 4 is a block diagram of a memory control unit.

FIG. 5 is a flow chart for explaining a process at the time of reading an instruction or data of a memory control unit.

FIG. 6 is a flowchart for explaining a process of writing data in the memory control unit.

FIG. 7 is a block diagram showing a second embodiment of a method register.

8 is a diagram for explaining correspondence between an address and cache memory control information when the method register of FIG. 7 is used and a method of using the same.

FIG. 9 is a block diagram showing a third embodiment of a method register.

FIG. 10 is a block diagram showing a fourth embodiment of a method register.

FIG. 11 is a block diagram showing a second embodiment of the cache memory.

FIG. 12 is a block diagram showing a second embodiment of the present invention.

FIG. 13 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 100 Method Register 102 Block Size (BKS) 104 Prefetch Number (NPF) 106 Caching Selection (C / N) 108 Copyback Selection (C / S) 110 Fetch On Write Selection (F / W) 112 Register 300 Cache Memory 400 Memory Control Unit 404 Prefetch control circuit 502 Instruction processing unit 608 Main memory

Claims (12)

[Claims] 1. A main storage means for storing an instruction to be executed and information about data to be processed, and an instruction processing means for processing the data stored in the main storage means in accordance with the instruction stored in the main storage means. A cache memory for storing a part of the information stored in the main storage means, a control information storage means for storing cache memory control information according to an application program, and a cache memory stored in the control information storage means An information processing apparatus comprising: a memory control unit that controls transfer of information between the main storage unit and the cache memory according to control information. 2. Main memory means for storing information on an instruction to be executed and data to be processed, and instruction processing means for processing the data stored in the main memory means in accordance with the instruction stored in the main memory means. A cache memory for storing a part of the information stored in the main storage means, a control information storage means for storing a plurality of cache memory control information according to an application program, and a control information storage means An information processing apparatus comprising: a memory control unit that controls transfer of information between the main storage unit and the cache memory according to designated cache memory control information of a cache memory control information group. 3. The cache memory has a plurality of memory areas according to a block size indicating a transfer unit of information, and a write control means for storing the information in a designated memory area according to the block size. 3. The information processing apparatus according to claim 1, wherein the cache memory control information stored in the storage means includes information regarding a block size suitable for transfer as a block size indicating a transfer unit of information. 4. The memory control means has prefetch control means for predicting an address of information required in the future and controlling transfer of information according to the prediction result, and cache memory control information stored in the control information storage means. 3. The information processing apparatus according to claim 1, wherein the prefetch control unit includes information designating a transfer amount of information to be transferred at one time. 5. The cache memory has a plurality of memory areas corresponding to a block size indicating a transfer unit of information, and write control means for storing the information in a designated memory area according to the block size. The cache memory control information stored in the storage means includes information on a block size suitable for transfer as a block size indicating a transfer unit of information, and the memory control means predicts an address of information required in the future, and according to this prediction result. The cache memory control information stored in the control information storage means includes prefetch control means for controlling information transfer, and the cache memory control information includes information designating a transfer amount of information to be transferred at one time by the prefetch control means. Or the information processing device according to 2. 6. The memory control means, when receiving the information read request from the instruction processing means, exchanges information with the cache memory and determines whether or not the specified information exists in the cache memory. And a transfer control unit that controls transfer of information according to the determination result of the determination unit and the cache memory control information stored in the control information storage unit, and the cache memory control information stored in the control information storage unit is 6. The information according to claim 1, 2, 3, 4 or 5, including information indicating whether or not designated information should be transferred from the main storage means to the cache memory when there is no information requested to be read in the cache memory. Processing equipment. 7. The memory control means, when receiving a request for writing information from the instruction processing means, exchanges information with the cache memory and determines whether or not the specified information exists in the cache memory. And a transfer control unit that controls transfer of information according to the determination result of the determination unit and the cache memory control information stored in the control information storage unit, and the cache memory control information stored in the control information storage unit is 6. The information according to claim 1, 2, 3, 4 or 5, including information indicating whether or not designated information should be transferred from the main storage means to the cache memory when there is no information requested to be written in the cache memory. Processing equipment. 8. The memory control means, when receiving a request for writing information from the instruction processing means, information transfer means for transferring designated information to the cache memory, and cache memory control information stored in the control information storage means. The cache memory control information stored in the control information storage means, should the specified information to be stored in the cache memory also be written in the main storage means or the cache memory. 2. The information including information indicating whether to prohibit writing of the designated information in the main storage means while the designated information stored in is valid.
The information processing device described in 2, 3, 4 or 5. 9. The control information storage means has a storage area group for respectively storing cache memory control information divided into a plurality of parts, and instructions divided according to the frequency of branch instructions are stored in the storage area. Data stored in any of the storage areas of the group in a distributed manner and divided according to the frequency of use are stored in the storage area of the storage area group different from the instruction. The information processing device according to 1 or 2. 10. The control information storage means has a plurality of storage areas for respectively storing different cache memory control information, and an address range in which the addresses are received from the instruction processing means and the addresses are set corresponding to the respective storage areas. A plurality of address range determining means for determining whether or not they are within the range, and the condition that a positive determination result is obtained from the designated address range determining means and a negative determination result is obtained from the other address range determining means. 3. An information processing apparatus according to claim 1, further comprising a plurality of information output means for selecting and outputting cache memory control information from a designated storage area. 11. The cache memory is composed of a plurality of memories having different response speeds, and the memory control means controls the transfer of information between the main storage means and one of the cache memories, and transfers the information between the cache memories. The information processing apparatus according to claim 1, wherein the information processing apparatus controls the information processing apparatus. 12. The cache memory comprises an instruction cache memory and a data cache memory, and the control information storage means stores an instruction control information storage means for storing instruction control information of the cache memory control information and a cache memory control. The memory control means controls transfer of information between the instruction cache memory and the main memory means, and the data cache memory and the main memory. The information processing apparatus according to claim 1, wherein transfer of information between means is controlled.