JP2002116748A - Image data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To makes display memories efficiently usable. SOLUTION: A VRAM 113 has a one-dimensional access region 122 where each pieces of pixel data constituting image data is stored at plural continuous addresses. The image data which is made necessary afterward according to the progression of processing is stored in this one-dimensional access region 122. A VDP 112 reads the image data out of the one-dimensional access region 122 at need. This image data is converted to the pixel data by each of respective pixel positions according to image size information 'SXn and SYn' and the addresses of respective pieces of the pixel data are determined according to refractive index pixel positions 'Xs and Ys' and are stored in a two-dimensional access region 121. A VDP 112 performs the deflag processing of the one-dimensional access region 122 on such an occasion when the image data is deleted from the one-dimensional access region 122, thereby optimizing the arrangement of the storage area of the image data and integrating free areas to one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus suitable for displaying images of various electronic devices such as a personal computer and a game machine.

[0002]

2. Description of the Related Art An image data processing apparatus for displaying an image on a display device such as a CRT (Cathode-Ray Tube) is a VRAM (Video Random Access Memory) in which image data is stored.
ry). The VRAM stores image data for one screen displayed on the display screen of the display device, and image data for editing and processing required to compose one screen in pixel data units.

FIG. 11 is a diagram schematically illustrating the configuration of a memory area 200 of a general VRAM. FIG.
As shown in (a), the memory area 200 is
It has an address configuration corresponding to each pixel position [X, Y] (X = 1 to 1024, Y = 1 to 1024) in a matrix of 24 × 1024 in the Y direction. To elaborate,
In the memory area 200, individual addresses are fixed in advance for each pixel position [X, Y]. Each pixel data is stored in the memory area 20 according to an address corresponding to each pixel position [X, Y].
0 is stored.

[0006] As shown in FIG. 11A, the memory area 200 is divided into a display area 201 and a work area 202. The display area 201 is an area where pixel data for one screen of the display device is stored. The display area 201 has, for example, a size of 640 pixels in the X direction × 480 pixels in the Y direction corresponding to each pixel position on the display screen, as shown in FIG. The work area 202 is an area other than the display area 201 in the memory area 200, and stores image data for editing or processing in units of pixel data.

FIG. 11B schematically shows a specific example of data storage in the memory area 200. The display area 201 stores image data A to be displayed on the screen, and the work area 202 stores image data B, image data C, image data D, and image data E.

[0006]

By the way, when processing related to image generation and display is performed in the image data processing apparatus, many image data are frequently rewritten in the memory area 200 of the VARM. In such a case, the following problem occurs in the work area 202 of the VRAM.

That is, in the work area 202 shown in FIG. 11B, the area below the image data C, the area between the image data B and the image data E, and the area between the image data D and the display area 201 are , The two-dimensional size of the empty area is very small. Therefore, it is difficult to store new image data in these empty areas, and these empty areas become substantially unusable memory areas. Thus, in the conventional VRAM,
A large number of small free areas that cannot be used are scattered, and memory resources cannot be used efficiently.

Further, as described above, the image data stored in the work area 202 of the VRAM includes the pixel position [X,
Y], and is stored in pixel data units in accordance with an address corresponding to [Y]. Therefore, in order to relocate the storage area of each image data in the work area 202 and secure a free area of an available size, the storage area must be transferred in units of pixel data. The control for grouping the areas is complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the circumstances described above, and has as its object to provide an image data processing apparatus that can efficiently use a display memory.

[0010]

According to the present invention, a first storage area in which pixel data of each pixel is stored in accordance with an address configuration corresponding to the position of each pixel on a display screen of a display device, A display memory having an address configuration, a second storage area in which each pixel data constituting the image data is stored at a continuous address, and the image data stored in the second storage area, Control means for storing each pixel data constituting the image data in the first storage area at an address corresponding to a position where the pixel is to be displayed; and each pixel data stored in the first storage area. And a supply unit that reads out and supplies the readout data to the display device.

Further, according to the present invention, in the above-mentioned image data processing apparatus, a discriminating means for discriminating whether or not there are a plurality of free areas in the second storage area, Changing means for changing a storage area of one or more image data in the second storage area in order to combine the empty areas into one when the operation is performed;
The gist is to further include

[0012]

Embodiments of the present invention will be described below. These embodiments show one aspect of the present invention, and do not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

A. First embodiment A-1. 1. Configuration of First Embodiment (1) Overall Configuration of PC (Personal Computer) FIG. 1 shows a PC main body 101 according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a PC 10 that uses a PC.
In FIG. 1, a PC 10 includes a display device 100 and a PC main body 101.

The display device 100 is a CRT or LCD (Liquor
id Crystal Display), and its display screen includes
Each pixel position is provided in a matrix of 640 pixels in the horizontal direction × 480 pixels in the vertical direction. This display device 100
VDP (Video Display Processor) of PC 101
An image is displayed on the display screen based on the analog image signal supplied from the terminal 112 and other control signals.

The PC main unit 101 has a CPU (Central Proc).
essing unit) 110, a memory 111, a VDP 112 and a VRAM 113. The CPU 110, the memory 111 and the VDP 112 are connected to each other via a bus 114.

The CPU 110 executes various programs stored in the memory 111 to execute
4 to control each unit connected to the apparatus. For example, the CPU 110 executes processing related to generation and display of an image in cooperation with the VDP 112. Details of the processing related to generation and display of the image will be described later.

The memory 111 stores the image data storage area 11
1a and an ID (IDentification) management table 111b. The memory 111 stores a program related to generation and display of an image executed by the CPU 110, and other programs and data necessary for controlling the PC 10.

The image data storage area 111a stores a plurality of image data and image size information [S _Xn , S _Yn ] of each image data. Each image data in the image data storage area 111a is constituted by pixel data of each pixel position constituting the image. Further, the X size value (S _Xn ) and the Y size value (S _Yn ) of the image size information are numerical data indicating the number of pixels in the X direction or the Y direction that constitute the image, respectively.

The ID management table 111b is a table in which the correspondence between identification information for identifying each image data and a header ID is registered. This ID management table 1
Details of 11b and the header ID will be described later.

The VDP 112 is an LSI (Large Scale In).
integration) and an integrated circuit.
In cooperation with the image processing unit 10, processing related to generation and display of an image is executed. At this time, for example, the VDP 112
Control of writing and reading of image data with respect to.
In addition, the VDP 112 sequentially reads pixel data for displaying each pixel on the display screen from the VRAM 113, generates an analog image signal, and supplies the analog image signal to the display device 100.

The VRAM 113 is connected to the VDP 112 and is a display memory for storing image data to be displayed on a display screen, and image data for editing and processing required to compose one screen. Below, this VR
The configuration of the memory area of the AM 113 will be described.

(2) Configuration of Memory Area of VRAM 113 FIG. 2 is a diagram illustrating the configuration of the memory area 120 of the VRAM 113 according to the present embodiment. In FIG.
The AM 113 has a continuous hexadecimal address "0X00
It has a 2M [byte] (M = 10 ⁶ ) memory area 120 in which data access is managed by “0000” to “0XFFFFFF”. This memory area 120 is
0.5-M [byte] two-dimensional access area 121;
5M [byte] one-dimensional access area 122. The one-dimensional access area 122 has a header area 123.

As shown in FIG. 2, the two-dimensional access area 1
Reference numeral 21 denotes a matrix of pixel positions [X, Y] of 1024 in the X direction × 512 in the Y direction (X = 1 to 1024, Y =
1 to 512). More specifically, in the two-dimensional access area 121, individual addresses (“0, 0”) are assigned to each pixel position [X, Y].
X000000 ”to“ 0X400000 ”) are fixed and provided in advance. Each pixel data is stored in the two-dimensional access area 121 according to an address corresponding to each pixel position [X, Y].

The two-dimensional access area 121 is divided into a display area 121a and a work area 121b.
The display area 121a is an area where pixel data for one screen of the display device 100 is stored, and has a size of 640 pixels in the X direction and 480 pixels in the Y direction corresponding to each pixel position on the display screen. The work area 121b is an area other than the display area 121a in the two-dimensional access area 121.

Next, the one-dimensional access area 122 corresponds to FIG.
As shown in the figure, addresses “0X400000” to “0X
A memory area of 1.5 M [byte] up to "FFFFFF", and is constituted by a large number of memory cells 122a having a data storage amount of 2 [byte] per address. When image data is stored in the one-dimensional access area 122, the image data is divided and stored in a plurality of memory cells 122a specified by consecutive addresses (address numbers) in units of 2 [bytes].

Hereinafter, an area constituted by a plurality of memory cells 122a for storing one image data is referred to as a storage area. Further, the image data is stored in the one-dimensional access area 122 at the start address “0X40000”.
Starting from "0", the addresses are sequentially stored in ascending order of the address numbers.

The one-dimensional access area 122 is an area used as a cache area for image data. Conventionally, the one-dimensional access area 122 is used for editing or processing image data, frequently used image data, Image data and the like that are required later according to the progress of the processing are temporarily stored. Specifically, the one-dimensional access area 122
Is used as described below in processing related to image generation and display.

In other words, the CPU 110 transmits the above-described image data, which is sequentially required in accordance with the progress of the processing, to the VDP 112 at a stage prior to the timing actually used by the VDP 112 in the processing relating to the generation and display of the image. . The VDP 112 temporarily stores these image data in the one-dimensional access area 122, and reads out the necessary image data from the one-dimensional access area 122 for use when the actual use timing comes.

Next, in the header area 123, header data of each image data stored in the one-dimensional access area 122 is stored. The header data is data in which management information of image data is stored, and is generated by the VDP 112. The header data is sequentially stored in descending order of address numbers starting from the last address “0XFFFFFF” of the one-dimensional access area 122. Details of this header data will be described later.

As described above, in the one-dimensional access area 122, the image data is sequentially stored in ascending order of the address numbers starting from the first address "0X400000", and the header data 130 is stored in the last address "0XFFFFFF".
Are sequentially stored in ascending order of the address numbers. With such a configuration, each header data is collectively stored in the header area 123, so that it is possible to easily search for the header data.

The image data is stored in the one-dimensional access area 1
22 are sequentially stored in descending order of the address numbers with the last address as a base point.
May be sequentially stored in ascending order of the address numbers with the start address of the address as a base point.

(3) Configuration of Header Data FIG. 3 is a diagram illustrating a configuration of the header data 130 stored in the header area 123 of the VRAM 113 according to the present embodiment. As shown in FIG.
Has header ID, start address, one-dimensional data size, image size information, and use state flag data.

The header ID is identification information for identifying the header data 130, and is numerical data such as "1" and "2". The start address is head address data of a storage area in the one-dimensional access area 122 where image data is stored. The one-dimensional data size indicates the amount of image data. In addition, since the image size information has been described above, the description is omitted. The use state flag is set to “1” when image data is stored in the one-dimensional access area 122, and is set to “0” when image data is not stored.

The header data 130 is stored in the header area 1
Once stored in the VDP 11, a command instructing the CPU 110 to clear the data in the header area 123 is output from the VDP 11.
2 is continuously stored in the header area 123 unless supplied to the header area 123. That is, even if the image data is deleted from the one-dimensional access area 122, the corresponding header data 130
Continues to be stored in the header area 123. Note that the data size of the header data 130 is a number per data [by
te] to about a dozen or more [bytes].

As described above, even when the image data is deleted from the one-dimensional access area 122, the following effect is obtained by continuously storing the corresponding header data 130.

That is, the CPU 1
When a request to confirm the presence or absence of certain image data from 00 is made, the VDP 112 returns the result of the presence or absence of storage to the CPU 100 only by confirming the value of the use state flag of the corresponding header data 130 in the header area 123. Can be. When the image data deleted from the one-dimensional access area 122 is stored again, the VDP 112
Does not need to generate the header data 130 again, but only to change the values of the start address and the use state flag using the existing header data 130 of the image data.

(4) Management of Header ID FIG. 4 is a diagram illustrating the configuration of the ID management table 111b stored in the memory 111 according to the present embodiment. In the figure, the correspondence between the identification information for identifying each image data and the header ID is registered in the ID management table 111b. In FIG. 4, identification information for identifying image data is “A”, “B”, “C”,.
, And the header IDs are “1,” “2,” “3,” and so on.
It is.

The CPU 110 and the VDP 112 use the header ID as identification information of the image data. For example, the CPU 110 acquires the header ID of the image data with reference to the ID management table 111b,
Is used to instruct the VDP 112 on image data to be read from the VRAM 113 or image data to be deleted. The above is the configuration of the PC 10 according to the present embodiment.

A-2. Operation of First Embodiment Next, the operation of the first embodiment will be described. In the PC 10, the CPU 110 and the VDP 113 cooperate with each other to execute processing related to image generation and display. Among the processes related to the generation and display of the image, the processes according to the present invention are roughly classified into the following three processes. That is, the one-dimensional access area 12
2, a process for storing new image data in the one-dimensional access area 122, a process for transferring image data stored in the one-dimensional access area 122 to the two-dimensional access area 121,
This is a process of deleting image data from the image data 2. The operation of each of these processes will be described below.

(1) Processing for Storing New Image Data in One-Dimensional Access Area 122 FIG. 5 is a sequence chart for explaining operations of CPU 110 and VDP 112 when storing new image data in one-dimensional access area 122. is there. This process
The process is started when the CPU 110 determines that new image data is to be stored in the one-dimensional access area 122.

As shown in FIG.
Refers to the ID management table 111b in the memory 111 and acquires the header ID of the newly stored image data. The image data to be newly stored and the image size information of the image data are read from the image data storage area 111a (step S1). And the CPU 110
Indicates the read header ID, image data, and image size information, and stores the image data in the one-dimensional access area 122.
And a storage command instructing storage in the VDP 11
2 (step S2).

In response, the VDP 112 first sets the CP
In order to store the image data supplied from U110 in the one-dimensional access area 122, the start address of a storage area for storing the image data is obtained. That is, VDP1
12 searches the header area 123 (step S12).
3) Specify the header data 130 whose use state flag value is "1" and whose start address value is the largest (step S4). And the VDP 112
The start address and one-dimensional data size of the specified header data 130 are read (step S5).

Next, the VDP 112 calculates the head address of the storage area using the read start address and the one-dimensional data size (step S6). Then, the VDP 112 stores the CPU 1 in a plurality of memory cells 122a (storage areas) that are consecutive from the calculated top address in ascending order of the address numbers from the top address.
10 is stored (step S).
7).

Next, the VDP 112 generates header data 130 of the stored image data (step S).
8). As the start address of the header data 130, the head address calculated in step S6 is used, and the one-dimensional data size is calculated. The image size information is stored in the CPU 110 in step S2.
Is used, and the value of the use state flag is set to “1”. In addition, the header ID supplied from the CPU 110 in step S2 is set as the identification information of the header data 130.

Then, the VDP 112 stores the generated header data 130 in the header area 123 (Step S9). At this time, the VDP 112 transmits the header data 130
Are stored in descending order of the address numbers from the last address side of the one-dimensional access area 122.

When the image data deleted from the one-dimensional access area 122 is stored again in the one-dimensional access area 122, the CPU 110 and the VDP 112 execute the same processing as the above-described steps from step S1 to S7. Then, in steps S8 and S9, the VDP 112 does not generate new header data 130 but performs a process of changing a part of the header data 130 of the image data already stored in the header area 123. That is, the VDP 112 rewrites the start address of the header data 130 with the top address of the storage area of the image data stored again,
The value of the use state flag is changed from “0” to “1”.

According to the above-described processing, new image data designated by the CPU 110 is stored in the one-dimensional access area 122 of the VRAM 113. Also, VD
The header data 130 of the image data is generated by P112 and stored in the header area 123. In the one-dimensional access area 122, the image data is sequentially stored in ascending order of the address numbers from the top address side, and the header data 130 is sequentially stored in the ascending order of the address numbers from the last address side.

(2) Process of Transferring Image Data Stored in One-Dimensional Access Area 122 to Two-Dimensional Access Area 121 FIG. 6 is a sequence chart for explaining operations of the CPU 110 and the VDP 112 when transferring data to the CPU. This processing is started when image data to be transferred to the two-dimensional access area 121 among the image data stored in the one-dimensional access area 122 is determined by the CPU 110. Specifically, for example, 1
This is executed when the image data for editing stored in the dimension access area 122 is displayed on a part of the screen.

In the figure, first, the CPU 110 refers to the ID management table 111b in the memory 111 and
From the two-dimensional access area 122 to the two-dimensional access area 121
The header ID of the image data to be transferred to is acquired (step S21). Further, the CPU 110 determines a reference pixel position [Xs, Ys] necessary for storing the image data to be transferred in the two-dimensional access area 121 (step S22).

The reference pixel position [Xs, Ys] is obtained by converting the image data to be transferred into pixel data for each pixel position constituting this image, and then converting the pixel data to any pixel position in the two-dimensional access area 121. These are XY coordinate values that specify whether to store based on [X, Y]. More specifically, for example, when a character image stored in the one-dimensional access area 122 is displayed at a certain position on the display screen, the reference pixel position [Xs , Ys] is determined.

Then, the CPU 110 stores the header ID and the reference pixel position [Xs, Ys] and
From the two-dimensional access area 122 to the two-dimensional access area 121
And a transfer command instructing the transfer to the VDP 11
2 (step S23).

In response, the VDP 112 first sets the CP
According to the header ID supplied from U110, the corresponding header data 130 is specified in the header area 123. Then, the VDP 112 identifies the specified header data 1
The 30 start addresses, one-dimensional data size and image size information are read (step S24).

Next, the VDP 112 reads the image data to be transferred from the one-dimensional access area 122 according to the read start address and one-dimensional data size (step S25). Note that the read image data is continuously stored in the one-dimensional access area 122 unless a deletion instruction is issued from the CPU 110. Therefore, the value of the use state flag in the header data 130 of this image data remains “1”.

Thereafter, the VDP 112 executes a conversion process on the read image data into pixel data using the image size information obtained in the above step S24 (step S26). Here, the image data read from the one-dimensional access area 122 is the image data originally stored in the image data storage area 111a, and is constituted by the pixel data of each pixel position constituting the image. In addition, as described above, X of the image size information
The size value and the Y size value correspond to the X direction constituting the image,
This is numerical data indicating the number of pixels in the Y direction.

Therefore, in the conversion process shown in step S 26, VDP 112
Is converted into pixel data for each pixel position constituting the image according to the X size value and the Y size value of the image size information.

Thereafter, the VDP 112 executes the processing in step S
In 23, using the reference pixel position [Xs, Ys] supplied from the CPU 110, the destination pixel position [X, Y] of the pixel data is calculated for each converted pixel data,
The corresponding address is determined (step S27). Then, the VDP 112 stores each pixel data in the two-dimensional access area 121 according to each address (Step S28).

The VDP 112 sequentially reads out each pixel data from the display area 121a of the two-dimensional access area 121 according to the scanning timing. Then, an analog image signal is generated based on the read pixel data, and the analog image signal is supplied to the display device 100. Accordingly, the display area 121 is displayed on the display screen of the display device 100.
An image based on each pixel data for one screen stored in a is displayed.

By the processing described above, the VDP 112
Reads out the image data specified by the CPU 110 from the image data stored in the one-dimensional access area 122 of the VRAM 113, converts the image data into pixel data for each pixel position, and converts each pixel data into the reference pixel position [Xs,
[Ys] in the two-dimensional access area 121.

(3) Processing for Deleting Image Data from One-Dimensional Access Area 122 FIG. 7 is a sequence chart illustrating the operation of CPU 110 and VDP 112 when deleting image data from one-dimensional access area 122. This processing is started when image data to be deleted among the image data stored in the one-dimensional access area 122 is determined by the CPU 110. Specifically, for example, the processing is executed when unnecessary image data is deleted from the one-dimensional access area 122 or when the data storage amount of the one-dimensional access area 122 reaches a predetermined amount.

In the figure, first, the CPU 110 refers to the ID management table 111b in the memory 111 and
The header ID of the image data to be deleted is acquired from the dimension access area 122 (step S41). And CPU
110 transmits to the VDP 112 a header ID and a delete command instructing that the image data be deleted from the one-dimensional access area 122 (step S42).

In response, the VDP 112 first sets the CP
According to the header ID supplied from U110, the corresponding header data 130 is specified in the header area 123. Then, the value of the use state flag of the specified header data 130 is changed to “0” (step S43). By the processing in step S43, the storage area of the image data designated to be deleted by the CPU 110 is released, and the deletion of the image data is completed.

After that, the VDP 112 executes a defragmentation process. The defragmentation process is a process of optimizing the arrangement of a plurality of data stored in the memory and collecting free areas.

In this defragmentation process, first, the VDP
Reference numeral 112 denotes header data 13 of the deleted image data.
The start address value is read from 0 (step S5).
1). Next, the VDP 112 searches the header area 123 (step S52), and if the value of the use state flag is “1” and the value of the start address is
It is determined whether or not there is header data 130 larger than the value of the start address acquired in step S51.

That is, the VDP 112 determines whether or not other image data is stored in an area having a larger address number than the storage area of the deleted image data in the one-dimensional access area 122 (step S53). Here, if the one having the larger address number in the one-dimensional access area 122 is defined as the rear, the above step S
In other words, it can be said that the determination 59 determines whether or not other image data is stored behind the storage area of the deleted image data in the one-dimensional access area 122.

If the VDP 112 determines that no other image data is stored behind the storage area for the deleted image data, the VDP 112 ends the defragmentation process. If the VDP 112 determines that the image data is stored behind the storage area of the deleted image data, the VDP 112 determines that the one-dimensional access area 122 is in a state where a plurality of free areas are scattered. Free space
Execute the process to combine them.

First, the VDP 112 searches the header data 130 of each of one or more pieces of image data stored after the storage area of the deleted image data, and confirms the respective start addresses (step S54).
Then, of these image data, the image data stored closest to the storage area of the deleted image data is specified (step S55).

Next, the VDP 112 reads the start address and the one-dimensional data size from the header data 130 of the specified image data (step S56). Then, image data is read from the one-dimensional access area 122 according to the start address and the one-dimensional data size (step S57).

Next, the VDP 112 stores the read image data again in the storage area starting from the start address of the deleted image data (step S58). The VDP 112 changes the value of the start address of the image data to the start address of the deleted image data (step S59).

Thereafter, the VDP 112 proceeds to step S
Returning to 53, for image data stored after the image data whose storage area has been changed, the storage area is sequentially changed one image data at a time in the same manner. However,
In this case, the start address of the image data whose storage area is changed can be obtained by calculation using the start address and the one-dimensional data size of the image data whose storage area has been changed immediately before. That is, the last address of the storage area is obtained for the image data whose storage area has been changed immediately before based on the start address and the one-dimensional data size. Therefore, the address following the last address is set as the start address of the image data whose storage area is to be changed this time.

FIG. 8 is a diagram exemplifying a state transition of the one-dimensional access area 122 when deleting image data from the one-dimensional access area 122. FIG. 8A is a diagram illustrating a state before image data is deleted from the one-dimensional access area 122. As shown in the figure, in the one-dimensional access area 122, the image data A,
Image data B, image data C, image data D, and image data E are stored. In the header area 123,
Header data 1, header data 2, header data 3, header data 4, and header data 5 are stored in order from the last address side of the one-dimensional access area 122 as the header data 130 of each of the image data A to E.

The correspondence between the image data A to E and the header data 1 to 5 is as shown in FIG. 8A to 8C, each of the header data 1 to
The value described after the item 5 is the value of the use state flag.

In the state shown in FIG. 8A, when the CPU 110 instructs to delete the image data C, the VDP 112 transfers the image data C in the header area 123 as shown in FIG. 8B. The value of the use state flag of the corresponding header data 3 is changed from “1” to “0”, and the storage area of the image data C is released. Thus, the area where the image data C is stored becomes a free area.

Next, a defragmentation process is executed by the VDP 112, and the storage areas of the image data D and the image data E stored in the area having the larger address number than the storage area of the deleted image data C are changed. That is, as shown in FIG. 8C, the storage areas of the image data D and the image data E are changed so as to fill the free space generated by the deletion of the image data C. At this time, regarding the image data D and the image data E whose storage areas have been changed, the corresponding header data 4
And the start address of the header data 5 is rewritten to the start address of the new storage area.

By the processing described above, the VDP 112
Performs the defragmentation process immediately after deleting the image data from the one-dimensional access area 122. Then, the arrangement of the storage areas of the respective image data stored in the one-dimensional access area 122 is optimized to prevent the occurrence of a plurality of free areas.

According to the present embodiment, the VRAM 113
It has a one-dimensional access area 122 in which image data is stored according to a plurality of consecutive addresses. The CPU 110 and the VDP 112
Temporarily stores various image data required later according to the progress of processing, and stores the one-dimensional access area 12
2 to read image data. And VDP112
_Converts read image data into pixel data of each pixel constituting the image according to image size information [S _Xn , S _Yn ], and determines an address of each pixel data according to a reference pixel position [Xs, Ys]. And stores it in the two-dimensional access area 121.

With such a configuration, it is possible to optimize the arrangement of the storage areas of the respective image data stored in the one-dimensional access area 122 and to realize the control of unifying the free areas with a simple configuration. . This also allows the memory cells 112a of the one-dimensional access area 122 to be used without waste. In addition, 1
By performing the defragmentation process immediately after deleting the image data from the dimension access area 122, it is possible to prevent a plurality of free areas from occurring.

Further, according to the present embodiment, the VDP 112
For each image data stored in the one-dimensional access area 122, it is possible to easily confirm the address information, the data amount, the current storage status, and the like by referring to the header data.

B. Second Embodiment In the first embodiment, the configuration in which the defragmentation process is executed when the image data is deleted from the one-dimensional access area 122 has been described. In the present embodiment, a configuration in which the VDP 112 executes a defragmentation process at an arbitrary timing will be described.

Note that the present embodiment differs from the first embodiment only in the procedure of the process of deleting image data from the one-dimensional access area 122 (see FIG. 7).
Therefore, the description of the parts common to the first embodiment will be omitted. In addition, the same reference numerals are used for parts common to the first embodiment.

(1) Processing for Deleting Image Data from One-Dimensional Access Area 122 In this embodiment, when deleting image data from one-dimensional access area 122, the value of the use state flag is set in header data 130 of the image data. Change to "0"
It only releases the storage area for the image data to be deleted. This part is the same as steps S41 to S43 described with reference to FIG. 7 in the first embodiment, and a description thereof will be omitted.

Next, FIG. 9 shows a one-dimensional access area 122.
5 is a flowchart for explaining the operation of the VDP 112 when performing the defragmentation process of FIG. This defragmentation process
It can be executed at an arbitrary timing by P112.
For example, this defragmentation process is performed at regular intervals of VDP11
The timing when the processing load of (2) falls below a certain level, 1
It is started at a timing when the data storage amount of the dimension access area 122 reaches a predetermined amount. CPU1
10 may be executed in accordance with a defragmentation start instruction from the user.

In FIG. 9, the VDP 112 first searches the header area 123 and specifies all the header data 130 whose use state flag value is “1” (step S101). Then, from the start addresses and the one-dimensional data sizes of all the specified header data 130, the storage areas of all the image data stored in the one-dimensional access area 122 are specified (step S10).
2).

Next, the VDP 112 determines whether or not a plurality of free areas are scattered in the one-dimensional access area 122 (step S103). And VDP112
If it is determined that there are no multiple free areas,
The defragmentation process ends.

If the VDP 112 determines that there are a plurality of vacant areas, the VDP 112 specifies a vacant area with the smallest address number and a vacant area with the next smallest address number among the vacant areas scattered in plural places. (Step S
104). Then, the VDP 112 rearranges the storage area of one or more image data stored between the free areas so as to eliminate the free area (Step S105). Thereafter, the VDP 112 changes the start address of the header data 130 for the image data whose storage area has been changed (step S106), and returns to step S103.

The VDP 112 repeats the processing of steps 103 to S106 until the number of free areas becomes one. If it is determined in step S103 that a plurality of free areas are not present, the defragmentation processing is performed. To end.

FIG. 10 is a diagram illustrating a state transition of the one-dimensional access area 122 when the one-dimensional access area 122 is defragmented in the present embodiment. FIG. 10A is a diagram illustrating a state before the defragmentation process of the one-dimensional access area 122 is performed. As shown in the figure,
In the one-dimensional access area 122, image data A, image data B, image data C, and image data D are stored in order from the top address side. An empty area exists between the image data A and the image data B, an empty area exists between the image data C and the image data D, and an empty area exists after the image data D. In the header area 123, as header data 130 of each of the image data A to D,
In order from the last address side of the one-dimensional access area 122,
Header data 1, header data 2, header data 3, and header data 4 are stored.

In the state shown in FIG.
When the defragmentation process is performed by the DP 112, first,
The storage area of the image data B and the image data C stored between the empty areas is shown in FIG.
As shown in (2), rearrangement is performed so as to eliminate the empty area. As a result, a new free area including a free area is generated in the one-dimensional access area 122.

Thereafter, the image data D stored between the free areas shown in FIG.
Are rearranged so as to eliminate the empty area. As a result, as shown in FIG. 10C, in the one-dimensional access area 122, the storage areas of the image data A, the image data B, the image data C, and the image data D are sequentially arranged from the head address side. The empty areas are arranged and are combined into one as an empty area. For the image data whose storage area has been changed, each time the storage area is changed, the start address of the header data is rewritten to the start address value of the new storage area.

According to the present embodiment, the VDP 112 optimizes the arrangement of the storage area of each image data stored in the one-dimensional access area 122 at an arbitrary timing,
Empty areas can be combined into one. This also allows the memory cell 112a of the one-dimensional access area 122
Can be used without waste.

C. 3. Modifications While the embodiment of the present invention has been described above, this embodiment is merely an example, and various modifications can be made without departing from the spirit of the present invention. For example, the following modifications can be considered.

(Modification 1) In the first and second embodiments, the image data stored in the memory 111
The image size information, the ID management table 111b, and programs related to image generation and display are stored in a CD-ROM (Co-ROM).
mpact Disc Read Only Memory) and DVD (Digital Ver
It may be configured to be stored in the memory 111 via a storage medium such as a satile disc. In this case, the PC body 1
01 may be configured to include a storage medium drive for loading the program and data from the storage medium. Further, the configuration may be such that the program and data are stored in the memory 111 by being downloaded from another device. In this case, the PC main body 101 may be configured to include a communication control unit for controlling data communication performed with another device.

(Modification 2) In the first and second embodiments, the size of the two-dimensional access area 121 in the VRAM 113 and the size of the display area 121a provided in the two-dimensional access area 121 are determined by the PC main body 101. Depending on the resolution of the display device connected to
It is desirable that the configuration be changeable. In this case, for example, a plurality of types of memory area setting data are stored in the memory 111 in advance, for example, for a resolution of 640 × 480 in the horizontal direction or for a resolution of 320 × 240 in the vertical direction. VRAM according to the resolution of
The configuration of changing the setting of the memory area 113 may be adopted.

(Modification 3) In the first and second embodiments, the case where the present invention is applied to a PC that does not include a display device has been described. However, it goes without saying that the present invention is applicable to a PC integrated with a display device. Furthermore, the scope of application of the present invention is not limited to a PC, but it is needless to say that the present invention can be applied to an electronic device having a display memory and displaying an image on a display screen, such as a game machine.

[0094]

As described above, according to the present invention, it is possible to optimize the arrangement of the image data stored in the display memory and realize the control for collecting the free areas with a simple configuration. This also allows the display memory to be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PC using a PC main body according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a memory area of the VRAM according to the embodiment;

FIG. 3 is a diagram illustrating a configuration of header data stored in a header area of a VRAM according to the embodiment.

FIG. 4 is a diagram illustrating a configuration of an ID management table stored in a memory according to the embodiment;

FIG. 5 is a sequence chart illustrating operations of a CPU and a VDP when new image data is stored in a one-dimensional access area according to the embodiment.

FIG. 6 is a sequence chart illustrating operations of a CPU and a VDP when image data stored in a one-dimensional access area according to the embodiment is transferred to a two-dimensional access area.

FIG. 7 is a sequence chart illustrating operations of the CPU and the VDP when deleting image data from the one-dimensional access area according to the embodiment.

FIG. 8 is a diagram illustrating a state transition of the one-dimensional access area when deleting image data from the one-dimensional access area according to the embodiment.

FIG. 9 is a diagram illustrating a VDP when a defragmentation process is performed on a one-dimensional access area of a VRAM according to a second embodiment of the present invention;
5 is a flowchart for explaining the operation of FIG.

FIG. 10 is a diagram illustrating a state transition of the one-dimensional access area when the one-dimensional access area according to the first embodiment is subjected to the defragmentation process.

FIG. 11 is a diagram schematically illustrating a configuration of a memory area of a conventional general VRAM.

[Brief description of reference numerals]

10 PC, 100 Display device, 101 PC body, 110 CPU, 111 Memory, 111a
... image data storage area, 111b ... ID management table, 112 ... VDP, 113 ... VRAM, 114 ...
... bus, 120 ... memory area (VRAM), 121 ...
... two-dimensional access area, 121a ... display area, 121
b: Work area, 122: One-dimensional access area, 12
2a: memory cell, 123: header area, 130:
... Header data.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 12/02 580 G06F 12/02 580G G06T 1/60 450 G06T 1/60 450C

Claims (6)

[Claims] A first storage area in which pixel data of each pixel is stored in accordance with an address configuration corresponding to a position of each pixel on a display screen of a display device, and a one-dimensional address configuration; A display memory comprising: a second storage area in which each pixel data constituting the image data is stored at consecutive addresses; and a pixel data constituting the image data stored in the second storage area. And control means for storing the pixel data in the first storage area at an address corresponding to the position where the pixels are to be displayed, and reading out each pixel data stored in the first storage area and supplying the read data to the display device An image data processing apparatus comprising: 2. A discriminating means for discriminating whether or not there are a plurality of free areas in the second storage area; 2. The image data processing apparatus according to claim 1, further comprising: a changing unit configured to change a storage area of one or more image data in the second storage area to collectively store the image data. 3. The image processing apparatus according to claim 2, wherein the determination unit determines whether there is a plurality of the empty areas when the image data stored in the second storage area is deleted. An image data processing device as described in the above. 4. A generating means for generating, for each image data stored in the second storage area, management data including address information indicating a storage area of the image data, and management data generated by the generating means. The image data processing apparatus according to any one of claims 1 to 3, further comprising: data storage means for storing in the second storage area together with corresponding image data. 5. The determination means refers to address information of each management data stored in the second storage area by the data storage means, and determines whether there are a plurality of free areas in the second storage area. 5. The method according to claim 4, wherein
An image data processing device according to claim 1. 6. When the image data and management data of the image data are stored in the second storage area, the data storage means stores one of the data in the first storage area from the start address side of the second storage area. 5. The image data processing apparatus according to claim 4, wherein the image data is stored in ascending order, and the other data is stored in descending order of the address from the last address side of the second storage area.