JP2002108726A - Inter-package monitoring device of bus-sharing parallel data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter-package monitoring device of a bus-sharing parallel data transfer system which makes it possible to always perform inter- package monitoring of the bus-sharing parallel data transfer system through very simple circuitry. SOLUTION: This inter-package monitoring device performs the monitoring between multiple packages of the bus-sharing parallel data transfer system wherein the packages are connected to one common bus to perform parallel data transfer and a reception-end package provided at the reception end of the common bus; and each package is provided with a test data generating circuit which sends out test data generated by using a counter to the common bus and the reception-end package 31 is provided with a test data detecting circuit which compares the test data sent from each package through the common bus with test data generated by using a similar counter to obtain a detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-package monitoring device in a bus shared parallel data transfer system in which a plurality of packages are connected to a single shared bus and performs data transmission in parallel. The present invention relates to an inter-package monitoring device capable of constantly monitoring between packages with a very compact circuit configuration.

[0002]

2. Description of the Related Art In general, a plurality of packages are connected via a motherboard, and a device which realizes a predetermined function utilizes an idle time of data transfer between packages as a maintenance method for realizing high reliability. A method of transferring test pattern data and monitoring the normality by hardware is known. Here, an inter-package monitoring method based on the test pattern data will be described in the case of a serial data transfer system. In the conventional serial data transfer system, as shown in FIG. 9A, one package is connected between the packages (in this case, packages A and B) by the data line 1.
They are connected one to one. In the apparatus shown in FIG. 9A, the failure monitoring of the data line 1 is performed by adding toggle test pattern data of 1010... To an empty area of the transfer data between the package A and the package B as shown in FIG. This was achieved by inserting and detecting the toggle test pattern data. That is, the failure is detected by detecting the degeneration of the toggle test pattern data to 0 or 1.

Next, generation and insertion of test data and detection of test data in the serial data transfer method will be described. FIG. 10 is a configuration diagram of a test data generation / insertion unit in the serial data transfer method. As shown in FIG. 10, the test data generation / insertion unit 3 includes a D-type flip-flop 5 for generating the toggle test pattern.
The clock is input to the clock (c) terminal of the D-type flip-flop 5 and the output of the AND circuit 7 is input to the D terminal. Here, the AND pulse 7 has a start pulse and the D signal.
The QN output of the type flip-flop 5 is input and ANDed. Then, the Q output (Turgue test pattern) of the D-type flip-flop 5 and the transfer data are input to the selector 9, the selector 9 is switched by the SEL control pulse, and the Trug test pattern data is stored in a predetermined empty area of the transfer data. It is to be inserted. As described above, the transfer data to which the test pattern is added in the predetermined package (for example, package A in FIG. 9A) is transferred to the connection destination package (package B) via the data line 1. The operation timing of the test data generation / insertion unit 3 is as shown in FIG.
FIG. 12 is a configuration diagram of a test data detection unit in the serial data transfer system. As shown in FIG. 12, the test data detecting section 11 has a D-type flip-flop 13 for generating the toggle test pattern, and a clock is applied to a clock (c) terminal of the D-type flip-flop 13. In addition to the input, the output of the first AND circuit 15 is input to the D terminal. Here, the start pulse and the QN output of the D-type flip-flop 13 are input to the first AND circuit 15 so that an AND is obtained. Then, the Q output (Torg test pattern) of the D-type flip-flop 13 and the transfer data with the test pattern transferred from the package A are input to a NAND circuit 17 for comparison, and the comparison result is output to a second AND circuit. 19 and sent to the monitoring result holding unit at the timing of the monitoring pulse. In addition,
FIG. 13 shows the operation timing of the test data detection unit 11. On the other hand, the above-described serial data transfer system (see FIG. 9) is convenient, but has a drawback that a package cannot be easily added. In order to solve the drawback, as shown in FIG. A bus-sharing parallel data transfer system has been proposed, which is connected in parallel to one shared bus 23 to transfer data in parallel.

[0004]

However, when monitoring between packages is performed simply by using the above-described toggle test pattern in the above-mentioned bus-shared parallel data transfer system, the toggle test pattern becomes very small. If a logic circuit for creating a very complicated toggle test pattern is to be formed, the scale of the test data generation / insertion circuit and the test data detection circuit becomes large, which is difficult to realize. In fact, an inter-package monitoring device in such a bus-sharing parallel data transfer system has not been proposed. That is, in the bus shared parallel data transfer system, the following conditions are required to monitor the normality of the shared bus 23 between the package 21 and the receiving package 25 as shown in FIG. The test pattern is toggled so that a 0/1 stuck-at fault can be detected for each bit of the bus 23. Data between adjacent bits of the bus are made different to enable detection of a short circuit in the wiring. Within the same cycle, it may not be possible to determine which package sent the data, so the test data of each package is different (if package 1 sends 5h of test data, package 2 also sends 5h of test data). When the data is transmitted, it is not known whether the data of 5h is from the package 1 or the test data from the package 2 at the receiving end package). Each of the packages 1 to N can transmit a different test pattern by setting so that the same package can be used (because a package can be freely inserted and added). To satisfy the above conditions, the test pattern must be
N types × 2 patterns are required, and there is a problem that the hardware becomes complicated and large-scale when an attempt is made to form a logic circuit for generating and detecting the N × 2 patterns. The present invention has been made in view of the above circumstances, and has an extremely compact circuit configuration to enable constant monitoring between packages in a bus shared parallel data transfer system. The purpose is to provide.

[0005]

In order to achieve the above object, the present invention provides a bus shared parallel data transfer system in which a plurality of packages are connected to a single shared bus and performs parallel data transfer. An inter-package monitoring device for monitoring between a receiving end package provided at a receiving end of the package and a test data generating means for transmitting test data created by using a counter to the shared bus. A test that is provided for each package and obtains a detection result by comparing test data sent from each package via the shared bus with test data created using the same counter as the test generation means. Data detecting means is provided on the receiving end package.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a schematic configuration diagram of an embodiment of a bus shared parallel data transfer system having an inter-package monitoring device according to the present invention. As shown in FIG.
This bus shared parallel data transfer system has a configuration in which a plurality of (in this case, 12) packages 27 are connected in parallel to one shared bus 29, and a receiving end package 31 is connected to the end of the shared bus 29. Has become. Here, the bus width of the shared bus 29 is 5 bits, and when the bus width is 5 bits, the number of the plurality of packages 27 is set to 12 or less. Note that the bus width of the shared bus 29 may be 10 bits, and a case where the bus width is 10 bits will be described as another example. FIG. 2 is an explanatory diagram showing a configuration of an inter-package data transfer frame in the bus shared parallel data transfer system shown in FIG. In FIG. 2, an unused area is fixedly assigned to a leading portion of a repetition period of one frame, and test data for monitoring between packages is assigned to this unused area. That is, the first to twelfth packages 27
2, a fixed time is assigned as shown in FIG. 2, and each package 27 sends monitoring test data to a position assigned to itself. Then, the test data is multiplexed on the shared bus 29 and transmitted to the receiving end package 31. That is, each package 27 outputs test data in accordance with the time allocation in the unused area for each frame.

Next, as described above, each of the packages 27
A circuit for generating the transferred test data inserted into the unused allocation area of the transferred data will be described. FIG.
3 is a configuration diagram of a test data generation circuit provided as a part of the inter-package monitoring device in each package 27. FIG.
As shown in FIG. 3, the test data generation circuit has a test data generation counter 33 for generating test data. A clock is input to a clock input terminal of the test data generation counter 33, An inverted output of the AND circuit 35 and its E terminal are connected to its LD terminal.
A control pulse is input to the P terminal. Here, the AND circuit 35 receives a 64 MF pulse and a decoded version of the output of the test data generation counter 33, and performs an AND operation.
The above decoding is not performed when the bus width is 5 bits).
Then, the output (Turgue test data) of the test data generation counter 33 and the transfer data are input to the selector 37, the selector 37 is switched by the SEL control pulse, and the Trug test pattern data is stored in a predetermined unused area of the transfer data. It is to be inserted. The above S
The EL control pulse is an output of the coincidence comparing section 39. The coincidence comparing section 39 receives the value of the frame counter and the value of the transmission position instructing section 41, and compares the values when both are coincident. The output of the test data generation counter 33 is selected. That is, if the value of the transmission position instruction is set in the transmission position instruction section 41, the test data from the test data generation counter 33 is selected and allocated to the unused area. FIG. 4 shows the operation timing of the test data generation circuit.

Next, the operation of the test data generation circuit will be described with reference to FIG. First, a 64 MF pulse shown in FIG.
(B). Note that each code in FIG. 4B is a hexadecimal code display.
Is synonymous with Then, as shown in FIG.
One count value of the 4MF counter value is one frame (repetition cycle), and one frame is composed of an unused area and a data transfer area. Next, in the unused area, the frame counter value is counted as shown in FIG. 4D, and as shown in FIG. It is assigned to each of the twelve packages 27. That is, FIG.
As shown in (e), for example, a predetermined time of the frame counter value 18 is allocated to the first package 27, and a predetermined time of the frame counter value 1A is allocated to the second package 27. Next, FIG.
4 (g) shows a clock signal and a control pulse signal, respectively, and FIG. 4 (h) shows an output value of the test data generation counter 33. 4D to 4H, the output value OD of the test data generation counter 33 corresponding to the predetermined time 18 (frame counter value) assigned to the first package 27 is selected by the selector 37. Output. By the way,
The output value of the test data generation counter 33 corresponding to the predetermined time 1A (frame counter value) allocated to the second package 27 becomes OE, and the third package 27
The output value of the test data generation counter 33 corresponding to the predetermined allocation time 1C (frame counter value) is OF, and the predetermined allocation time 1E of the fourth package 27 is set.
The output value of the test data generation counter 33 corresponding to (frame counter value) is 10, and the output value of the test data generation counter 33 corresponding to the predetermined time 20 (frame counter value) of the fifth package 27 is 11. Become. Next, FIGS. 4 (i), (j), and (k) are diagrams showing test data transmission timings of the test data generation circuit in the fifth package 27. FIG. The test data from the test data generation counter 33 is as shown in FIG.
Here, the output value of the test data generation counter shown in FIG. This corresponds to the portion surrounded by the bold line 2. The bus width of the bus 29 can be set to 10 bits. In this case, the test data generation counter 33 is a counter for outputting 10-bit test data, and the test data in this case is as shown in FIG. become.

Next, a description will be given of a test data detecting circuit for detecting the test data in the receiving end package 31 to which the transfer data with the test data sent from each package 27 via the bus is input. FIG.
3 is a configuration diagram of a test data detection circuit provided as a part of the inter-package monitoring device in the receiving end package 31. FIG. As shown in FIG. 7, the configuration around the test data generation counter 33 of the test data detection circuit is the same as the configuration around the test data generation counter 33 of the test data generation circuit, and outputs exactly the same test data. It is like. That is, as shown in FIG. 7, the test data detection circuit has a test data generation counter 33 for generating test data, and a clock signal is input to a clock input terminal of the test data generation counter 33. At the same time, the inverted output of the AND circuit 35 is input to the LD terminal and a control pulse is input to the EP terminal. Here, the AND circuit 35 includes 6
The 4MF pulse and the decoded output of the test data generation counter 33 are input and ANDed (however, the decoding is not performed when the bus width is 5 bits). Then, the output (test data) of the test data generation counter 33 and the transfer data with test data sent via the bus 29 are sent to the EXOR logic circuit 43, where the EXOR logic circuit 43 compares them. The first to twelfth package result holding units 45 hold the results. Here, the timing at which the test results are held in each of the first to twelfth package result holding units 45 is determined by a value obtained by decoding the frame counter value by the decoder 47.

Next, the operation of the test data detecting circuit will be described with reference to FIG. First, as shown in FIG. 8B, the frame counter value shown in FIG.
The predetermined time of the frame counter value is the first to twelfth.
Is assigned to each of the packages 27. That is, as shown in FIG. 8B, for example, a predetermined time of the frame counter value 18 is allocated to the first package 27, and a predetermined time of the frame counter value 1A is allocated to the second package 27. ing. Next, FIG.
(C) and (d) show a clock signal and a control pulse signal, respectively, and FIG. 8 (e) shows an output value of the test data generation counter 33. FIG. 8A to FIG.
As can be seen from (e), the output value OD of the test data generation counter 33 corresponding to the predetermined time 18 (frame counter value) assigned to the first package 27 is selected and output by the selector 37. ing. Incidentally, the output value of the test data generation counter 33 corresponding to the predetermined time 1A (frame counter value) of the allocation of the second package 27 becomes OE, and the output value of the test data generation counter 33 corresponds to the predetermined time 1C (frame counter value) of the third package 27. The output value of the corresponding test data generation counter 33 becomes OF, the output value of the test data generation counter 33 corresponding to the predetermined time 1E (frame counter value) allocated to the fourth package 27 becomes 10, and the output value of the fifth package 27 becomes The output value of the test data generation counter 33 corresponding to the assigned predetermined time 20 (frame counter value) of 27 is 11. Next, FIGS. 8F to 8I are time charts showing the holding timings of the test data detection results of the first to twelfth packages, respectively. Specifically, FIGS. To twelfth
The signals sent to the package detection result holding unit 45 are shown.

[0011]

As described above, according to the present invention, a plurality of packages are connected to one shared bus, and in a bus shared parallel data transfer system which performs data transfer in parallel, monitoring of each package is performed. Each package is provided with a test data generation circuit for creating test data using a counter, allocating the data to an unused area of the transfer data and transmitting the data, and detecting the test data transmitted from each package via the bus. The test data detection circuit that holds the detection result compared with the test data created using the same counter is provided in the receiving end package provided at the receiving end of the bus, so that a very compact circuit configuration is provided. This enables constant monitoring between packages in the bus shared parallel data transfer system.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a bus shared parallel data transfer system having an inter-package monitoring device according to the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a data transfer frame between packages in the bus shared parallel data transfer system shown in FIG. 1;

FIG. 3 is a configuration diagram of a test data generation circuit provided in each package as the inter-package monitoring device.

FIG. 4 is a time chart for explaining an operation of the test data generation circuit shown in FIG. 3;

FIG. 5 is a diagram illustrating an example of test data from a test data generation circuit illustrated in FIG. 3;

FIG. 6 is a diagram illustrating an example of test data from a test data generation circuit illustrated in FIG. 3;

FIG. 7 is a configuration diagram of a test data detection circuit provided in the receiving end package as the inter-package monitoring device.

FIG. 8 is a time chart for explaining an operation of the test data detection circuit shown in FIG. 7;

FIG. 9 is an explanatory diagram of a conventional serial data transfer method.

FIG. 10 is a configuration diagram of a test data generation / insertion unit in the serial data transfer method shown in FIG.

FIG. 11 is a time chart for explaining the operation of the test data generation and insertion unit shown in FIG. 10;

FIG. 12 is a configuration diagram of a test data detection unit in the serial data transfer method.

FIG. 13 is a time chart for explaining an operation of the test data detection unit shown in FIG.

FIG. 14 is a configuration diagram of a conventional bus shared parallel data transfer method.

[Explanation of symbols]

1 data line, 3 test data generation and insertion section, 5, 13 ...
D-type flip-flop, 7, 15, 19, 35 ... AND circuit, 9, 37 ... selector, 11 ... test data detector,
17 ... NAND circuit, 21, 27 ... multiple packages, 2
3, 29: shared bus, 31: receiving end package, 33: test data generation counter, 39: comparing unit, 41: sending position indicating unit, 43: EXOR logic circuit, 45: package result holding unit, 47: decoder

Claims (1)

[Claims] 1. In a bus shared parallel data transfer system in which a plurality of packages are connected to one shared bus and perform parallel data transfer, monitoring between each of the packages and a receiving end package provided at a receiving end of the shared bus. And a test data generating unit for transmitting test data created using a counter to the shared bus is provided for each of the packages, and each of the packages is monitored via the shared bus. The receiving end package is provided with test data detecting means for obtaining test results by comparing test data sent from the package with test data created using the same counter as the test generating means. Monitoring device between packages.