JP2002043354A - Flip chip mounting method - Google Patents

Flip chip mounting method

Info

Publication number
JP2002043354A
JP2002043354A JP2000229401A JP2000229401A JP2002043354A JP 2002043354 A JP2002043354 A JP 2002043354A JP 2000229401 A JP2000229401 A JP 2000229401A JP 2000229401 A JP2000229401 A JP 2000229401A JP 2002043354 A JP2002043354 A JP 2002043354A
Authority
JP
Japan
Prior art keywords
load
electrode
electronic component
component element
protruding electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000229401A
Other languages
Japanese (ja)
Inventor
Masafumi Hisataka
将文 久高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000229401A priority Critical patent/JP2002043354A/en
Publication of JP2002043354A publication Critical patent/JP2002043354A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
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    • H01L2924/013—Alloys
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the method of a flip chip for eliminating mounting position deviation at the time of ultrasonic fusion without adding a leveling process. SOLUTION: In this flip chip mounting method, an electronic component element 1 provided with a projection electrode 3 composed of a pedestal part 3a, a chamfer part 3b and a steeple part 3c on a mounting surface is joined to a pad electrode 21 formed on the surface of a prescribed wiring board 2 while impressing a load and ultrasonic vibration. The flip chip mounting method is composed of the first process of abutting the steeple part 3c of the projection electrode 3 to the pad electrode 21 while increasing and impressing the load, the second process of fusing the steeple part 3c of the projection electrode 3 to the pad electrode 21 by impressing the ultrasonic vibration while increasing and impressing the load, and the third process of fusing the chamfer part 3b of the projection electrode 3 to the pad electrode 21 by impressing the ultrasonic vibration while impressing a fixed load or reducing the impressing the load.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は実装底面に突出電極
を有するＩＣチップ、ＳＡＷ素子などの電子部品素子
を、配線基板又はパッケージ等の配線基板に、荷重及び
超音波振動を印加して融着するフリップチップ実装方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fusion of electronic parts such as IC chips and SAW elements having projecting electrodes on the mounting bottom surface to a wiring board such as a wiring board or a package by applying a load and ultrasonic vibration. And a flip-chip mounting method.

【０００２】[0002]

【従来の技術】従来より、ＩＣチップなどの電子部品素
子を高密度に配線基板に実装する方法として、フリップ
チップ実装方法が盛んに使用されている。一般的な例と
として、このフリップチップ実装方法は、突出電極とパ
ッド電極とを当接させ、加熱しながら、荷重及び超音波
振動を与えて超音波融着する方法、突出電極とパッド電
極との間に導電性樹脂を介在させて接合する方法、突出
電極とパッド電極との間に異方性導電樹脂を介在させて
接合する方法、突出電極自身を半田ポールで形成し、こ
の半田の一部を溶融させることによって、パッド電極に
接合する方法などもある。2. Description of the Related Art Conventionally, a flip chip mounting method has been actively used as a method for mounting an electronic component element such as an IC chip on a wiring board at high density. As a general example, this flip chip mounting method is a method in which a protruding electrode and a pad electrode are brought into contact with each other, and while applying heat, a load and ultrasonic vibration are applied to perform ultrasonic fusion, a protruding electrode and a pad electrode, A method in which a conductive resin is interposed between the electrodes and a method of bonding, a method in which an anisotropic conductive resin is interposed between a protruding electrode and a pad electrode, and a method in which the protruding electrode itself is formed by a solder pole and There is also a method of bonding the pad electrode by melting the portion.

【０００３】尚、上述の方法では、突出電極の材料によ
って左右されるが、半田ボールの接合方法を除いては、
金属ワイヤーを用いたボールボンディング方法を用いて
形成されることが一般的である。[0003] In the above method, although it depends on the material of the protruding electrode, except for the method of joining the solder balls,
It is general that it is formed using a ball bonding method using a metal wire.

【０００４】この金属ワイヤーを用いたボールボンディ
ング方法による突出電極は、キャピラリーの先端から突
出する部分をトーチなどで溶融したワイヤーを、電子部
品素子の実装面に形成された入出力パッド上に押し当
て、次に、溶融した部分を上方に延伸させることにより
形成していた。A protruding electrode formed by a ball bonding method using a metal wire presses a wire whose portion protruding from the tip of a capillary is melted by a torch or the like onto an input / output pad formed on a mounting surface of an electronic component element. Then, the melted portion was formed by stretching upward.

【０００５】これにより、突出電極は、電子部品素子の
入出力パッド側から、ワイヤー先端の溶融及び押圧によ
り形成されるバンプ台座部と、該台座部上でワイヤーキ
ャピラリーの先端形状で規制されて形成されるチャンフ
ァ部と、該チャンファ部上にワイヤーの延伸により形成
される尖塔部とから構成されてる。尚、突出電極の材料
として、Ａｕ、Ｃｕ、Ａｇ等を用いることができる。Accordingly, the protruding electrode is formed from the input / output pad side of the electronic component element by being regulated by the bump pedestal formed by melting and pressing the tip of the wire and the tip of the wire capillary on the pedestal. And a spire formed by drawing a wire on the chamfer. Note that Au, Cu, Ag, or the like can be used as a material for the protruding electrode.

【０００６】[0006]

【発明が解決しようとする課題】突出電極を有するＩＣ
チップ等を超音波圧着する方法としては、特開平１１−
７４３１５及び特開平１１−１０２９３３に例示されて
いるように、荷重、超音波振動を同時に印加を開始し、
階段状に荷重、超音波振動の印加をする方法があった。
このように荷重と超音波振動とを同時に印加する方法で
は、突出電極の尖塔部を潰し始める時点に、即ち、その
尖塔部が充分に潰れてない状態で超音波振動が印加され
る。このような印加方法では、突出電極とパッド電極と
の間にほとんど摩擦がない状態であり、超音波振動を印
加すると、電子部品素子自身が動いてしまい、結局は、
実装位置のずれが発生してしまう。SUMMARY OF THE INVENTION IC having a protruding electrode
As a method for ultrasonically pressing a chip or the like, see Japanese Patent Application Laid-Open
74315 and Japanese Patent Application Laid-Open No. H11-102933, the load and the application of ultrasonic vibration are simultaneously started,
There is a method of applying a load and ultrasonic vibration in a stepwise manner.
In the method of simultaneously applying the load and the ultrasonic vibration, the ultrasonic vibration is applied at the time when the spire of the projecting electrode starts to be crushed, that is, in a state where the spire is not sufficiently crushed. In such an application method, there is almost no friction between the protruding electrode and the pad electrode, and when ultrasonic vibration is applied, the electronic component element itself moves, and eventually,
The mounting position shifts.

【０００７】また、荷重、超音波振動を同時に階段的に
増加印加する方法では、接合条件が強くなりすぎること
があり、電子部品素子にクレタリングを起こすことがあ
る。Further, in the method in which the load and the ultrasonic vibration are simultaneously increased stepwise, the joining conditions may be too strong, and cretering may occur in the electronic component element.

【０００８】さらに、荷重が強すぎると超音波振動を抑
制し、突出電極の潰れ面積の割に超音波融着による接合
が不充分となってしまう。Further, if the load is too strong, the ultrasonic vibration is suppressed, and the bonding by the ultrasonic fusion becomes insufficient for the crushed area of the protruding electrode.

【０００９】特に、上述のボールホンディング方法によ
る突出電極では、例えばＡｕ線をに延伸によりワイヤー
を引き切りるため、突出電極の高さ、特に、尖塔部の高
さにバラツキが発生するため、１つの電子部品素子中で
あっも、突出電極の高さがバラツキ、１つの電子部品素
子を実装する場合でも、全ての同じ条件で荷重印加と超
音波振動印加を与えることができない。Particularly, in the case of the protruding electrode formed by the above-described ball bonding method, since the wire is cut off by, for example, drawing an Au wire, the height of the protruding electrode, particularly the height of the spire portion, varies, so that Even in one electronic component element, even if the height of the protruding electrode varies, and even if one electronic component element is mounted, it is impossible to apply the load and the ultrasonic vibration under all the same conditions.

【００１０】例えば、突出電極の潰し過ぎが起こった場
合は、突出電極と基板間に必要以上の時間で荷重及び超
音波振動が印加されてしまうため、突出電極とパッド電
極との間の接合部にダメージを与えてしまう問題があっ
た。さらに、電子部品素子と配線基板との間隔が狭くな
り、例えば、アンダーフィル樹脂（電子部品素子と基板
との間に供給され、機械的な接合強度を補う樹脂）の充
填不足が生じてしまうという問題があった。[0010] For example, if the protruding electrode is crushed too much, a load and ultrasonic vibration are applied between the protruding electrode and the substrate for an unnecessarily long time. There was a problem that would cause damage. Further, the space between the electronic component element and the wiring board is reduced, and for example, insufficient filling of underfill resin (resin supplied between the electronic component element and the substrate and supplementing mechanical bonding strength) occurs. There was a problem.

【００１１】また、突出電極の高さを安定させるため
に、従来、１つの電子部品素子に突出電極を形成したの
ち、尖塔経部の一部を機械的に潰して、全ての突出電極
の高さを揃えるフラットニング工程を行うこともあっ
た。このフラットニング工程では、工程付加となり、生
産性を悪化させることになる。Further, in order to stabilize the height of the protruding electrodes, conventionally, after forming the protruding electrodes on one electronic component element, a part of the spire portion is mechanically crushed, and the height of all the protruding electrodes is increased. In some cases, a flattening process was performed to adjust the uniformity. In the flattening step, a step is added, and the productivity is deteriorated.

【００１２】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的は、工程の付加を行うことな
く、超音波融着時に、実装位置ずれがないフリップチッ
プの方法を提供することにある。The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a method of a flip chip which does not have a mounting position shift at the time of ultrasonic welding without adding a process. To provide.

【００１３】[0013]

【課題を解決するための手段】本発明は、実装面にワイ
ヤのボールボンデングにより形成した突出電極を有する
電子部品素子を、荷重、超音波振動を印加しならが、所
定配線基板の表面に形成したパッド電極に接合して成る
フリップチップ実装方法において、前記電子部品素子の
突出電極が、ワイヤー先端の溶融及び押圧により形成さ
れるバンプ台座部と、該台座部上でワイヤーキャピラリ
の先端形状で規制されて形成されるチャンファ部と、該
チャンファ部上にワイヤーの延伸により形成される尖塔
部とからなり、パッド電極への突出電極の接合が、前記
突出電極の尖塔部を、荷重を増加印加しながら前記パッ
ド電極に当接する第１の工程と、前記突出電極の尖塔部
を、荷重の増加印加しながら、超音波振動を印加してパ
ッド電極に融着する第２の工程と、前記突出電極のチャ
ンファ部を、一定荷重または荷重の減少印加しながら、
超音波振動を印加してパッド電極に融着する第３の工程
と、から成ることを特徴とするフリップチップ実装方法
である。According to the present invention, an electronic component element having a protruding electrode formed by ball bonding of a wire on a mounting surface is formed by applying a load and ultrasonic vibration to a surface of a predetermined wiring board. In the flip-chip mounting method of bonding to the formed pad electrode, the projecting electrode of the electronic component element has a bump pedestal formed by melting and pressing the tip of the wire, and a tip shape of the wire capillary on the pedestal. Consisting of a restricted chamfer portion and a spire portion formed by drawing a wire on the chamfer portion, the joining of the protruding electrode to the pad electrode increases the load on the spire portion of the protruding electrode. A first step of abutting on the pad electrode while applying an ultrasonic load to the spike of the protruding electrode while applying an increased load to the pad electrode. A second step, the chamfer portion of the projecting electrode, while reducing the application of a constant load or a load,
A third step of applying ultrasonic vibration and fusing to the pad electrode.

【００１４】[0014]

【発明の実施の形態】以下に、本発明のフリップチップ
の実装方法を図面に基づいて説明する。図１は、本発明
のフリップチップ実装方法にかかる電子部品素子を配線
基板にフリップチップ実装した状態の側面図であり、図
２は、電子部品素子に突出電極を形成した状態の側面図
であり、図３はボンディン方法の実装条件を示すタイミ
ングチャート図である。尚、図４は本発明の一実施例で
あるフリップチップボンディング装置の概略図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting a flip chip according to the present invention will be described below with reference to the drawings. FIG. 1 is a side view showing a state in which an electronic component element according to the flip chip mounting method of the present invention is flip-chip mounted on a wiring board, and FIG. 2 is a side view showing a state in which protruding electrodes are formed on the electronic component element. FIG. 3 is a timing chart showing the mounting conditions of the bonding method. FIG. 4 is a schematic view of a flip chip bonding apparatus according to one embodiment of the present invention.

【００１５】図において、１は電子部品素子、２は配線
基板であり、３は突出電極である。電子部品素子１は、
例えばＩＣチップやＳＡＷ素子などが用いられる。そし
て、配線基板２側の実装面には、ＩＣチップやＳＡＷ素
子などの電源供給、接地接続、信号入出力などを行うた
めの入出力パッド１１が形成されている。そして、図２
に示すように、この入出力パッド１１上に、突出電極３
が形成されている。この突出電極３は、入出力パッド１
１側から球体が上下方向に押しつぶされた形状のバンプ
台座部３ａ、キャピラリの先端形状で規制されて、概略
円台形状のチャンファ部３ｂと、ワイヤーの延伸により
形成される尖塔部３ｃとからなっている。In the figure, 1 is an electronic component element, 2 is a wiring board, and 3 is a protruding electrode. The electronic component element 1
For example, an IC chip or a SAW element is used. On the mounting surface on the wiring board 2 side, input / output pads 11 for power supply, ground connection, signal input / output, and the like of IC chips and SAW elements are formed. And FIG.
As shown in FIG.
Are formed. The projecting electrode 3 is connected to the input / output pad 1
A bump pedestal portion 3a having a shape in which a sphere is crushed vertically from the first side, a chamfer portion 3b having a substantially circular trapezoidal shape regulated by the tip shape of the capillary, and a spire portion 3c formed by extending a wire. ing.

【００１６】また、配線基板２は、平板状の回路基板や
キャビティー部を有するセラミックパッケージなどが用
いられ、回路基板の表面やキャビティー部の底面には、
電子部品素子１の突起電極３と接合するパッド電極２１
が形成されている。Further, as the wiring board 2, a flat circuit board or a ceramic package having a cavity is used, and the surface of the circuit board or the bottom of the cavity is provided on the circuit board.
Pad electrode 21 to be joined to bump electrode 3 of electronic component element 1
Are formed.

【００１７】上述の突出電極３は、例えば、Ａｕワイヤ
を用いて、そのボールボンディング方法によって形成さ
れる。具体的には、ワイヤキャラリーの先端から所定量
のワイヤを延出させて、この突出部分にトーチなどで加
熱し、その先端を溶融させる。この状態で、ワイヤーを
電子部品素子１の入出力パッドに押圧して、ワイヤと電
子部品素子１の入出力パッド２とを融着させる。その
後、ワイヤ自身を上方に延伸して、ワイヤ先端の溶融部
分とワイヤとの境界部分で引き切る。これより、突出電
極３は、上述したように、バンプ台座部３ａ、キャピラ
リの先端形状（キャピラリーのインサイドチャンプア部
分）で規制されたチャンファ部３ｂと、延伸により形成
される尖塔部３ｃが形成されることになる。尚、延伸
を、単に上方に引き延ばした場合には、図２のようにを
上方に延びる尖塔部となり、また、上方の延伸に続い
て、横方向にせり切りした場合には、途中が屈曲した尖
塔部となり、さらに、上方の延伸に続いて、ヘアピン状
に下方に延伸させた場合、先端がＵ字状となった尖塔部
が得られる。The above-mentioned protruding electrode 3 is formed by, for example, an Au wire by a ball bonding method. Specifically, a predetermined amount of the wire is extended from the tip of the wire carrier, and the projecting portion is heated with a torch or the like to melt the tip. In this state, the wire is pressed against the input / output pad of the electronic component element 1 to fuse the wire and the input / output pad 2 of the electronic component element 1. Thereafter, the wire itself is extended upward and cut off at the boundary between the molten portion at the wire tip and the wire. Thus, as described above, the protruding electrode 3 has the bump pedestal portion 3a, the chamfer portion 3b regulated by the tip shape of the capillary (the inside champa portion of the capillary), and the spire portion 3c formed by extension. Will be. In addition, when extending | stretching is simply extended upward, it becomes the spire part which extends upward like FIG. When a spire portion is formed and further extended downward in a hairpin shape following the upward extension, a spire portion having a U-shaped tip is obtained.

【００１８】尚、ワイヤーを引き千切るり位置が安定す
るように、Ｐｄなどが微量に添加されたＡｕワイヤーを
用いることが望ましい。It is desirable to use an Au wire to which a small amount of Pd or the like is added so that the position where the wire is torn is stabilized.

【００１９】一方、配線基板２のパッド電極は、基板材
料のセラミックの表面に、タングステン（Ｗ）やモリブ
デン（Ｍｏ）などの下地導体膜が形成され、さらにその
表面にＮｉメッキ、Ａｕメッキが施されている。On the other hand, the pad electrode of the wiring board 2 has a base conductor film such as tungsten (W) or molybdenum (Mo) formed on a ceramic surface of a substrate material, and further, Ni plating and Au plating are applied to the surface. Have been.

【００２０】次に、本発明のフリップチップ実装方法に
ついて、実装後の構造（図１）及び実装装置（図４）を
交えて説明する。Next, the flip chip mounting method of the present invention will be described with reference to the structure after mounting (FIG. 1) and the mounting apparatus (FIG. 4).

【００２１】実装装置は、電子部品素子１の実装面と対
向する上面側を真空吸着するツール４１、ツール４１を
支持し、且つ所定超音波振動を発生する超音波振動子４
２及びトランスジューサ４３、ツール４１に吸着された
電子部品素子１を所定位置に回転方向させ、上下方向に
移動させるとともに、電子部品素子１に印加する荷重量
を制御する制御系を有している。例えば、図面奥行方向
を制御するＸ軸駆動部４４、図面の上下方向の動作を制
御するｚ軸駆動部４５、回転軸を中心に動作するθ回転
駆動部４６とを有している。The mounting apparatus includes a tool 41 for vacuum-sucking the upper surface of the electronic component element 1 opposite to the mounting surface, an ultrasonic vibrator 4 for supporting the tool 41 and generating a predetermined ultrasonic vibration.
2, a transducer 43, and a control system for rotating the electronic component element 1 sucked by the tool 41 to a predetermined position, moving the electronic component element 1 vertically, and controlling the amount of load applied to the electronic component element 1. For example, it has an X-axis drive unit 44 that controls the depth direction of the drawing, a z-axis drive unit 45 that controls the operation in the vertical direction of the drawing, and a θ rotation drive unit 46 that operates around the rotation axis.

【００２２】また、ツール４１は、吸着孔４７が形成さ
れ、該孔が真空源に接続されている。さらに、ツール４
１の先端部分は、図示していないが、加熱手段を有して
おり、ツールで吸着保持した電子部品素子１を所定温度
に加熱可能となっている。The tool 41 has a suction hole 47 formed therein, and the hole is connected to a vacuum source. In addition, tool 4
Although not shown, the distal end of 1 has a heating means, and can heat the electronic component element 1 sucked and held by the tool to a predetermined temperature.

【００２３】また、ワーク固定側装置は、ワークを固定
する固定台５１、固定台５１を加熱する加熱台５２、固
定台のＸ−Ｙ方向、さらに、Ｚ軸方向に位置合わせする
ための駆動部５３とから構成されている。この固定台５
１と加熱台５２とは吸着孔５５とで連通しており、真空
源に接続されているぁ上述のように、パッド電極２１が
形成された配線基板２は、ワーク固定台５１のキャビテ
ィー部内に保持され、吸気孔５５を介して固定されるこ
とになる。さらに加熱台５２により、配線基板２は所定
温度に加熱され、超音波振動による融着信頼性を向上さ
せるようになっている。The work fixing side device includes a fixing stand 51 for fixing the work, a heating stand 52 for heating the fixing stand 51, and a drive unit for positioning the fixing stand in the X-Y direction and the Z-axis direction. 53. This fixed base 5
1 and the heating table 52 are communicated with each other through the suction hole 55 and are connected to a vacuum source. As described above, the wiring board 2 on which the pad electrodes 21 are formed is located inside the cavity of the work fixing table 51. And is fixed via the intake hole 55. Further, the wiring board 2 is heated to a predetermined temperature by the heating table 52, so that the reliability of fusion by ultrasonic vibration is improved.

【００２４】また、ツール４１の先端には、電子部品素
子１の実装面と対向する面が吸着により保持され、画像
認識などによって、Ｘ駆動部４４、Ｚ軸駆動部４５、さ
らに、回転駆動部４６によって、電子部品素子１が配線
基板２の所定位置に実装されるように所定位置に位置決
めされることになる。At the tip of the tool 41, a surface facing the mounting surface of the electronic component element 1 is held by suction, and an X drive unit 44, a Z-axis drive unit 45, and a rotation drive unit are recognized by image recognition or the like. By 46, the electronic component element 1 is positioned at a predetermined position so as to be mounted at a predetermined position on the wiring board 2.

【００２５】次に、実際のフリップフチップ実装の接合
方法について説明する。Next, a method of actual flip-chip mounting will be described.

【００２６】ワーク固定台５１内の配線基板２と、ツー
ル４１に保持された電子部品素子１との位置決めが完了
した後、例えば、加熱台５２やツール４１側の加熱手段
により配線基板２及び電子部品素子１を加熱処理する。
尚、熱の直接的な印加により、特性が変動する電子部品
素子１の場合には、加熱は固定台５１側のみで行うこと
が望ましい。例えば、加熱によって温められる温度は、
例えば２００℃である。After the positioning of the wiring board 2 in the work fixing table 51 and the electronic component element 1 held by the tool 41 is completed, for example, the wiring board 2 and the electronic device are heated by the heating means 52 or the heating means on the tool 41 side. The component element 1 is heated.
In addition, in the case of the electronic component element 1 whose characteristics fluctuate by direct application of heat, it is desirable that heating be performed only on the fixed base 51 side. For example, the temperature heated by heating is
For example, it is 200 ° C.

【００２７】次に、紙面の上下方向、例えばＺ軸駆動部
４５を制御して、ツール４１に保持された電子部品素子
１の実装面が、ワーク固定台５１に保持された配線基板
２の所定位置にまで降下させる。この降下によって、電
子部品素子１の突出電極３の尖塔部３ｃが、配線基板２
の所定パッド電極２１に接触したとする。この状態は、
図３（ａ）に示す上下駆動系において「下降」で示す領
域である。この接触した状態より、実際の接合処理が行
われる。Next, the mounting surface of the electronic component element 1 held by the tool 41 is controlled by controlling the vertical direction of the paper surface, for example, the Z-axis drive unit 45, so that the mounting surface of the wiring board 2 held by the work fixing table 51 is fixed. Lower to position. Due to this drop, the spire portion 3c of the protruding electrode 3 of the electronic component element 1
Is assumed to be in contact with the predetermined pad electrode 21. This state is
This is a region indicated by “down” in the vertical drive system shown in FIG. From this contact state, the actual bonding process is performed.

【００２８】本発明者は、上述の実装方法について、特
に、第１の工程から第２の工程に移行する際の荷重点
（第１の荷重点ｘという）及び第２の工程から第３の工
程に移行する際の荷重点（第２の荷重点ｙという）につ
いて調べた。The inventor of the present invention has described the above mounting method, in particular, the load point (referred to as a first load point x) when shifting from the first step to the second step, and the third step from the second step. A load point (referred to as a second load point y) at the time of shifting to the process was examined.

【００２９】尚、第１の荷重点ｘについては、主に第２
の工程で超音波振動を与えた時の位置ずれに着目して、
その評価を行った。また、第２の荷重点ｙとして、主に
接合（超音波融着ににおけるシェア強度）、その破壊モ
ード（バンプ基板残り率）及びクレタリグの発生率に基
づいて評価を行った。The first load point x mainly corresponds to the second load point x.
Pay attention to the displacement when applying ultrasonic vibration in the process of
The evaluation was performed. Further, as the second load point y, evaluation was performed mainly based on bonding (shear strength in ultrasonic welding), its destruction mode (remaining ratio of bump substrate), and the occurrence rate of crate rig.

【００３０】尚、クレタリングは、ＩＣチップなど電極
下の基材のクラックであり、その発生確認は、フリップ
チップ実装接合後、王水に常温で１時間浸漬してＡｕを
溶解して電子部品素子電極を検査した。[0030] The cretering is a crack in a substrate under an electrode such as an IC chip. The occurrence of the crack is confirmed by flip-chip mounting and then immersing in aqua regia at room temperature for 1 hour to dissolve Au to dissolve the electronic component. The device electrodes were inspected.

【００３１】また、フリップチップ実装後のシェア強度
測定試験での破壊モードにおいて、突出電極３が配線基
板２に残存する率で示している。仮に１００％とは、突
出電極３と配線基板２のパッド電極２１との接合強度
が、電子部品素子１の入出力パッド１１と突出電極３と
の接合強度を上回っているが、電子部品素子１と突出電
極３との間にダメージを接合強度が劣化していることを
示している。Further, in the destruction mode in the shear strength measurement test after the flip chip mounting, the ratio of the protruding electrode 3 remaining on the wiring board 2 is shown. Supposing that 100% means that the bonding strength between the protruding electrode 3 and the pad electrode 21 of the wiring board 2 is higher than the bonding strength between the input / output pad 11 of the electronic component element 1 and the protruding electrode 3. This indicates that the bonding strength between the electrode and the protruding electrode 3 is deteriorated.

【００３２】実装方法では、まず、図３（ａ）は、ｚ軸
駆動部４５の制御による上下駆動系の動作を示し、図３
（ｂ）では、上下駆動系と連動し、実際に電子部品素子
1から配線基板２に印加される１突出電極あたりの荷重
量の推移を示し、図３（ｃ）は、振動素子４２の動作に
よる超音波振動出力の状態の推移を示すものである。In the mounting method, first, FIG. 3A shows the operation of the vertical drive system under the control of the z-axis drive unit 45.
In (b), the electronic component element is actually operated in conjunction with the vertical drive system.
3 shows the transition of the amount of load per one protruding electrode applied to the wiring board 2 from 1, and FIG. 3C shows the transition of the state of the ultrasonic vibration output by the operation of the vibration element 42.

【００３３】まず、実装方法の始めとして、電子部品素
子１の突出電極３が配線基板２のパッド電極２１に接触
するまで、図３（ａ）に示す上下駆動系で「下降」を行
う。そして、点Ａで、実質的に電子部品素子１の突出電
極３の先端が配線基板２のパッド電極２１に接触する。First, at the beginning of the mounting method, "down" is performed by the vertical drive system shown in FIG. 3A until the protruding electrode 3 of the electronic component element 1 contacts the pad electrode 21 of the wiring board 2. Then, at the point A, the tip of the protruding electrode 3 of the electronic component element 1 substantially contacts the pad electrode 21 of the wiring board 2.

【００３４】次に、第１の工程（点Ａ〜点Ｂ）は、図３
（ｃ）に示すように、超音波振動を供給しない状態で、
図３（ａ）に示すように、「低速下降」を行う。尚、こ
の下降速度は、１８０μｍ／０．３秒である。また、図
３（ｂ）に示すように、荷重量の推移は、０〜例えば１
５ｇｆ／バンプと暫時増加印加されるものである。即
ち、第１の荷重点ｘは、例えば１５ｇｆ／バンプであ
る。この目安として、少なくとも、電子部品素子１の実
装面に形成された複数の突出電極３の高さのバラツキを
充分に緩和だけの量の尖塔部３ｃの先端を潰するように
する。即ち、複数の突出電極３の高さの差がΔｈとする
と、この第１の工程で潰される尖塔部３ｃの量は、最も
高い突出電極３を基準にして、少なくともΔｈ以上を潰
すことになる。Next, the first step (points A and B) is as shown in FIG.
As shown in (c), without supplying ultrasonic vibration,
As shown in FIG. 3A, "low speed descent" is performed. The lowering speed is 180 μm / 0.3 second. Also, as shown in FIG. 3B, the transition of the load amount is 0 to, for example, 1
The applied voltage is increased to 5 gf / bump for a while. That is, the first load point x is, for example, 15 gf / bump. As a guide, at least the tip of the spire portion 3c is squeezed in such an amount that the variation in height of the plurality of protruding electrodes 3 formed on the mounting surface of the electronic component element 1 is sufficiently reduced. That is, assuming that the difference between the heights of the plurality of projecting electrodes 3 is Δh, the amount of the spire portion 3c that is crushed in the first step is at least Δh or more with respect to the highest projecting electrode 3. .

【００３５】この第１の工程では、突出電極３の尖塔部
３Ｃの先端部分が潰れ、配線基板２のパッド電極と突出
電極３との当接面積が増大し、もって、この間の摩擦力
が大きくなり、第２の工程に移行（超音波振動を印加）
しても、その振動による位置ずれを有効に抑えることが
できる。In the first step, the tip of the spire 3C of the protruding electrode 3 is crushed, and the contact area between the pad electrode of the wiring board 2 and the protruding electrode 3 is increased, so that the frictional force therebetween is large. And proceed to the second step (ultrasonic vibration is applied)
However, the displacement caused by the vibration can be effectively suppressed.

【００３６】ここで、第１の工程の終点である荷重を１
０ｇｆ／バンプに設定すると、第２の工程による超音波
振動による位置ずれが発生してしまう。また、逆に２０
ｇｆ／バンプを越える値に設定すると、荷重が強すぎる
ため突出電極３が超音波接合する前に必要以上塑性変形
し、その結果接合面積が減少するという問題が発生す
る。Here, the load, which is the end point of the first step, is set to 1
If it is set to 0 gf / bump, a displacement will occur due to ultrasonic vibration in the second step. Conversely, 20
If the value is set to a value exceeding gf / bump, the load is too strong, so that the protruding electrode 3 is plastically deformed more than necessary before ultrasonic bonding, and as a result, a problem occurs in that the bonding area is reduced.

【００３７】次に、図３（ａ）に示す上下駆動系の「低
速下降」、（図３（ｂ）の荷重暫時増加印加）しなが
ら、図４（ｃ）に示すように、超音波振動の供給を行う
第２の工程である。Next, as shown in FIG. 4C, while the vertical drive system shown in FIG. 3A is "lower-lowering" (temporarily increasing the load in FIG. 3B), as shown in FIG. This is the second step of supplying the water.

【００３８】この工程は、点Ｂ〜点Ｃの領域であり、第
１の荷重点ｘ（例えば１５ｇｆ／バンプ）〜第２の荷重
点ｙ（例えば、４０ｇｆ／バンプ）に達するまでの領域
である。This step is an area from point B to point C, and is an area from the first load point x (for example, 15 gf / bump) to the second load point y (for example, 40 gf / bump). .

【００３９】この第２の工程で、概ね突出電極３の尖塔
部３ｃが完全に潰れてしまい、突出電極３の直径が大き
くなる尖塔部３ｃとチャンフア部３ｂとの境界領域が配
線基板２のパッド電極２１に融着接合する状態となる。In the second step, the spire 3c of the protruding electrode 3 is almost completely crushed, and the boundary region between the spire 3c and the chamfer 3b, where the diameter of the protruding electrode 3 becomes large, is formed on the pad of the wiring board 2. It will be in a state of fusion bonding to the electrode 21.

【００４０】例えば、第２の荷重点ｙを、例えば４０ｇ
ｆ／バンプとすると、接合強度（シェア強度）が例え
ば、５０ｇｆ／バンプを越え、例えば５２ｇｆ／バンプ
となる。そして、その剥離モードは、パンプ基板残り率
が７０％となり、突出電極３のチャンフア部３ｂ部分で
破壊されることになる。これにより、充分な接合が達成
できていることが理解できる。For example, if the second load point y is, for example, 40 g
When f / bump is used, the bonding strength (shear strength) exceeds, for example, 50 gf / bump, and becomes, for example, 52 gf / bump. In the peeling mode, the remaining ratio of the pump substrate becomes 70%, and the bump electrode 3 is broken at the portion 3 b of the protruding electrode 3. Thus, it can be understood that sufficient bonding has been achieved.

【００４１】この第２の荷重点ｙが、例えば４０ｇｆ／
バンプを下回り、例えば、３０ｇｆ／バンプとなると、
接合強度（シェア強度）が例えば、４４ｇｆ／バンプと
なり、充分な接合強度が得られない。そして、その破壊
モード（パンプ基板残り率が５５％となり、例えば、突
出電極３のチャンフア部３ｂ部分と尖塔部３ｃとの境界
付近で剥離切離されてしまう。これでは、充分な接合が
達成できていないことになる。When the second load point y is, for example, 40 gf /
Below the bump, for example, 30 gf / bump,
The bonding strength (shear strength) is, for example, 44 gf / bump, and a sufficient bonding strength cannot be obtained. Then, in the destruction mode (the pump substrate remaining rate becomes 55%, for example, the protruding electrode 3 is separated and separated in the vicinity of the boundary between the chamfer portion 3b and the spire portion 3c. In this case, sufficient bonding can be achieved. Will not be.

【００４２】また、この第２の荷重点ｙが、例えば５０
ｇｆ／バンプ、６０ｇｆ／バンプ、となるともると、接
合強度（シェア強度）が５８ｇｆ／バンプ、４４ｇｆ／
バンプ、となる。即ち、４０〜５０ｇｆ／バンプに接合
強度のピークが存在することになる。そして、その破壊
モードが、パンプ基板残り率が８０％、１００％とな
り、電子部品素子１の入出力パッド１１の直ぐ近傍また
は、入出力パッド１１と突出電極３との接合部分で剥離
切離されてしまう。このようにバンプ基板残り率が８０
〜１００％となると、超音波振動が直接または多大な力
が、電子部品素子１に加わることになり、電子部品素子
１にダメージを与えることになる。The second load point y is, for example, 50
gf / bump, 60 gf / bump, and bonding strength (shear strength) of 58 gf / bump, 44 gf / bump.
Bumps. That is, the peak of the bonding strength exists at 40 to 50 gf / bump. In the destruction mode, the remaining ratio of the pump substrate is 80% and 100%, and the delamination is performed in the vicinity of the input / output pad 11 of the electronic component element 1 or at the junction between the input / output pad 11 and the protruding electrode 3. Would. Thus, the remaining bump substrate ratio is 80.
When it becomes １００100%, the ultrasonic vibration is applied directly or a great force to the electronic component element 1, and the electronic component element 1 is damaged.

【００４３】以上のように、第１の荷重点ｘは、１５〜
２０ｇｆ／バンプが有効であり、第２の荷重点ｙは、３
０〜５０ｇｆ／バンプ、特に、４０ｇｆ／バンプ前後の
値が望ましい。As described above, the first load point x is 15 to
20 gf / bump is effective, and the second load point y is 3
A value of 0 to 50 gf / bump, particularly a value around 40 gf / bump is desirable.

【００４４】この第３の工程は、点Ｃ〜Ｄの領域であ
り、第２の荷重点ｙの荷重、例えば４０ｇｆ／バンプを
維持し、しかも、一定の超音波振動を供給する。この工
程では、突出電極３のチャンファ部３ｂ領域において、
超音波融着を行い、充分な接合を行うものである。そし
て、所定の時間、例えば０．６秒後に超音波印加を終了
しツールを上昇し実装工程を終了させた。The third step is an area between points C and D, and maintains a load of the second load point y, for example, 40 gf / bump, and supplies a constant ultrasonic vibration. In this step, in the region of the chamfer portion 3b of the protruding electrode 3,
Ultrasonic fusion is performed to perform sufficient bonding. Then, after a predetermined time, for example, 0.6 seconds, the application of the ultrasonic wave was terminated, the tool was raised, and the mounting process was terminated.

【００４５】この第３の工程で、荷重を維持または逆に
減少させることが望ましい。これは、突出電極３のチャ
ンファ部３ｂの融着において、このチャンファ部３ｂを
過度に潰さないようにするためである。In the third step, it is desirable to maintain or reduce the load. This is to prevent the chamfer portion 3b from being excessively crushed in the fusion of the chamfer portion 3b of the protruding electrode 3.

【００４６】尚、上述の実施例では、ボールボンディン
グ方法によりワイヤを用いて突出電極を形成した全ての
電子部品素子に広く適用できるものである。In the above-described embodiment, the present invention can be widely applied to all electronic component elements in which projecting electrodes are formed using wires by a ball bonding method.

【００４７】[0047]

【発明の効果】以上のように、フリップチップの実装方
法では、第１の工程から第２の工程に移行しても、電子
部品素子１の位置ずれを有効に抑えることができ、しか
も、各突出電極の高さバラツキも有効に許容でき、従来
のレベリング加工工程も一切不要となり、さらに、強固
な接合及び電子部品素子にダメージを与えることがない
プリップチップ実装方法となる。As described above, in the flip-chip mounting method, even if the process shifts from the first process to the second process, the displacement of the electronic component element 1 can be effectively suppressed. Variations in the height of the protruding electrodes can be effectively tolerated, and the conventional leveling process is not required at all. Further, a method of mounting a flip chip that does not damage the strong bonding and the electronic component elements is provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】電子部品素子を配線基板にフリップチップ実装
した状態の側面図である。FIG. 1 is a side view showing a state in which an electronic component element is flip-chip mounted on a wiring board.

【図２】電子部品素子に突出電極を形成した状態の側面
図である。FIG. 2 is a side view showing a state in which protruding electrodes are formed on the electronic component element.

【図３】ボンディング方法の実装条件を示すタイミング
チャート図であり、（ａ）は上下駆動系の動作の推移を
示し、（ｂ）は荷重の推移を示し、（ｃ）は超音波振動
出力の推移を示す。3A and 3B are timing charts showing mounting conditions of a bonding method, wherein FIG. 3A shows a transition of an operation of an up-down driving system, FIG. 3B shows a transition of a load, and FIG. Shows the transition.

【図４】フリップチップボンディング装置の概略図であ
る。FIG. 4 is a schematic view of a flip chip bonding apparatus.

【符号の説明】[Explanation of symbols]

１・・電子部品素子 １１・・入出力パッド ２・・配線基板 ２１・・パッド電極 ３・・突出電極 ３ａ・・台座部 ３ｂ・・チャンファ部 ３Ｃ・・尖塔部 1, electronic component element 11, input / output pad 2, wiring board 21, pad electrode 3, protruding electrode 3a, base 3b, chamfer 3C, spire

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 実装面にワイヤのボールボンデングによ
り形成した突出電極を有する電子部品素子を、荷重、超
音波振動を印加しならが、所定配線基板の表面に形成し
たパッド電極に接合して成るフリップチップ実装方法に
おいて、 前記電子部品素子の突出電極が、ワイヤー先端の溶融及
び押圧により形成されるバンプ台座部と、該台座部上で
ワイヤーキャピラリーの先端形状で規制されて形成され
るチャンファ部と、該チャンファ部上にワイヤーの延伸
により形成される尖塔部とからなり、 パッド電極への突出電極の接合が前記突出電極の尖塔部
を、荷重を増加印加しながら前記パッド電極に当接する
第１の工程と、 前記突出電極の尖塔部を、荷重の増加印加しながら、超
音波振動を印加してパッド電極に融着する第２の工程
と、 前記突出電極のチャンファ部を、一定荷重または荷重の
減少印加しながら、超音波振動を印加してパッド電極に
融着する第３の工程と、から成ることを特徴とするフリ
ップチップ実装方法。An electronic component element having a protruding electrode formed by ball bonding of a wire on a mounting surface is bonded to a pad electrode formed on the surface of a predetermined wiring board by applying a load and ultrasonic vibration. In the flip chip mounting method, the protruding electrode of the electronic component element is formed by melting and pressing a tip of a wire, and a bump portion formed on the pedestal portion by being restricted by a tip shape of a wire capillary. And a spire portion formed by extending a wire on the chamfer portion, and the joining of the protruding electrode to the pad electrode causes the spire portion of the protruding electrode to contact the pad electrode while increasing the load. A second step of applying ultrasonic vibration to the spire of the protruding electrode while applying an increase in load to fuse the spire to the pad electrode; The chamfer portion of the electrode, while reducing the application of a constant load or a load, a third step and, a flip chip mounting method which is characterized in that it consists of fusing the pad electrode by applying ultrasonic vibration.
JP2000229401A 2000-07-28 2000-07-28 Flip chip mounting method Pending JP2002043354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000229401A JP2002043354A (en) 2000-07-28 2000-07-28 Flip chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000229401A JP2002043354A (en) 2000-07-28 2000-07-28 Flip chip mounting method

Publications (1)

Publication Number Publication Date
JP2002043354A true JP2002043354A (en) 2002-02-08

Family

ID=18722524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000229401A Pending JP2002043354A (en) 2000-07-28 2000-07-28 Flip chip mounting method

Country Status (1)

Country Link
JP (1) JP2002043354A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147847A (en) * 2004-11-19 2006-06-08 Pioneer Electronic Corp Bump forming method and structure for bonding
JP2006190777A (en) * 2005-01-05 2006-07-20 Pioneer Electronic Corp Bump forming method
US9685478B2 (en) 2012-11-16 2017-06-20 Sharp Kabushiki Kaisha Flip-chip bonding method and solid-state image pickup device manufacturing method characterized in including flip-chip bonding method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147847A (en) * 2004-11-19 2006-06-08 Pioneer Electronic Corp Bump forming method and structure for bonding
JP2006190777A (en) * 2005-01-05 2006-07-20 Pioneer Electronic Corp Bump forming method
US9685478B2 (en) 2012-11-16 2017-06-20 Sharp Kabushiki Kaisha Flip-chip bonding method and solid-state image pickup device manufacturing method characterized in including flip-chip bonding method

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