JP3202193B2 - Wire bonding method - Google Patents

Wire bonding method

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Publication number
JP3202193B2
JP3202193B2 JP15351498A JP15351498A JP3202193B2 JP 3202193 B2 JP3202193 B2 JP 3202193B2 JP 15351498 A JP15351498 A JP 15351498A JP 15351498 A JP15351498 A JP 15351498A JP 3202193 B2 JP3202193 B2 JP 3202193B2
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JP
Japan
Prior art keywords
wire
bonding
bump
semiconductor chip
capillary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15351498A
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Japanese (ja)
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JPH11307571A (en
Inventor
祐介 後藤
Original Assignee
シャープタカヤ電子工業株式会社
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Priority to JP15351498A priority Critical patent/JP3202193B2/en
Publication of JPH11307571A publication Critical patent/JPH11307571A/en
Application granted granted Critical
Publication of JP3202193B2 publication Critical patent/JP3202193B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置内のワイヤ
ボンディング構造及びワイヤボンディング方法に関するBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding structure in a semiconductor device and a wire bonding method.

【０００２】[0002]

【従来の技術】図７は従来の半導体装置のワイヤボンデ
ィング構造を示したものである。金属、樹脂、セラミッ
ク等でできたフレーム３の上に、接着剤を用いて半導体
チップ１を装着し、半導体チップ１上のボンディングパ
ッド２とフレーム３上の電極をワイヤ４によって接続し
ている。なお、ワイヤボンディングは、まず、ワイヤ４
の先端に溶融ボールを形成し、当該溶融ボールを半導体
チップ１上のボンディングパッド２に圧着して第１ボン
ド部５を形成し、続いてフレーム３上の電極にワイヤ４
を圧着して、第２ボンド部６を形成している。図８は図
７において、ワイヤ４の接続順序を変えて第１ボンド部
５をフレーム３側に第２ボンド部６を半導体チップ１上
に形成したものである。一般に、半導体チップ１上のボ
ンディングパッド２は第１ボンド用に小さく形成されて
いるため、第２ボンド点として使うためにはボンディン
グパッド２上にバンプ７を形成する必要があり、通常以
下の手順が用いられている。 （１）ワイヤボンダ等のボンディング装置を利用して半
導体チップ１上のボンディングパッド２にワイヤ４の先
端に形成した溶融ボールをキャピラリー８で圧着する。
（図９） （２）わずかにキャピラリー８上昇後、ワイヤクランパ
９でワイヤ４をクランプし、さらに上昇する。（図１
０） （３）溶融ボールは電気スパークによって形成されるた
め、一般にボール付近のワイヤは再結晶化されて、もろ
い状態にあり、ワイヤ４は溶融ボールの近くでひきちぎ
られて、ワイヤバンプ１２が形成される。（図１１） （４）表面が平坦なスタンピングツール１０で、ワイヤ
バンブ１２を加圧し、表面が平坦で均一な高さのバンプ
７を形成する。（図１２） （５）フレーム３の電極上に第１ボンディング、バンプ
７上に第２ボンディングの順序でワイヤ４を接続する。
（図１３）2. Description of the Related Art FIG. 7 shows a wire bonding structure of a conventional semiconductor device. A semiconductor chip 1 is mounted on a frame 3 made of metal, resin, ceramic, or the like using an adhesive, and a bonding pad 2 on the semiconductor chip 1 is connected to an electrode on the frame 3 by a wire 4. In addition, first, wire bonding
A molten ball is formed at the tip of the semiconductor chip 1 and the molten ball is pressed against the bonding pad 2 on the semiconductor chip 1 to form a first bond portion 5.
Is pressed to form the second bond portion 6. FIG. 8 is different from FIG. 7 in that the connection sequence of the wires 4 is changed to form the first bond portion 5 on the frame 3 side and the second bond portion 6 on the semiconductor chip 1. Generally, since the bonding pad 2 on the semiconductor chip 1 is formed small for the first bond, it is necessary to form the bump 7 on the bonding pad 2 in order to use it as the second bond point. Is used. (1) Using a bonding device such as a wire bonder, a molten ball formed at the tip of a wire 4 is pressed against a bonding pad 2 on a semiconductor chip 1 with a capillary 8.
(FIG. 9) (2) After the capillary 8 is slightly raised, the wire 4 is clamped by the wire clamper 9 and further raised. (Figure 1
0) (3) Since the molten ball is formed by electric spark, the wire near the ball is generally recrystallized and in a brittle state, and the wire 4 is torn off near the molten ball to form a wire bump 12. Is done. (FIG. 11) (4) The wire bump 12 is pressed by the stamping tool 10 having a flat surface to form the bump 7 having a flat surface and a uniform height. (FIG. 12) (5) The wires 4 are connected in the order of the first bonding on the electrodes of the frame 3 and the second bonding on the bumps 7.
(FIG. 13)

【０００３】[0003]

【発明が解決しようとする課題】従来技術における課題
を以下に列挙する。 （１）半導体チップ上に第１ボンド部を形成し、フレー
ム上に第２ボンド部を形成する図７のワイヤボンド構造
は、第１ボンド部付近でのワイヤの傾斜が垂直に近いた
め、ワイヤループの高さを低くすることが困難であり、
半導体装置を薄くできない。 （２）図１４は半導体チップを２つ重ねた複合半導体装
置に図７と同様のワイヤボンド構造を用いた例である
が、この場合、第２ボンディング部付近でのワイヤ間の
距離が短く、後続の工程において、ワイヤ間ショートの
恐れがある。 （３）図９から図１３で示した方法によるワイヤボンド
方式では、以下の問題がある。 （ａ）ワイヤバンプ形成用、スタンピング用、ワイヤボ
ンディング用にワイヤボンダが３台必要になるため、作
業効率の低下だけでなく、各ワイヤボンダ間の特性のば
らつきのため、ボンディング位置が微妙にずれる恐れが
ある。 （ｂ）ワイヤのひきちぎりにより発生するテール残り１
１の長さを正確にコントロールすることは困難であり、
長い場合には、次工程のスタンピングにより、隣接する
バンプと接触する恐れがある。そのため、テール残りを
小さくするために高硬度金線を用いるなどの方法が用い
られるが、その場合バンプ用の金線とワイヤボンディン
グ用の金線を変更する必要がある。 （ｃ）スタンピングツールに異物付着が発生しやすく、
スタンピング後のバンプ形状が不安定になる。 （ｄ）第２ボンディング部では通常、ワイヤの自重によ
り、余分に繰出されたワイヤに対して第１ボンディング
部方法に引き戻されるプルバック現象が発生するが、平
面バンプ上へのボンディングの場合、プルバックの方向
が下方に向かい、図１５に示したようにワイヤがチップ
表面に接触する恐れがある。Problems to be solved by the prior art are enumerated below. (1) The first bond portion is formed on the semiconductor chip, and the second bond portion is formed on the frame. In the wire bond structure of FIG. 7, since the inclination of the wire near the first bond portion is almost vertical, the wire It is difficult to lower the height of the loop,
Semiconductor devices cannot be made thin. (2) FIG. 14 shows an example in which a wire bond structure similar to that of FIG. 7 is used in a composite semiconductor device in which two semiconductor chips are stacked. In this case, the distance between wires near the second bonding portion is short. In a subsequent process, there is a risk of short-circuit between wires. (3) The wire bonding method according to the method shown in FIGS. 9 to 13 has the following problems. (A) Since three wire bonders are required for wire bump formation, stamping, and wire bonding, not only the work efficiency is reduced, but also the bonding position may be slightly shifted due to variations in characteristics between the wire bonders. . (B) Tail remaining 1 generated by breaking the wire
It is difficult to control the length of one precisely,
If the length is long, there is a possibility that adjacent bumps may be contacted by stamping in the next step. Therefore, a method such as using a high-hardness gold wire is used to reduce the tail residue. In this case, it is necessary to change the gold wire for the bump and the gold wire for the wire bonding. (C) Foreign matter easily adheres to the stamping tool,
The bump shape after stamping becomes unstable. (D) In the second bonding portion, a pull-back phenomenon occurs in which the extra wire is pulled back to the first bonding portion method due to the weight of the wire. However, in the case of bonding on a planar bump, the pull-back phenomenon occurs. The direction is directed downward, and the wires may come into contact with the chip surface as shown in FIG.

【０００４】[0004]

【課題を解決するための手段】本発明はかかる課題を解
決するために発明されたものである。基本的には、フレ
ーム側に第１ボンディング部、半導体チップ側に第２ボ
ンディング部を有するワイヤボンディング構造に関し
て、新たな構造及び新たな方式を提供するものである。
図１に本発明に係るワイヤボンディング構造を示す。以
下、図を用いて本発明のワイヤボンディング法を詳述す
る。 （１）ワイヤボンディング装置等の従来方式により、半
導体チップ上のボンディングパッド２にワイヤ先端の溶
融ボールをキャピラリー８により圧着したのち、ワイヤ
をひきちぎり、テール残り１１を有するワイヤバンプ１
２を形成する。（図２） （２）フレーム３上の電極に第１ボンド部５を形成す
る。（図３） （３）ワイヤバンプ１２上に第２ボンディング部６を形
成するが、その際、キャピラリー８の貫通穴にテール残
り１１を挿入した状態でワイヤ４を圧着する。なお、キ
ャピラリー８の貫通穴の内径はワイヤ径の２倍程度に選
定している。（図４）SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. Basically, a new structure and a new method are provided for a wire bonding structure having a first bonding portion on the frame side and a second bonding portion on the semiconductor chip side.
FIG. 1 shows a wire bonding structure according to the present invention. Hereinafter, the wire bonding method of the present invention will be described in detail with reference to the drawings. (1) By a conventional method such as a wire bonding apparatus, a molten ball at the tip of a wire is press-bonded to a bonding pad 2 on a semiconductor chip by a capillary 8, and then the wire is cut off and a wire bump 1 having a tail residue 11 is formed.
Form 2 (FIG. 2) (2) The first bond portions 5 are formed on the electrodes on the frame 3. (FIG. 3) (3) The second bonding portion 6 is formed on the wire bump 12. At this time, the wire 4 is crimped with the tail remaining 11 inserted into the through hole of the capillary 8. The inner diameter of the through hole of the capillary 8 is selected to be about twice the wire diameter. (FIG. 4)

【０００５】[0005]

【発明の実施の形態】図５、図６は第２ボンディング部
の形成法について示したものである。図５に示すように
キャピラリー８とテール残り１１の中心にオフセット１
５を持たせてキャピラリー８を下降させたのち、図６の
状態でキャピラリー８をわずかにワイヤ４をひっぱる側
に移動させることにより、安定した第２ボンディング部
の形成が確認されている。FIG. 5 and FIG. 6 show a method of forming a second bonding portion. As shown in FIG. 5, offset 1 is set at the center of capillary 8 and tail rest 11.
5, the capillary 8 is lowered, and then the capillary 8 is slightly moved to the side where the wire 4 is pulled in the state of FIG. 6, thereby confirming the stable formation of the second bonding portion.

【０００６】[0006]

【発明の効果】以上述べてきた本発明の効果を以下に列
挙する。 （１）ワイヤループ高さを低くできる。 （２）テール残りの長さのばらつきを気にせずにワイヤ
バンプを形成することができるため、ワイヤバンプ用金
線とワイヤボンディング用金線を同一にすることがで
き、半導体チップ上のボンディングパッドへのワイヤバ
ンプの形成及びフレームとワイヤバンプ間のワイヤボン
ディング工程が同一のワイヤボンディング装置によって
連続に出来る。したがって、従来方式に比較して作業効
率が高く、かつ、精度の高いワイヤボンディングが可能
である。 （３）ワイヤひきちぎりにより発生するテール残りの品
質上への影響がない。 （４）第２ボンディング部で発生するワイヤのプルバッ
クに関して、本発明の方式では第２ボンディング部が図
１６に示されるように、つば部１３、傾斜部１４になる
ため、プルバックの方向が斜め上方になり、ワイヤとチ
ップの接触がない。The effects of the present invention described above are listed below. (1) The wire loop height can be reduced. (2) Since the wire bumps can be formed without concern for variations in the remaining length of the tail, the gold wires for wire bumps and the gold wires for wire bonding can be made the same, and the bonding pads to the bonding pads on the semiconductor chip can be formed. The formation of the wire bump and the wire bonding process between the frame and the wire bump can be continuously performed by the same wire bonding apparatus. Therefore, it is possible to perform wire bonding with higher working efficiency and higher precision than the conventional method. (3) There is no effect on the quality of the tail residue generated by breaking the wire. (4) Regarding pullback of the wire generated in the second bonding portion, in the method of the present invention, as shown in FIG. 16, the second bonding portion becomes the collar portion 13 and the inclined portion 14, so that the pullback direction is obliquely upward. And there is no contact between the wire and the chip.

【０００７】[0007]

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係るワイヤボンディング構造を示す図
である。FIG. 1 is a diagram showing a wire bonding structure according to the present invention.

【図２】本発明に係るワイヤボンディング方法の手順を
説明する図である。FIG. 2 is a diagram illustrating a procedure of a wire bonding method according to the present invention.

【図３】本発明に係るワイヤボンディング方法の手順を
説明する図である。FIG. 3 is a diagram illustrating a procedure of a wire bonding method according to the present invention.

【図４】本発明に係るワイヤボンディング方法の手順を
説明する図である。FIG. 4 is a diagram illustrating a procedure of a wire bonding method according to the present invention.

【図５】本発明に係るワイヤボンディング方法におい
て、第２ボンディング部の説明をする図である。FIG. 5 is a diagram illustrating a second bonding portion in the wire bonding method according to the present invention.

【図６】本発明に係るワイヤボンディング方法におい
て、第２ボンディング部の説明をする図である。FIG. 6 is a diagram illustrating a second bonding portion in the wire bonding method according to the present invention.

【図７】従来の半導体装置のワイヤボンディング構造を
示す図である。FIG. 7 is a diagram illustrating a wire bonding structure of a conventional semiconductor device.

【図８】従来の半導体装置のワイヤボンディング構造を
示す図である。FIG. 8 is a diagram showing a wire bonding structure of a conventional semiconductor device.

【図９】従来の半導体装置のワイヤボンディング方法の
手順を説明する図である。FIG. 9 is a diagram illustrating a procedure of a conventional wire bonding method for a semiconductor device.

【図１０】従来の半導体装置のワイヤボンディング方法
の手順を説明する図である。FIG. 10 is a diagram illustrating a procedure of a conventional wire bonding method for a semiconductor device.

【図１１】従来の半導体装置のワイヤボンディング方法
の手順を説明する図である。FIG. 11 is a diagram illustrating a procedure of a conventional wire bonding method for a semiconductor device.

【図１２】従来の半導体装置のワイヤボンディング方法
の手順を説明する図である。FIG. 12 is a diagram illustrating a procedure of a conventional wire bonding method for a semiconductor device.

【図１３】従来の半導体装置のワイヤボンディング方法
の手順を説明する図である。FIG. 13 is a diagram illustrating a procedure of a conventional wire bonding method for a semiconductor device.

【図１４】従来の半導体装置の他の構造を示す図であ
る。FIG. 14 is a diagram showing another structure of a conventional semiconductor device.

【図１５】従来のワイヤボンディング方法の課題を示す
図である。FIG. 15 is a diagram showing a problem of a conventional wire bonding method.

【図１６】本発明の効果を説明した図である。FIG. 16 is a diagram illustrating an effect of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ ボンディングパッド
３ フレーム ４ ワイヤ ５ 第１ボンド部
６ 第２ボンド部 ７ バンプ ８ キャピラリー
９ ワイヤクランパ １０ スタンピングツール １１ テール残り
１２ ワイヤバンプ １３ つば部 １４ 傾斜部
１５ オフセット1 semiconductor chip 2 bonding pad
3 Frame 4 Wire 5 First bond
6 Second bond part 7 Bump 8 Capillary
9 Wire clamper 10 Stamping tool 11 Tail remaining
12 Wire bump 13 Collar 14 Slope
15 Offset

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップ上のボンディングパッドとA bonding pad on the semiconductor chip;
当該半導体チップを装着するフレーム上の電極間を接続Connect the electrodes on the frame on which the semiconductor chip is mounted
するワイヤボンディング方法において（１）半導体チッ(1) Semiconductor chip
プ上のボンディングパッドにワイヤの先端に形成した溶To the bonding pad on the tip of the wire.
融ボールを圧着したのち、ワイヤをひきちぎってワイヤAfter crimping the molten ball, cut the wire
バンプを形成する。（２）フレーム上の電極にワイヤのForm bumps. (2) Wire the electrode on the frame
先端に形成した溶融ボールを圧着する第１ボンディングFirst bonding to press the molten ball formed at the tip
を行う。（３）当該ワイヤをキャピラリーによって、前I do. (3) The wire is moved forward by a capillary.
記ワイヤバンプに圧着する際、ひきちぎりによってワイWhen crimping to the wire bump,
ヤバンプ上に形成されたテール残りをキャピラリーの貫The remaining tail formed on the bump is passed through the capillary.
通穴の中心からわずかに第１ボンディング方向にずらしSlightly shifted from the center of the through hole in the first bonding direction
て貫通穴に導くと同時に、キャピラリーを第１ボンディAt the same time as the capillary through the first bondy
ングにより一方を圧着されたワイヤを引っ張る側に移動To the side pulling the crimped wire
させる。以上を特徴とするワイヤボンディング方法。Let it. A wire bonding method characterized by the above.
JP15351498A 1998-04-24 1998-04-24 Wire bonding method Expired - Fee Related JP3202193B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15351498A JP3202193B2 (en) 1998-04-24 1998-04-24 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15351498A JP3202193B2 (en) 1998-04-24 1998-04-24 Wire bonding method

Publications (2)

Publication Number Publication Date
JPH11307571A JPH11307571A (en) 1999-11-05
JP3202193B2 true JP3202193B2 (en) 2001-08-27

Family

ID=15564211

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3202193B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4219781B2 (en) 2003-10-03 2009-02-04 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
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Also Published As

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JPH11307571A (en) 1999-11-05

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