JP2002015596A - Semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test device which can test plural DUT simultaneously measured in a shorter time. SOLUTION: This semiconductor is provided with an individual test pattern generating means for generating individual test patterns of the prescribed number of tester channels and provided individually for each DUT, an individual test pattern interrupting means for interrupting in the prescribed test channel of a common test pattern continuously generated and supplying individual test pattern to each DUT, and an interrupting timing generating means for interrupting individual test pattern in the common test pattern continuously generated with the prescribed timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus capable of testing a device under test (DUT) in a shorter time. In particular, in a test mode in which a large number of DUTs are measured at the same time, and for a test mode in which the DUT is determined to be good or bad in units of memory blocks, such as a flash memory, the test can be performed in a shorter time. It relates to a possible semiconductor test device.

[0002]

2. Description of the Related Art As is well known, in a flash memory,
Internally, programming (writing) can be performed in units of a large number of memory blocks. This flash memory has an internal control system in which a command of a plurality of bytes is first written, and then writing / reading can be performed in units of memory blocks or pages. Further, the flash memory is characterized in that it can be shipped as a non-defective product even if there are defective memory blocks of a specified number or less. Although it depends on the product specifications, for example, even if a defect of up to 3 to 5% exists in the memory block, it can be shipped as a good product.

On the other hand, a semiconductor test apparatus has a configuration for simultaneously measuring a plurality of DUTs, for example, 64 DUTs, to improve the throughput of a device test. By the way, I
Due to a yield in manufacturing C, a defective device exists with a certain probability. For this reason, from the viewpoint of improving the throughput, a semiconductor test apparatus generally performs a test of a device in two stages as a test procedure. That is, the first
In the stage, a simple operation confirmation test is performed in a short time by a pretest, and in the subsequent second stage test, a full-scale detailed test such as a functional test, a characteristic test, and a category classification is performed. Usually, the test time in the second stage takes several tens of times or more as long as the test time in the first stage. According to this test procedure, if a failure is detected in the first stage pretest,
The UT can substantially improve the throughput of the device test as a result of eliminating unnecessary second-stage test time.

[0004] Even when the DUT is a flash memory, the test is performed in two stages. In FIG. 2, it is assumed that, among the block numbers 1 to 1024 of the memory of each DUT, the block number of the hatched portion is a bad block. In the first stage of the pretest, a simple operation confirmation test is performed for each block of the memory, and as shown in FIG. 1, the defect information for each block is stored in a dedicated defective area recognition memory (BBM).
Is stored in Here, a BBM (Bad Block Memory) has a storage capacity corresponding to the number of blocks of the DUT.
This is a 1-bit-wide memory for storing a failure flag, and is used to accumulate and store fail information in block address area units.

In the test time of the second stage, the throughput can be improved if the test can be performed by jumping over (skipping) the block number in which the defect information exists. However, this skip operation can be easily performed when one DUT is used. However, when a plurality of DUTs are measured at the same time, all the DUTs do not always have the same block number, and therefore, substantially no defect occurs. Can not be skipped and executed. Usually, the probability that all DUTs have the same block number is low. Usually, defects occur discretely at random block number positions. Therefore, at most block number positions, at least one DUT is a normal block. There are many cases. Therefore, in the case of simultaneous measurement, some D
Even if there is a defect in the UT, the block number cannot be skipped. This is because the address pattern individually supplied from the ALPG to each DUT is generated by branching and supplying the same pattern. That is, the plural D
As a result of not providing a means for supplying an individual address pattern to the UT, there is a disadvantage that the device test throughput cannot be substantially improved.

The above will be described more specifically. Here, it is assumed that 64 flash memories, which are DUTs, are measured simultaneously, and as shown in FIG. 2, it is assumed that the block numbers of the DUT are from 1 to 1024, which are obtained in the first stage pretest. The location of the bad block
It is assumed that it occurs randomly at different block number positions for each DUT. In this case, in the second stage test execution, when 64 DUTs are sequentially tested in ascending order from block number 1 by simultaneous measurement, the DUTs corresponding to the bad blocks are, as shown in FIG. Based on the BBM defect flag obtained individually,
The UT outputs control signals (/ CE, / WE, //
RE, etc.) are controlled to be in an invalid state, and the write test and the read test are not performed.

[0007]

As described above, in the prior art, when a plurality of DUTs are measured at the same time, the throughput is substantially improved even if a bad block exists. Can not. In this respect, it is not preferable, and there is a practical difficulty. Accordingly, an object of the present invention is to provide a DUT for simultaneously measuring a plurality of DUTs.
To provide a semiconductor test apparatus capable of performing a test in a shorter time.

[0008]

First, in order to solve the above-mentioned problems, a common test pattern used in common is generated from a pattern generator (for example, ALPG) and is simultaneously transmitted to a predetermined plurality of devices under test. In a semiconductor test apparatus for supplying and measuring a plurality of DUTs at the same time, the semiconductor test apparatus includes an individual test pattern generating means provided individually for each DUT for generating an individual test pattern of a predetermined number of tester channels, and the above-described method for continuously generating An individual test pattern interrupting means which interrupts a predetermined tester channel of the common test pattern and supplies the individual test pattern to each DUT is provided for each DUT. Interrupt timing generation means for interrupting the individual test pattern at the timing of A semiconductor test apparatus, wherein a part of the test pattern that allows the test carried out by interrupting the respective DUT individual test pattern. According to the above invention, it is possible to realize a semiconductor test apparatus capable of performing a test of a DUT for simultaneously measuring a plurality of devices, for example, a test of a flash memory in a shorter time.

Further, as one mode of the above-mentioned individual test pattern generation means, based on the previously acquired failure information of each functional circuit unit for each DUT, a DUT corresponding to the acquired failure information is obtained. Each DUT is so designed that the test execution of the functional circuit is skipped in a predetermined manner and the test execution is continuously performed without a non-operation period in which the test execution is not performed.
The semiconductor test apparatus described above is characterized in that a predetermined test pattern is individually generated.

[0010] Further, the DUT test is performed by dividing the test into two stages of test embodiments.
When the failure information of the functional circuit unit of T is acquired by the semiconductor test apparatus or another semiconductor test apparatus, and the test is performed in the second stage of the test based on the failure information of each DUT acquired in the above. The individual test pattern generating means is applied to the test execution in the second stage, the test execution of the functional circuit of the DUT corresponding to the obtained defect information is skipped, and the non-operation period during which the test execution is not performed Each DU is to be tested continuously without any
The above-described semiconductor test apparatus is characterized in that a predetermined test pattern is generated for each T.

When the functional circuit unit of the DUT is a memory block unit in a memory device and the defect information is defect information indicating a defect in the memory block unit obtained in the first-stage test, the memory block unit Information storing means (for example, B
BM), wherein the individual test pattern generating means are individually provided corresponding to the number of DUTs to be simultaneously measured, and sequentially read the defect information from the defect information storage means in a predetermined manner to skip defective memory blocks. The semiconductor test apparatus described above is characterized in that a predetermined test pattern for each DUT is generated, which becomes a normal memory block to be tested next.

Further, one mode of the above-mentioned defect information storage means is as follows.
Upon receiving the fail signal FL1 which is individually provided corresponding to the number of DUTs to be measured at the same time and is stored in the memory block unit and which has been determined in the logical comparator SC in a predetermined pass / fail manner, to the address position in the memory block unit supplied from the ALPG And a defective area recognition memory BBM that accumulates and stores defective block information BBM_FL.

One embodiment of the above-mentioned individual test pattern generating means is provided individually corresponding to the number of DUTs to be simultaneously measured, and is provided with bad block information BBM_ in memory block units.
A counting means (e.g., a block address signal (YBBM)) for generating a predetermined number of block address information (e.g., a block address signal YBBM) so as to sequentially access a normal memory block by skipping a predetermined area; For example, BBM address pointer BBMA
P), and based on the bad block information BBM_FL read from the BBM, generates a block address signal YBBM counted by the counting means in a predetermined manner, and skips the defective block in a predetermined manner to become a normal memory block. The semiconductor test apparatus described above is characterized in that block address information is sequentially generated as individual test patterns.

Further, as one mode of the defect information acquired in the first stage test execution, the defect information acquired and applied in the semiconductor test apparatus for performing the second stage test is described below.
Alternatively, there is the above-described semiconductor test apparatus, which is defect information applied based on the above-described defect information obtained by another semiconductor test apparatus (for example, a wafer test apparatus in a previous process).

One aspect of the individual test pattern interrupt means is a selection output means (for example, a multiplexer MPX1) which receives two test patterns of a predetermined data width and selects and outputs any one of the data. The selection output means is provided immediately before the waveform shaper FC, and the selection output means is provided for a predetermined number of tester channels to be interrupted for supplying a test pattern to the DUT, and a common test pattern generated from the ALPG and an individual test pattern. The above-mentioned semiconductor test apparatus is characterized in that, upon receiving an individual test pattern generated from a test pattern generating means, at a predetermined interrupt timing, the individual test pattern is selectively output and supplied to the FC.

As one mode of the tester channel to be interrupted, when the DUT is a flash memory whose pass / fail inspection is performed in memory block units, the tester channel for supplying a test pattern designating a block number of the DUT is targeted. The semiconductor test apparatus described above is characterized in that the semiconductor test apparatus is interrupted as follows.

Further, one mode of the above-mentioned interrupt timing generating means generates a control command FLCMD at a predetermined timing based on the description of the pattern program, and transmits the control command FLCMD to, for example, the mode data generating section 20.
The semiconductor test apparatus described above is characterized in that when 0 is received, the selection test means (for example, the multiplexer MPX1) is controlled to interrupt the individual test pattern with the common test pattern.

Further, there is the above-mentioned semiconductor test apparatus, wherein the above-mentioned DUT is a device (for example, a flash memory) including at least a memory in a block unit. Further, there is the above-mentioned semiconductor test apparatus, wherein the above-mentioned DUT is a memory device having at least a block-unit memory therein, or a system LSI incorporating the above-mentioned memory device.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Further, the scope of the claims is not limited by the following description of the embodiments, and the elements and connection relationships described in the embodiments are not necessarily essential to the solving means.
Further, the description of the elements and connection relations described in the embodiments is an example, and is not limited to the description.

FIGS. 3, 4 and 5 illustrate the present invention.
And FIG. 6 will be described below. It should be noted that since the semiconductor test apparatus is well-known and well-known in the art, other signals and components, and the detailed description thereof will be omitted except for the main part according to the present application.

First, the main configuration of the semiconductor test apparatus according to the present invention shown in FIG. 3 will be described. The components are ALPG and PDS
, Multiplexer MPX1, FC, PTG, S
C, AFM, BBM, BBMAP, and mode data generation unit 200.

ALPG (Algorithmic Pattern Generato
r) is for generating a desired address pattern (address signal), a write data pattern, and the like by a complicated calculation having an internal calculation function, and the / CE, / W of the IC pin of the DUT.
E, / RE, ALE, CLE and other control signals that can be arbitrarily generated. Y address signal Y which is noticed in this application
D is supplied to PDS, AFM and BBMAP. Here, CLE (command, latch,
Enable) is an IC pin used for the flash memory, and is a dedicated IC pin for writing and setting a command string of a plurality of continuous bytes (1 to 4 bytes) therein. As an example of the command string, the first command, the first
The address, the second address, and the third address are supplied in this order. At this time, the upper address bits are used as the block number. For example, when 10 bits are used to specify the block number, the upper two bits of the third address and the second address are applied.

PDS (Programmable Data Selector)
Can receive a plurality of pattern data from the ALPG and arbitrarily select and output desired device data or expected value data to be supplied to the SC. Here, it is assumed that the I / O pins for writing / reading the DUT are 8 bits wide,
Also, only an 8-bit width test pattern PD1 for I / O pins supplied to the multiplexer MPX1 is shown, and the other is omitted.

The multiplexer MPX1 is a 2-input, 1-output 8-bit width multiplexer. This receives the 8-bit test pattern PD1 from the PDS, and receives the 8-bit block data BD from the mode data generator 200.
2 based on the selection signal SL4 from the mode data generation unit 200, the selected selection pattern MP
X1d is output to FC.

The FC (Format Control) receives the selection pattern MPX1d and receives an NRZ, RZ, EXOR (S
The waveform data shaped and converted into a predetermined waveform mode such as BC) is supplied to the PTG.

The PTG (Per Pin Timing Generator)
Timing set TS received from ALPG (not shown)
, A predetermined pulse waveform defining the leading edge and trailing edge of the output pulse for each tester channel is output to the I / O pin of the DUT via the driver DR. Note that a driver pin dedicated to an address and a driver pin for generating ALE, / CE, / RE, etc. are separately provided separately.

SC is a logic comparator, which converts a response signal from each DUT into logic data by a comparator CP and receives it, latches it at a predetermined timing of a strobe signal STB, and generates this from an ALPG. The pass / fail judgment is performed based on the expected value data (not shown), and the fail signal FL1 determined to be defective is supplied to the AFM and the BBM.

The AFM (Address Failure Memory) has the same memory capacity as the address space of each DUT, receives fail information for each memory cell of each DUT as the above-mentioned fail signal FL1, and accumulates the information at the corresponding address position of the AFM. It is a storage device for storing.

BBMAP is a block address signal YBB
It is an address pointer for generating M and for generating an address for the BBM. This is for each DUT
A block address signal YBBM for each DUT is generated in synchronization with the reference clock REFCLK. As a specific example, it is realized by a 10-bit UP counter that can be preset. The preset input terminal Di of BBMAP receives a 10-bit Y address signal YD of Y address start address data (usually starting from "0") sent from the ALPG, and receives a load signal LD7 from the mode data generator 200. When the data is received at the load input terminal ld, an initial value is preset in a count register which is itself. Then, the mode data generation unit 200
Is incremented each time an increment signal INC8 is received. When receiving the clear signal CLR9 from the mode data generator 200, the value of the count register is cleared to “0”. From the output end of BBMAP, a 10-bit count value is output from the block address signal Y.
The BBM is supplied to the BBM and the mode data generator 200 as a BBM.

The BBM is a 1-bit width storage device for accumulating and storing fail information in block address area units. For example, in the case of 1024 blocks, the BBM includes a memory having a 1 KW × 1 bit width configuration and an accumulation storage circuit. BB above
The block address signal YBBM from the MAP is received at the address input terminal, and the fail signal FL1 from the SC is supplied to D.
Upon receipt at the i input terminal, block failure information is accumulated and stored at the corresponding address position. As a result, it is stored as a defective flag in block units. Also,
The bad block information of the block number accumulated and stored is B
It is supplied to the mode data generation unit 200 as a BM_FL signal.

The mode data generator 200 is configured to execute the BBM
The operation of the AP is controlled in a predetermined manner, and the multiplexer MPX
1 is a control unit for controlling the operation of No. 1 in a predetermined manner.

Next, with respect to an example of the internal configuration of the main part of the mode data generating section 200, an example of the internal configuration of FIG. 4, a timing chart for explaining the operation of FIG. 5, and an individual block address signal YBBM for the DUT of FIG. This will be described with reference to an explanatory diagram for supplying. Note that the timing chart of FIG. 5 shows an operation for the DUT 1 in FIG. It is assumed that the DUT 1 has a bad block in block numbers 2, 5, and 6. In FIG. 3,
The mask operation for masking the logical comparison with the SC is simultaneously controlled based on the fail information of the AFM and the BBM, but the circuit elements related to the generation of the mask signal MASK6 are omitted.

The main components of the mode data generator 200 are a multiplexer MPX3 and a latch register RG5.
, Flip-flop FF6, and logical OR means 22
And a logical AND means 14. Externally received signals include a PG_START signal indicating the start of pattern generation, a TEST_START signal indicating the start of a test, an S_BBM signal indicating an operation mode to which the present invention is applied, and an AL signal.
A control command FLCMD signal that can be generated at an arbitrary timing based on a PG pattern program, a test cycle (test rate) of a device test, for example, a Period_SNC signal indicating a timing every 100 nanoseconds, and a reference clock REFCLK of, for example, 100 MHz. is there. In the case of the above numerical example, generation of the Period_SNC signal is one pulse for every 10 pulses of REFCLK. The operation of each circuit element is basically REFCL
It operates in synchronization with K. Also, a flip-flop for a pipeline for simply retiming with REFCLK is omitted.

First, the output signal of the multiplexer MPX3 is applied to the load signal LD7 supplied to the BBMAP. PG_ST when S_BBM signal is asserted
An ART signal is supplied. When the S_BBM signal is negated, an "H" signal is always supplied. According to this, when the S_BBM signal is negated, that is, in the general operation mode, the Y address signal YD is always loaded into the BBMAP, and the Y address signal YD from the ALPG is controlled to be supplied to the BBM as it is. As a result, an operation compatible with the related art can be performed. On the other hand, when the present invention is applied, that is, when the S_BBM signal is asserted, PG
When the _START signal is generated, the Y address signal YD as an initial value is loaded into BBMAP (FIG. 5D
reference). Secondly, an increment signal INC8 to be supplied to the BBMAP includes a control command FLCMD signal generated from the ALPG based on a predetermined pattern program,
BB output from the BBM via the logical AND means 14
A signal resulting from the logical OR of the M_FL signal with the logical OR means 22 is applied as an increment signal INC8. The control command FLCMD signal is a start-up pulse for proceeding to the next block number having no failure. According to this, when the control command FLCMD signal is generated when the next block number is to be designated,
The count value of BBMAP is incremented by +1 (FIG. 5F,
J, L). The block address signal Y which is the output
The BBM is supplied to the BBM. As a result, the block fail information BBL_FL of the next block address is read from the BBM. At this time, if the read block fail information BBL_FL is a bad block “1”, this signal is supplied again to the BBMAP as an increment signal INC8, and the count value is further counted up by +1 at the next REFCLK, and Block numbers are skipped (see FIGS. 5G, M, N). As a result, the final value of the block address signal YBBM becomes BBM_F
Stop at a block address position where L is not a bad block. Therefore, even if there is a failure with consecutive block numbers, it is possible to continuously skip to the position immediately after that and stop (see FIG. 5N).

Third, the TEST_START signal is applied to the clear signal CLR9 supplied to the BBMAP,
The initial value of BBMAP is cleared to "0".

Fourth, the selection control signal SL4 to be supplied to the multiplexer MPX1 has a flip-flop FF6, sets the output state of the selection control signal SL4 to an asserted state by a control command FLCMD signal, and sets a test cycle. The output state of the selection control signal SL4 is reset by the Period_SNC signal to be in a negated state. However, in this figure, although the principle block is shown as the RS flip-flop, the REFC
This is a circuit configuration of a flip-flop that operates in synchronization with LK and operates with priority on the set side.

Fifth, the 8-bit block data BD2 supplied to the multiplexer MPX1 is provided with a latch register RG5, receives a 10-bit block address signal YBBM output from BBMAP, and receives a control command FLCMD signal. Latched and output as a block address output signal YBBM2 (see FIGS. 5E, 5H, and 5K). However, in the configuration example of FIG. 4, the upper 8 bits of the 10 bits are supplied to the multiplexer MPX1 as the block data BD2. The block number is 10
Since it is assumed to be 24, it should normally receive 10 bits of the block address output signal YBBM2 and divide the block address output signal YBBM2 into 8-bit data and 2-bit data at a timing synchronized with the Period_SNC signal, which is a test cycle. Should be supplied to the multiplexer MPX1,
Here, for ease of explanation, a simple block diagram for supplying only the upper 8 bits is shown. Essentially, as described above, it is necessary to provide circuit means for supplying the data in two separate steps and generating the corresponding two selection control signals SL4.

According to the fourth and fifth descriptions, for each control command FLCMD signal, the block address signal YBBM generated by BBMAP is latched by the control command FLCMD signal, and the multiplexer MPX1 uses the test pattern as a test pattern to be applied to the DUT. Interrupts can be made at any time. As a result, a block number value unique to each DUT can be applied as a test pattern. This has the effect of acting as if the ALPG generates a unique block number for each DUT and supplies it to each DUT.

Referring to the timing chart of FIG.
It will be further described together. The timing chart of FIG. 5 shows an operation for the DUT 1 in FIG. D
Since UT1 is a defective block with block numbers 2, 5, and 6, the block address output signal YBBM2 to be supplied to the multiplexer MPX1 is "0", "2", "
3 ”,“ 6 ”,... According to the configuration of the present invention described above, the control command FLC is generated.
Since the block address output signal YBBM2 can be interrupted by the multiplexer MPX1 every time an MD occurs, the following operation is performed.

First, first, the block number is initialized to "0" by the PG_START signal and supplied to the BBM as the block address signal YBBM. The BBM_FL signal, which is bad block information read from the BBM, is normal. It is "0". Therefore, the value of YBBM is "#
0 "(see FIG. 5D). In the first control command FLCMD, the value of the YBBM is"# 0 ".
Is interrupted as a block number (see FIG. 5E). As a result, a normal block number (see FIG. 6A) is tested. Immediately after this, the value “# 1” (see FIG. 5F) of the block address signal YBBM counted by +1 is supplied to the BBM, and the BBM_FL signal to be read is “1” indicating a block failure. YBBM value “# 2” (FIG. 5
G). That is, the block number “2” is skipped.

Second, in the next control command FLCMD, the value "# 2" of the YBBM is interrupted as a block number (see FIG. 5H). As a result, one defective block number is skipped, and the next normal block number (see FIG. 6B) is tested. Immediately after this, the block address signal YBBM counted by +1 is added.
Is supplied to the BBM, and the BBM_FL signal to be read is normal "0". Therefore, the YBBM value "# 3" (see FIG. 5J) is maintained and stopped.

Third, in the next control command FLCMD, the value "# 3" of the YBBM is interrupted as a block number (see FIG. 5K). Immediately after this, the value “# 4” (see FIG. 5L) of the block address signal YBBM counted by +1 is supplied to the BBM, and the read BBM_
Since the FL signal is a block defect "1", the value of the block address signal YBBM further counted by +1 "# 5"
(See FIG. 5M), which is again supplied to the BBM,
The read BBM_FL signal indicates that the block is defective again.
Since the value is 1 ", the block address signal YBBM further counts up by 1 and the value becomes"# 6 "(see FIG. 5N), and the operation stops.Fourth, in the next control command FLCMD, the YBBM value"# 6 "is changed to" 1 ". As a result, the two defective block numbers are skipped, and the next normal block number (see FIG. 6D) is tested.

According to the configuration of the present invention described above, there is provided a means for generating a block address signal YBBM corresponding to the next normal block number by skipping a defective block number for each DUT and interrupting the generated block address signal as a test pattern. As a result, there is obtained an advantage that it is possible to eliminate the occurrence of dead time associated with a defective block as in the related art. Accordingly, an advantage that the throughput of the device test is improved can be obtained.

Note that the technical concept of the present invention is not limited to the specific configuration examples and connection examples of the above-described embodiment. Further, based on the technical idea of the present invention, the above-described embodiment may be appropriately modified and applied. For example, in the above-described embodiment, a specific example in which the BBMAP is counted up to skip the bad block has been described. However, as another configuration example, the same operation can be realized by the configuration example shown in FIG. That is, a jump memory 50 corresponding to the data width of the block address information is provided, and the data of the block numbers excluding the block number to be skipped based on the fail information of the BBM is stored in this order. For example, in the case of the DUT 1 shown in FIG.
0 ”is stored, and“ # 2 ”is stored in the address“ 1 ”.
“# 3” is stored in the address “2”, and the address “3” is stored.
Stores "# 6". On the other hand, BBMAP need only count +1 each time the control command FLCMD is generated. Then, the jump memory 50 may receive the YBBM output of the BBMAP as an address signal, read out the block number data 50s corresponding to the block number which is the content of the address, and interrupt the read out as the block address output signal YBBM2. Others are the same as above.

Further, in the above-described embodiment, a configuration example in which one byte is interrupted is shown in order to make a simplified block diagram.
The interruption in two times can be realized by a configuration corresponding to the above description. FIG. 8 shows an example in which the block address information and other lower address information, for example, need to be combined and supplied as a test pattern in the same cycle. This can be realized as an application configuration example of the multiplexer MPX1 described above, for example, when it is necessary to apply two bits to the DUT as block address information and six bits to the DUT as lower address information. A, B, receiving the selection control signal SL4,
This can be realized by generating two selection control signals 31 s and 32 s by using 32 and controlling the selection conditions of the corresponding multiplexers MPX1 a and MPX1 b. According to this, there is an advantage that the test pattern from the ALPG side and the block data BD2 from the mode data generation unit 200 side are received, and only the desired bits are interrupted and supplied to the DUT.

Further, in the application example of FIG. 8, an example in which a test pattern of one cycle is interrupted by one generation of the control command FLCMD is shown. The jump memory 50 is stored in the jump memory 50 for one desired generation of the control command FLCMD for a desired plurality of cycles.
May be read continuously and interrupted as a test pattern of the DUT. in this case,
In spite of the device test of the simultaneous measurement mode, an advantage is obtained that different test patterns generated individually for each DUT can be applied to the DUT to perform the test, instead of a plurality of ALPG continuous test patterns. That is, a DUT individual pattern generation function can be realized.

As the defect information stored in the defect area recognition memory BBM, it is normal to use the defect information stored by performing a first-stage pretest in the semiconductor test apparatus. Alternatively, an embodiment may be used in which defect information in block units obtained based on the result of a test performed by another semiconductor test apparatus is loaded into the BBM and used.

[0048]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, there is provided a means for generating a block address signal corresponding to the next normal block number by skipping a defective block number for each DUT and interrupting the generated block address signal as a test pattern. With such a configuration, there is obtained an advantage that it is possible to eliminate the occurrence of the dead time associated with the defective block as in the related art. Accordingly, a great advantage that the throughput of the device test is improved can be obtained. Also, multiple DUTs
Can maximize the device test throughput by simultaneous measurement. Therefore, the technical effect of the present invention is great,
Industrial economic effects are also great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a defective area recognition memory (B) in which each block number 1 to 1024 of a memory and defect information of each block unit are dedicated.
FIG. 6 is a diagram showing a state stored in the BM).

FIG. 2 shows block numbers 1 to 3 of memories in a plurality of DUTs.
FIG. 1024 is a diagram showing the occurrence of a random bad block in 1024.

FIG. 3 is a configuration diagram of a main part of a semiconductor test apparatus according to the present application.

FIG. 4 is an example of an internal configuration of a main part of a mode data generator according to the present invention.

FIG. 5 is a timing chart illustrating an operation of the present invention.

FIG. 6 is an explanatory diagram of the present invention for supplying an individual block address signal YBBM to each DUT.

FIG. 7 is another example of the configuration of the mode data generator of the present invention.

FIG. 8 is a configuration example of a multiplexer according to the present invention that can perform interrupt control for each bit.

[Explanation of symbols]

DUT1, DUT Device under test MPX1, MPX1a, MPX1b, MPX3 Multiplexer RG5 Latch register FF6 Flip flop 14 Logic AND means 22 Logical OR means 31, 32 Gate means 50 Jump memory 200 Mode data generator CP comparator ALPG pattern generator (Algorithmic Pattern Gen
AFM Address Failure Memory BBM Bad area recognition memory BBMAP BBM address pointer FC Waveform shaper (Format Control) PDS Programmable Data Selector PTG Per pin Timing Generator SC Logical comparator

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G01R 31/28 Q

Claims (11)

[Claims] 1. A semiconductor test apparatus for generating a common test pattern commonly used from a pattern generator and simultaneously supplying the common test pattern to a plurality of devices under test (DUT) to simultaneously measure a plurality of DUTs. An individual test pattern generating means for generating an individual test pattern corresponding to the number of tester channels, individually provided for each DUT, and interrupting a predetermined tester channel of the common test pattern which is continuously generated, and applying the individual test pattern to each DUT. An individual test pattern interrupting means provided for each DUT to be supplied, and an interrupt timing generating means for interrupting the continuously generated common test pattern with the individual test pattern at a predetermined timing. A semiconductor test apparatus characterized by the above-mentioned. 2. The DUT corresponding to the acquired defect information, based on the defect information of each functional circuit for each DUT acquired in advance.
2. The semiconductor test apparatus according to claim 1, wherein a predetermined test pattern is generated individually for each DUT so that the test execution of the functional circuit is skipped at a predetermined time and the test is continuously performed. 3. The test of the DUT is performed in two stages of test embodiments. In the first stage of the test, the failure information for each functional circuit of the DUT is obtained. When a test is performed based on the acquired defect information of each DUT, the individual test pattern generating means is applied to the second stage of the test, and the functional circuit of the DUT corresponding to the acquired defect information is provided. 2. The semiconductor test apparatus according to claim 1, wherein a predetermined test pattern is generated individually for each DUT so that the test is skipped and the test is continuously performed. 4. The function circuit unit of the DUT is a memory block unit in a memory device, and the failure information is the first
When the defect information indicating the defect in the memory block unit obtained by performing the test in stages is provided, a defect information storage unit for storing the defect information in the memory block unit is provided. Each of the DUTs is individually provided in accordance with the number of the DUTs. The defective information is sequentially read from the defective information storage means in a predetermined manner, and the defective memory block is skipped to become the next normal memory block to be tested. 4. The semiconductor test apparatus according to claim 3, wherein said predetermined test pattern is generated. 5. The defect information storage means comprises:
A fail signal, which is individually provided corresponding to the number of UTs and is stored in memory block units, and is determined in a logical comparator in a predetermined pass / fail manner, is sent to the address position in memory block units supplied from the ALPG as bad block information. 5. The semiconductor test apparatus according to claim 4, wherein the memory is a defective area recognition memory BBM for accumulating and storing. 6. The defective area recognition memory BBM, which is individually provided corresponding to the number of DUTs to be simultaneously measured and stores defective block information in memory block units, wherein the individual test pattern generating means skips a predetermined area. Counting means for generating predetermined counted block address information so as to sequentially access normal memory blocks; and generating a predetermined counted block address by the counting means based on bad block information read from the BBM. 2. The semiconductor test apparatus according to claim 1, wherein the block address information which becomes a normal memory block by skipping the defective block in a predetermined manner is sequentially generated as an individual test pattern. 7. The failure information obtained in the first stage test execution is obtained by the semiconductor test device that performs the second stage test execution and applied, or obtained by another semiconductor test device. 5. The semiconductor test apparatus according to claim 4, wherein the defect information is applied based on the defect information. 8. An individual test pattern interrupting means, comprising: a waveform shaper F which receives two test patterns of a predetermined data width and selects and outputs any one of the data.
C is provided immediately before C. The selection output means is provided for a predetermined number of tester channels to be interrupted for supplying a test pattern to the DUT,
Receiving a common test pattern generated from the ALPG and an individual test pattern generated from the individual test pattern generating means, selectively outputting the individual test pattern at a predetermined interrupt timing, and supplying the selected test pattern to the FC. 2. The semiconductor test apparatus according to claim 1, wherein: 9. The tester channel to be interrupted is a DUT
9. The semiconductor test apparatus according to claim 8, wherein when is a flash memory that is tested for pass / fail in memory block units, a tester channel for supplying a test pattern designating a block number of the DUT is interrupted. 10. The interrupt timing generating means generates a control command at a predetermined timing based on a description of a pattern program, and upon receiving the control command, causes the individual test pattern to be interrupted by a common test pattern. The semiconductor test apparatus according to claim 1, wherein: 11. The semiconductor test apparatus according to claim 1, wherein the DUT is a device including at least a memory in a block unit.