JPH11213695A - Semiconductor memory-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly perform high-speed classification by providing a counter block consisting of a word-line fail counter and a bit-line fail counter, and by analyzing a fail cell distribution shape according to only word-line and bit-line fail counter values being transferred from the counter block. SOLUTION: A memory repair analysis MRA 10 is constituted of a fail buffer memory FBM 11, a counter block 12, an I/O 14, and a control part 13 for controlling the MRA 10. All memories are classified for each predetermined block, and a fail shape from a large region to a small one is analyzed and classified for each block. A word-line fail counter and a bit-line fail counter are provided in each column and each row of the FBM 11, respectively, and a line fail bit analysis means 22 is provided at a work station 20, thus analyzing the distribution shape of a fail cell according to each fail counter value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory test apparatus for performing a failure analysis of a DUT (memory device under test) at high speed within a limited range.

[0002]

2. Description of the Related Art First, an outline of a semiconductor memory test apparatus will be described. FIG. 4 shows a basic configuration diagram of the semiconductor memory test apparatus. The test processor 31 controls the entire apparatus, and supplies a control signal to each unit via a tester bus. The pattern generator 32 generates an applied pattern to be applied to a DUT (semiconductor memory IC under test) 39 and an expected value pattern to be applied to a pattern comparator 37. In a semiconductor memory test apparatus, generally, an AL
PG (Algorithmic Pattern Generator) is used.
The ALPG is a pattern generator that generates a test pattern of a memory IC by computation using a register having an internal computation function.

A timing generator 33 generates a test pulse signal for obtaining a test period signal and a test timing of the entire apparatus, and generates a waveform shaper 34 and a comparator 3.
6 and the pattern comparator 37, etc., to take the timing of the test. The waveform shaper 34 shapes the applied pattern from the pattern generator 32 into a test signal waveform, and supplies a test signal to the DUT 39 via the driver 35. The response signal read from the DUT 39 is compared in voltage by the comparator 36, and the resulting logic signal is given to the pattern comparator 37. The pattern comparator 37 logically compares the logical pattern of the test result from the comparator 36 with the expected value pattern from the pattern generator 32 to detect a match / mismatch.
A pass / fail judgment is made in T39. The result of the test is given to a fail memory of an address fail memory (AFM) 38 and stored together with various kinds of information from the pattern generator 32.

The fail memory of the AFM 38 is a DUT 39
"1" is written to the address corresponding to the fail cell. That is, "0" is stored in the same memory area as the DUT 39.
Bit map (F
BM). When the test is completed, this AFM3
The information of the fail memory 8 is transferred to the fail buffer memory of the MRA (Memory Repair Analysis) 10 at a high speed by the dedicated bus for MRA. F of this MRA10
Work station (WS) with built-in BM and CPU
20 or, although not shown, failure analysis is performed by a personal computer (PC) or the like. In this specification, everything analyzed by a CPU including a PC is described and described as a representative of the WS 20. That is, the WS 20 includes all analyzers having a built-in CPU. The present invention relates to this failure analysis.

[0005] In order to analyze these defects, a so-called bitmap data processing method is conventionally used. In this bitmap data processing method, information on electrically defective cells of the FBM in the MRA 10 is read, and it is determined whether each cell is normal or defective and classified into various types of failure modes. For example, the pass / fail information of the cell at the intersection of the row (row) signal and the column (column) signal is read out, or the pass / fail of the row or column is read out one step at a time, and various faults are read by the information of each cell. Classified into shapes.

[0006] Failure analysis of the DUT 39 in the semiconductor memory test apparatus is diversified, and is classified into various failure modes. FIG. 5 shows an example of a failure mode type. 5A shows a block defect in FIG. 5A, a sub-block defect in FIG. 5B, a bit line defect in FIG. 5C, a word line defect in FIG. 5D, a cross line defect in FIG. 5E, and FIG. Of 1
6 shows examples of bit failure. FIG. 5 (B)
3 shows three examples of a slightly complicated line regularity defect (a), a line bundle defect (b), and a 2-bit defect (c). In addition, defective bits are displayed in three dimensions.

As described above, the semiconductor memory IC (DU)
Analyzing the inside of T), the R & D Department aims to elucidate defective parts and aim to eradicate them. In the manufacturing department, this DUT3
9 tests were performed at the wafer stage in the manufacturing process,
In order to repair a partially defective chip, a memory repair for replacing a defective part with a non-defective cell is performed.

[0008]

The test of the DUT 39 at the wafer stage in the manufacturing process can be sufficiently tested by a conventional method. However, in order to identify and analyze complicated defective / defective shapes of each cell, it takes much more analysis time than test time. For example, in the analysis of a 64 Mbit DRAM (dynamic RAM), 1
It takes about several tens of seconds to analyze a chip.
Since there are 500 chips, it takes about one hour to analyze one wafer. The throughput is too bad and the test cost is too high.

The present invention relates to a semiconductor memory I which is a DUT.
It is an object of the present invention to analyze the minimum necessary defective cell distribution shape in a short time and at high speed, although it is impossible to identify the defective shape of C even to detailed information.

[0010]

In order to achieve the above object, the present invention provides a column fail counter for each column line of an FBM (fail buffer memory) provided in an MRA (memory repair analysis). A row / fail counter is provided for each row line. Use the existing models. In a semiconductor memory test device, a column line is also called a word line, and a row line is also called a bit line. Therefore, the word line and the bit line will be described below. The distribution pattern of the electrically defective cells of the DUT is analyzed only by the word line / fail counter value of each column line and the bit line / fail counter value of each row line.

WS (work station) is an MRA
Receives the word line counter value and the bit line counter value, and analyzes and outputs the defective cell distribution shape that can be processed from the number of fail bits of each line by the line / fail bit analysis means of the operation unit. According to the present invention, if the number of columns (rows) and the number of rows (rows) are N, a counter value provided for each column and row can be used instead of reading and analyzing a failure for each cell in the related art. Can be analyzed,
The analysis time can be processed as fast as (1 / N ² ) or less, and the analysis time can be greatly reduced.

That is, since the defective cell distribution shape is analyzed only from the count value of the fail bit of the word line fail counter provided in each column of the FBM and the bit line fail counter provided in each row, for example, Assuming that the number N of columns and rows is 100, analysis can be performed in 1 / N ² = 1/100 ² = 10 ⁻⁴ times as long as the conventional analysis time. Since the analysis time is shorter than the measurement time, the analysis can be always performed. If this analysis is not sufficient, a conventional precision analysis may be performed. The configuration will be described below.

The first invention has a basic configuration. DUT
, A test signal is applied to the readout signal, and the response signal is logically compared with an expected value by a pattern comparator.
A semiconductor memory test apparatus for transferring to an FBM (fail buffer memory) of an RA (memory repair analysis) and analyzing a defective cell distribution shape of a DUT by using an MRA and a WS (work station).
MRA having a counter block including a word line fail counter for counting the number of defective cells for each column, a bit line fail counter for counting the number of defective cells for each row, and a counter block of the MRA. A WS having a built-in line / fail bit analyzing means for analyzing a defective cell distribution shape only from the transferred word line / fail counter value and bit line / fail counter value.

The second invention specifies a defective cell distribution shape which can be analyzed by the line / fail bit analyzing means. In other words, the WS line / fail bit analysis means analyzes block defects, sub-block defects, bit line defects, word line defects, cross line defects, and one-bit defects.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a detailed configuration diagram, and FIG. 3 is an explanatory diagram of a procedure for analyzing a defective cell distribution shape in the present invention. This will be described with reference to FIGS.

As shown in FIG. 1, the MRA 10 is an FBM.
11, the counter block 12, and the I / O (input /
Output) 14 and control unit 13 for controlling MRA 10
It consists of. FBM (Fail buffer memory)
11 is an AFM (address fail memory) 38 and MRA
The data is transferred at high speed through a dedicated bus. Counter block 12, as shown in FIG. 2, and a and bit line counter 12 _second word line counter 12 ₁ and each row of each column. Therefore, the number of fail bits of a column or a row can be counted immediately.

The WS (work station) 20 includes an operation unit 21, a control unit 23, an I / O 24, and the like. In addition to the conventional fail bit analysis means, the operation unit 21 has a new line / fail bit analysis unit. Means 22 are provided. The I / O 24 includes the test processor 31 and the MRA 10
And a dedicated bus for easy data transfer. The line / fail bit analysis means 22 analyzes the distribution shape of the defective cells as follows.

At the time of analysis, all memories are divided into predetermined blocks, and analysis is performed for each block.
Then, the defective shapes from the large area to the small area are analyzed and classified. Therefore, the classification order is block failure, bit line / word line failure, cross line failure,
The order is the order of bit failure. As a classification method, first, the number of defective cells in all bit lines and all word lines in all blocks is counted by respective counters. Next, based on the distribution of the counter values of the bit line and the word line of each block, the defective shape is classified as follows.

This will be described with reference to FIG. FIG. 3A shows the determination of a block failure. The counter value of the number of failures of each bit line or each word line is added, and a value equal to or greater than a specified value is determined as a block failure. The specified value is supposed to be 80% here, but can be arbitrarily determined. In the case of FIG. 3A, since all the cells are 30 and the word line counter value of the fail is 26, it is larger than 24, which is the specified value of 80%, and is regarded as a block failure. In the bit line failure and the word line failure, a bit line failure or a word line failure is defined as a counter value of each bit line or each word line that is equal to or greater than a specified value. In FIG. 3B, when the number of cells in each bit line is 5 and the specified value is 80%, the first row and the third row have bit line defects.

FIG. 3C shows a cross line defect. A cross line defect is defined as a cross line defect when there is a bit line having a defective cell of a specified value or more and a word line having a defective cell of another specified value or more. FIG.
In (c), assuming that the specified value is 80%, the third row and the third row
The column becomes a cross line defect. After the classification of the block defect, the bit line defect, the word line defect, and the cross line defect as described above, a defective cell which does not satisfy a specified value in the bit line and the word line is determined as a bit defect. FIG. 3D shows the situation. As described above, the distribution shape of the defective cells of the DUT is analyzed. The distribution shape that can be analyzed by this procedure is the shape of the group (A) in FIG. The shape of the group in FIG. 5B is difficult to analyze by this method. Conventional methods are suitable.

[0021]

As described in detail above, the present invention relates to a semiconductor memory test apparatus, in which
A word line fail counter is provided in each column of the BM 11 and a bit line fail counter is provided in each row.
Also, the WS 20 has a line / fail bit analysis unit 22.
Is provided, and the DUT 39 is provided with each word line fail counter value and bit line fail counter value.
Was able to analyze the state of the distribution shape of the electrically defective cells at high speed.

The analysis time can be reduced to the reciprocal times the product of the number of columns and the number of rows. If both the number of columns and the number of rows are N
And N is 100, the reduction ratio is 1 / N ² = 1
/ 100 ² = 10 ^-4 , and the analysis time did not matter. Only when detailed information is needed, it is better to analyze by the conventional method. As described above, the present invention has improved the test throughput of the semiconductor memory test apparatus and contributed to the reduction of the test cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a defective cell distribution shape in the present invention.

FIG. 4 is a block diagram of a semiconductor memory test apparatus.

FIG. 5 is an explanatory diagram of classification of a defective cell mode of a semiconductor memory;

[Explanation of symbols]

Reference Signs List 10 MRA (Memory Repair Analysis) 11 FBM (Fail Buffer Memory) 12 Counter Block 12 ₁ Word Line Counter (Column Fail Counter) 12 ₂ Bit Line Counter (Row Fail Counter) 13 Controller 14 I / O (input / output) 20 WS (work station) 21 operation unit 22 line / fail bit analysis means 23 control unit 24 I / O 31 test processor 32 pattern generator 33 timing generator 34 waveform shaper 35 driver 36 comparator 37 pattern comparator 38 AFM (address fail memory) 39 DUT (semiconductor memory IC under test)

Claims (2)

[Claims] 1. A test signal is applied to a DUT (39) and then read out, and the response signal is read by a pattern comparator (3).
At 7), the logical comparison with the expected value is performed, the result is transferred to the FBM (11) of the MRA (10), and the MRA (10) and the WS (2) are transferred.
0), a word line / fail counter (12 ₁ ) for counting the number of defective cells for each column of the FBM (11); An MRA (10) having a counter block (12) comprising a bit line fail counter (12 ₂ ) for counting the number of defective cells for each row, and transferred from the counter block (12) of the MRA (10). A WS (20) having an operation unit (21) incorporating a line / fail bit analyzing means (22) for analyzing a defective cell distribution shape from only the word line / fail counter value and the bit line / fail counter value. A semiconductor memory test apparatus characterized by the above-mentioned. 2. The line / fail bit analysis means (22) of the WS (20) analyzes a block defect, a sub-block defect, a bit line defect, a word line defect, a cross line defect, and a one-bit defect. 2. The semiconductor memory test device according to claim 1, wherein