JP2002007117A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To selectively execute plural processing. SOLUTION: Time-division multiplexed) data ((B) in Figure 2) are generated from input data ((A) in Figure 2) by time-division multiplexing the input unit data by two each. Then, processing to remove a noise is operated to the input unit data arranged ahead (data D-1, D-2, D-3,... to which 'A' is added in Figure) among the input unit data which are time-division multiplexed by two each. Also, processing to correct luminance is operated to the input unit data arranged behind (the data D-1, D-2, D-3,... to which 'B' is added in Figure).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus capable of performing different processes on input data according to an output destination.

[0002]

2. Description of the Related Art Devices capable of executing a plurality of processes without changing the basic hardware configuration have been developed.

[0003]

However, an apparatus that switches processing to be executed according to an output destination and outputs data subjected to the processing to a corresponding output destination,
Not disclosed.

The present invention has been made in view of such a situation, and the processing to be executed is switched according to the output destination, and the processed data can be output to the corresponding output destination. It is to be.

[0005]

According to an information processing apparatus of the present invention, input data input at a predetermined input speed is divided into N pieces of unit data constituting the input data by time division multiplexing. Generating means for generating time-division multiplexed data at a speed of N times the speed, connecting means for connecting to N output destinations, and obtaining the time-division multiplexed data generated by the generating means; An execution unit for executing a plurality of different signal processes according to the output destination; and an output destination connected by the connection unit to each of the N unit data time-division multiplexed to the time division multiplexed data. , The signal processing executed by the execution means is selectively switched in accordance with the timing at which each of the N unit data is acquired by the execution means. And Rikae means, signal processing by the execution means is performed, each of the N unit data, via the connecting means, characterized in that it comprises an output control means for outputting the corresponding output destination.

The execution means executes a plurality of class classification adaptation processing as signal processing, and the switching means selectively switches the class classification adaptation processing executed by the execution means in accordance with an output destination. I do.

The execution means forms a class tap on the basis of the class tap formation information, forms a prediction tap on the basis of the prediction tap formation information, executes a class classification adaptation process, and the switching means sets an output destination. The method is characterized in that the class tap formation information or the prediction tap formation information is switched accordingly.

The switching means detects the order of the unit data obtained by the execution means among the N data, and switches the signal processing executed by the execution means based on the detection result. It is characterized by.

In the information processing apparatus according to the present invention, from input data input at a predetermined input speed, each of unit data constituting the input data is time-division multiplexed by N pieces, and is N times the input speed. Time-division multiplexed data of speed is generated, connected to N output destinations, the generated time-division multiplexed data is obtained, and a plurality of different signal processings corresponding to the output destinations are performed on the time-division multiplexed data. Is executed,
Each of the N unit data is acquired such that the signal processing corresponding to the connected output destination is performed on each of the N unit data time-division multiplexed with the time division multiplexed data. The signal processing to be executed is selectively switched in accordance with the timing at which the signal processing is performed.
Each of the unit data is output to the corresponding output destination.

[0010]

FIG. 1 shows an example of use of a data processing apparatus 1 to which the present invention is applied. A plurality of external devices (a display device and a printing device in the example of FIG. 1) are connected to the data processing device 1, and the data processing device 1 performs processing on input data D (for example, image data). And selectively performs a process according to the output destination external device, and outputs the resulting data to the corresponding external device.

An outline of the operation of the data processing device 1 will be described. In the case of this example, as shown in FIG. 2A, data D input to the data processing device 1 has a predetermined size (data D-1, D-2, D-3,...). (Hereinafter, as appropriate,
It is assumed that time-division multiplexing is performed for each input unit data.

The data processing device 1 stores data D (FIG. 2).
When (A)) is input, time-division multiplexed data is generated in which each input unit data in the data D is time-divided by the number (N) of external devices as output destinations.

For example, when two external devices, a display device and a printing device, are output destinations, each input unit data in the data D is time-division multiplexed by two as shown in FIG. Time-division multiplexed data (connected and arranged in the figure) is generated. In FIG. 2B, for simplicity of the following description, among the same input unit data arranged two by two, the input unit data arranged at the top (first) is , "A", and the input unit data arranged thereafter (second) is denoted by "B".

Next, the data processing device 1 processes the input unit data in accordance with the time-division multiplexing order of the generated time-division multiplexed data. At this time, the data processing device 1
Switches the process to be executed depending on the order of the input unit data in the N connections.
That is, the processing is switched according to the output destination.

For example, in the example of FIG. 2B, the input unit data (“A”) arranged first in the two connections
Input unit data D-1, D-2, D-3,...)
Is subjected to a process for removing noise corresponding to the display device. Further, the input unit data D-1, D-2, D
-3,...) Are subjected to a process for correcting the luminance corresponding to the printing apparatus.

The data processing apparatus 1 executes processing on the time-division multiplexed data as described above, and the processing speed at this time is N times the input speed of the data D. Thus, the processed data is output to each of the external devices at a speed corresponding to the input speed of the data D.

In the example of FIG. 2, data D (FIG. 2A)
Is input at time T at a speed at which one input unit data is input. That is, in this case, the time-division multiplexed data is processed at a speed at which two input unit data are processed at time T, which is twice the input speed of the data D. Accordingly, the data D from which noise has been removed or the data D whose luminance has been corrected is output to the display device or the printing device at a speed corresponding to the same speed as the input speed of the data D.

FIG. 3 shows a configuration example of the data processing device 1.

The data D input to the data processing device 1
Is supplied to the input control unit 10. The input control unit 10
From the data D, the input unit data is time-division multiplexed to generate N time-division multiplexed data. To the unit 12.

In the case of this example, the input control unit 10
It has FIFOs 21 and 22 and a switch 23, and the data D
By controlling the writing and reading of the input unit data to and from the FIFO 21 or the FIFO 22 by using the switch 23, as shown in FIG. The time-division multiplexed data that has been division-multiplexed is generated, and is output to the synchronization signal generation unit 11 and the general information processing unit 12 at twice the input speed of the data D.

The synchronization signal generator 11 reads the synchronization information with reference to the header added to the input unit data of the time division multiplexed data supplied from the input controller 10, and performs synchronization based on the read synchronization information. Generate a signal,
The information is supplied to the general information processing unit 12. For example, as shown in FIG. 2C, a clock corresponding to the position of the input unit data of the time division multiplexed data (FIG. 2B) is generated as a synchronization signal.

The general information processing section 12 processes the time-division multiplexed data supplied from the input control section 10 according to an output destination (for example, a display device or a printing device) (for example,
A process for removing noise or a process for correcting luminance (hereinafter, appropriately referred to as signal processing) is executed.

The general information processing section 12 also selects the storage 14 of the storage section 13 and the FIFO 16 of the FIFO section 15 according to the output destination (according to the signal processing to be executed) (hereinafter referred to as selection processing as appropriate). ).

When executing the signal processing, the general information processing section 12 stores various data (hereinafter, appropriately referred to as necessary data) necessary for executing the signal processing in the storage 14 of the selected storage section 13. Supply and accumulate as appropriate. Then, the general information processing unit 12 reads out necessary data from the storage 14 of the storage unit 13 as necessary, and executes signal processing using the data.

The general information processing section 12 supplies data generated as a result of executing the signal processing (hereinafter, referred to as processed data) to the FIFO 16 of the selected FIFO section 15.

The storage unit 13 includes N storage units 1
4-1 to 14-N. The storage 14 selected by the general information processing unit 12 stores the necessary data supplied from the general information processing unit 12 and supplies these data to the general information processing unit 12 in response to a request.

The FIFO unit 15 includes FIFOs 16-1 to 16-N connected to external devices. The FIFO 16 selected by the general information processing unit 12 temporarily stores the processed data supplied from the general information processing unit 12, and outputs it to an external device connected thereto. In this case, a display device is connected to the FIFO 16-1, and a printing device is connected to the FIFO 16-2.

Next, the operation of the data processing device 1 will be described.

In this example, as shown in FIG. 4A, time division multiplexed data D is input to the data processing device 1. FIG. 4A shows the data D of FIG.
Are shown in correspondence with the data shown in FIGS. 4B to 4G to be described later and a common time axis.

In the input control unit 10 (FIFO 21), for example,
It is assumed that data D-1 (FIG. 4A) of the input unit data is input. At this time, the FIFO 21 stores the input data D
-1 is temporarily held, and then the FIFO 22 and the switch 23
Output to At this timing, the switch 23
The data D-1 which is the output of the FIFO 21 is input to the synchronization signal generation unit 11 and the general information processing unit 12.

The FIFO 22 receives the data D-1 from the FIFO 21
For a predetermined period of time (data D-1 held in the FIFO 21).
Is output to the synchronization signal generation unit 11 and the general information processing unit 12), and then output to the switch 23. At this timing, the switch 23 connects to the FIFO 22 (switches the connection from the FIFO 21 to the FIFO 22), inputs the data D-1 that is the output of the FIFO 22, and sends the data D-1 to the synchronization signal generation unit 11 and the general information processing unit 12. Output.
That is, as a result of the processing up to this point, as shown in FIG. 4B, two data D-1 connected in series ("
The data D-1) with A "and" B "are output to the synchronization signal generation unit 11 and the general information processing unit 12.

The data D-1 from the FIFO 22 is transmitted to the switch 2
3, while being output to the synchronization signal generation unit 11 and the general information processing unit 12, the data D-2 is stored in the FIFO 21.
(FIG. 4A) is input. The FIFO 21 stores the data D-2
Is held for a predetermined time (the time until the data D-1 held in the FIFO 22 is output to the synchronization signal generation unit 11 and the general information processing unit 12), and then output to the FIFO 22 and the switch 23. At this timing, the switch 23
It connects to the FIFO 21 (switches the connection from the FIFO 22 to the FIFO 21), inputs the data D-2 which is the output of the FIFO 21, and outputs it to the synchronization signal generator 11 and the general information processor 12.

The FIFO 22 holds the data D-2 from the FIFO 21 for a predetermined time, and then outputs the data D-2 to the switch 23. The switch 23 connects to the FIFO 22 at this timing,
The data D-2 output from the FO 22 is input and output to the synchronization signal generator 11 and the general information processor 12. That is, by the processing so far, as shown in FIG.
Two data D-2 ("A" in the figure) connected and arranged
And data D-2) to which "B" is added,
1 and to the general information processing section 12.

FIFO 21 through switch 2 of input control unit 10
3 is such that, at time T, two input unit data are output to the synchronization signal generation unit 11 and the general information processing unit 12 (to be output at twice the input speed of the data D). , Execute the above-described processing.

The above processing is also performed on the input unit data (FIG. 4A) after the data D-3. That is, thereby, each input unit data of the data D is time-division multiplexed two by two (see FIG. 4B).
Is output to the synchronization signal generation unit 11 and the general information processing unit 12 at twice the input speed of the data D. In addition,
FIG. 4B shows the time-division multiplexed data of FIG.
In addition to the data D of FIG.
It is shown in correspondence with the data of (G) and a common time axis.

The synchronizing signal generator 11 generates a synchronizing signal based on the time division multiplexed data supplied from the input controller 10 (FIG. 4C), and supplies the synchronizing signal to the general information processor 12.

The general information processing section 12 is configured as shown in FIG.
When the data D-1 to which A "is added is supplied from the input control unit 10, that is, among the same input unit data which are arranged two by two, the first input unit arranged When the data is supplied, the storage unit 13 corresponding to the display device (corresponding to signal processing for removing noise)
Of the storage 14-1 and the FIFO 16-1 of the FIFO unit 15 (perform selection processing).

Then, the general information processing section 12 supplies necessary data to the storage 14-1 of the selected storage section 13 or reads out the necessary data, so that the data D-1 marked with "A" is Signal processing for removing noise. The general information processing unit 12 supplies the processed data Da-1 generated as a result of the processing to the FIFO 16-1 of the selected FIFO unit 15.

The signal supplied to the FIFO 16-1 of the FIFO unit 15
The processed data Da-1 (the data D-1 to which "A" is added in FIG. 4B from which noise has been removed) from the general information processing unit 12 is as shown in FIG. At the timing, it is written there. Then, after being held for a predetermined time,
The data is output to the display device at the timing shown in FIG.

Next, in FIG. 4 (B), when the data D-1 to which "B" is added is input from the input control unit 10, that is, the same input data which is arranged two by two is connected. When the second input unit data of the unit data is supplied, the general information processing unit 12 stores the storage unit 14 of the storage unit 13 corresponding to the printing apparatus (corresponding to the signal processing for correcting the luminance). -2 and FIFO 16-2 of FIFO unit 15
Select

Then, the general information processing section 12 supplies necessary data to the storage 14-2 of the selected storage section 13 and reads out the necessary data, so that the data D-1 with "B" is added. Then, signal processing for correcting the luminance is executed. The general information processing unit 12 supplies the processed data Db-1 generated as a result of the processing to the FIFO 16-2 of the selected FIFO unit 15.

The data supplied to the FIFO 16-2 of the FIFO unit 15
The processed data Db-1 (data D-1 to which "B" is added in FIG. 4B in which the luminance has been corrected) from the general information processing unit 12 is as shown in FIG. At the timing, it is written there. Then, after being held for a predetermined period, it is output to the printing apparatus at a timing as shown in FIG.

Next, in FIG. 4 (B), when data D-2 (input unit data arranged first) to which "A" is added is supplied to the general information processing section 12, the storage section The storage 14-1 of the thirteenth and the FIFO 16-1 of the FIFO unit 15 are selected again. Then, signal processing for removing noise is performed on the data D-2 to which "A" is added, and the processed data Da-2 generated as a result is selected by the selected FIF.
The data is supplied to the FIFO 16-1 of the O unit 15.

The signal supplied to the FIFO 16-1 of the FIFO unit 15 is
The processed data Da-2 from the general information processing unit 12 (data D-2 from which noise has been removed and data "A" is added in FIG. 4B) is as shown in FIG. 4D. At the timing, it is written there. Then, after being held for a predetermined time,
The data is output to the display device at the timing shown in FIG. That is, the processed data Da is output to the display device at a speed corresponding to the input speed of the data D.

Next, in FIG. 4B, when data D-2 (the second unit of input data) with "B" is supplied to the general information processing unit 12, the storage unit 13 is selected, and the FIFO 16-2 of the FIFO unit 15 is selected. Then, for the data D-2 to which "B" is added,
Signal processing for correcting the luminance is executed, and the processed data Db-2 generated as a result is stored in the selected FIFO unit 1.
5 FIFO 16-2.

The data supplied to the FIFO 16-2 of the FIFO unit 15
The processed data Db-2 (the data D-2 to which "B" is added in FIG. 4B in which the luminance has been corrected) from the general information processing unit 12 is as shown in FIG. At the timing, it is written there. Then, after being held for a predetermined period, it is output to the printing apparatus at a timing as shown in FIG. That is, the processed data Db is output to the printing device at a speed corresponding to the input speed of the data D.

The above processing is also performed on the input unit data supplied after the data D-3 time-division multiplexed to the time division multiplexed data (FIG. 4B).

In this way, different processing is performed on the input data D according to the output destination, and the data generated as a result is output to the corresponding output destination. Here, the case where the data D is input in a time-division multiplexed manner is described as an example. However, the present invention is applicable to a case where the data D is input in a state where other multiplexing such as frequency multiplexing is performed. can do. In this case,
The input control unit 10 has a configuration capable of generating the above-described time-division data from the input frequency-multiplexed data D.

FIG. 5 shows an example of the configuration of the general information processing section 12.

The general information processing section 12 includes a switching signal generation circuit 31, a processing related information management section 32, a processing execution section 33,
It comprises a storage data input / output control unit 34 and an output data output control unit 35.

The time division multiplexed data supplied to the general information processing section 12 is supplied to the switching signal generation circuit 31 and the processing execution section 33, respectively. The general information processing unit 12
The synchronization signal supplied from the synchronization signal generation unit 11 is
It is supplied to the switching signal generation circuit 31.

The switching signal generating circuit 31 refers to the supplied header added to the input unit data of the time-division multiplexed data, and the input unit data is included in the N connections in the time-division multiplexed data. , And a signal including the detection result (hereinafter, referred to as a switching signal) is generated.

In the example shown in FIG. 4B, the input unit data is the first input unit data (input unit data indicated by "A" in the figure), or is the second input unit data. Is detected, and a switching signal including the detection result is generated.

The switching signal generation circuit 31 converts the generated switching signal into a processing-related information management unit 32 at a timing corresponding to the synchronization signal supplied from the synchronization signal generation unit 11.
To the output data output control unit 35. For example, a switching signal is output at a timing corresponding to the synchronization signal shown in FIG.

The processing-related information management unit 32 is a processing execution unit 3
3 (hereinafter referred to as processing-related information). When a switching signal is supplied from the switching signal generation circuit 31, the signal processing corresponding to the switching signal is performed. The processing-related information is supplied to the processing execution unit 33.

In the example of FIG. 4B, the fact that the first input unit data (input unit data indicated by “A” in the figure) is detected is included in the switching signal. If so, the processing-related information of the signal processing for removing the noise is supplied to the processing execution unit 33. On the other hand, when the switching signal includes the fact that the second input unit data (the input unit data indicated by “B” in the figure) is detected in the switching signal, the signal processing for correcting the luminance is performed. Is supplied to the processing execution unit 33.

The processing execution section 33 supplies the signal processing corresponding to the switching signal from the switching signal generating circuit 31 to the input unit data of the time division multiplexed data supplied from the processing related information management section 32. It is executed based on the processing related information.

In the example of FIG. 4B, if the detection of the first input unit data is included in the switching signal, the signal processing for removing noise is executed, and the second processing is performed. If the switching signal indicates that the input unit data placed second is detected, signal processing for correcting the luminance is executed.

The stored data input / output control unit 34 selects the storage 14 of the storage unit 13 corresponding to the switching signal from the switching signal generation circuit 31 (performs a selection process). Accordingly, the processing execution unit 33 appropriately supplies data required for executing the signal processing to the storage 14 of the selected storage unit 13 via the storage data input / output control unit 34 and stores the data. . Then, the processing execution unit 33, if necessary,
, Necessary data is read out, and signal processing is executed using the data.

In the example shown in FIG. 4B, when the detection of the first input unit data is included in the switching signal, the storage unit 13
-1 is selected. As a result, the processing execution unit 33 appropriately transfers necessary data for executing signal processing for removing noise to the storage 14-1 of the selected storage unit 13 via the stored data input / output control unit 34. Supply and accumulate. Then, the processing execution unit 33 reads out the necessary data via the stored data input / output control unit 34 as necessary, and executes signal processing for removing noise using the data.

On the other hand, if the detection of the second input unit data is included in the switching signal, the storage unit 14-2 of the storage unit 13 is selected. As a result, the processing execution unit 33 appropriately transfers necessary data for executing the signal processing for correcting the luminance to the storage 14-2 of the selected storage unit 13 via the storage data input / output control unit 34. Supply and accumulate. Then, the processing execution unit 33 reads out the necessary data via the stored data input / output control unit 34 as necessary, and executes signal processing for correcting the luminance using the data.

The output data output control unit 35 is a FIFO unit 1 corresponding to the switching signal from the switching signal generation circuit 31.
5 is selected (performs selection processing). Accordingly, the processing execution unit 33 outputs the processed data generated as a result of performing the signal processing on the input unit data to the selected FI through the output data output control unit 15.
The data is output to the FIFO 16 of the FO unit 15.

In the example shown in FIG. 4B, if the detection of the first input unit data is included in the switching signal, the FIFO 16-1 of the FIFO unit 15 is selected. As a result, the processing execution unit 33 processes the processed data generated as a result of executing the signal processing for removing noise (data Da-1, Da-2, Da-3,... In FIG. 4D).
Is output to the FIFO 16-1 of the selected FIFO unit 15 via the output data output control unit 35.

On the other hand, if the detection of the second input unit data is included in the switching signal, the FIFO 16-2 of the FIFO unit 15 is selected. As a result, the processing execution unit 33 executes the processed data (the data Db-1, Db-2, Db-3,... In FIG. 4F) generated as a result of executing the signal processing for correcting the luminance. Via the output data output control unit 35 to the FIFO1 of the selected FIFO unit 15
Output to 6-2.

Next, the configuration of the processing execution unit 33 will be described with reference to FIG.

The processing execution unit 33 has two data generation circuits 41 and 44, three control memories 42, 45 and 47, one control signal generation circuit 43, and one arithmetic circuit 46.

Each of the control memory 42, the control memory 45, and the control memory 47 is
And supplies the data to the data generation circuits 41 and 44 and the arithmetic circuit 46 as necessary. The control memories 42, 45, 47
The processing-related information respectively supplied differs depending on the data generated by the data generation circuits 41 and 44 or the calculation performed by the calculation circuit 46. That is, the processing execution unit 3
3 differs depending on the signal processing executed (for example, noise removal processing or luminance correction processing). A specific example will be described later.

The time-division multiplexed data supplied to the processing execution unit 33 is transmitted to the data generation circuit 41 and the data generation circuit 44.
Supplied to The switching signal supplied from the switching signal generation circuit 31 to the processing execution unit 33 is supplied to the data generation circuits 41 and 44, the control signal generation circuit 43, and the arithmetic circuit 46, respectively.

Data generation circuit 41 is data necessary for executing signal processing corresponding to the switching signal from switching signal generation circuit 31 (hereinafter referred to as generated data).
Is generated based on the processing-related information supplied from the control memory 42 and supplied to the control signal generation circuit 43. In addition,
Specific examples of the generated data generated by the data generation circuit 41 include:
It will be described later.

At this time, the data generating circuit 41 generates data (necessary data) necessary for generating the generated data.
Is appropriately supplied to the storage 14 of the storage unit 13 via the storage data input / output control unit 34 and accumulated. Then, the data generation circuit 41 reads out necessary data via the stored data input / output control unit 34 as necessary, and generates generated data by using the data.

The control signal generation circuit 43 generates a control signal necessary for signal processing corresponding to the switching signal from the switching signal generation circuit 31 based on the generated data supplied from the data generation circuit 41, And to the control memory 47. A specific example of the control signal generated by the control signal generation circuit 43 will be described later.

The control memory 45 supplies to the data generation circuit 44 the processing-related information stored at the address corresponding to the control signal supplied from the control signal generation circuit 43 among the stored processing-related information.

The data generating circuit 44 generates generated data necessary for executing the signal processing corresponding to the switching signal from the switching signal generating circuit 31 based on the processing-related information supplied from the control memory 45. It is supplied to the arithmetic circuit 46. A specific example of the generated data generated by the data generation circuit 44 will be described later.

At this time, the data generating circuit 44 generates data (necessary data) necessary for generating the generated data.
Is appropriately supplied to the storage 14 of the storage unit 13 via the storage data input / output control unit 34 and accumulated. Then, the data generation circuit 44 reads out necessary data via the stored data input / output control unit 34 as necessary, and generates generated data by using the data.

The control memory 47 supplies, to the arithmetic circuit 46, the processing-related information stored at the address corresponding to the control signal supplied from the control signal generation circuit 43 among the stored processing-related information.

The operation circuit 46 uses the generated data supplied from the data generation circuit 44 and the processing-related information supplied from the control memory 47 to generate the switching signal generation circuit 3.
1 is executed, and the data (processed data) calculated as a result is output to the predetermined FIFO 16 of the FIFO unit 15 via the output data output control unit 35.
To supply.

Next, the operation of the processing execution unit 33 when performing the classification adaptive processing as the noise removal processing will be described. That is, in the case of this example, the data generation circuit 41
Generates a class tap as generation data, the control signal generation circuit 43 generates a class code as a control signal, the data generation circuit 44 generates a prediction tap as generation data, and the arithmetic circuit 46 An operation for predicting the pixel value of the pixel is performed.

That is, at this time, the processing-related information from the processing-related information management unit 32 stored in the control memory 42 is information on a pixel selected as a class tap in the classification adaptive processing (hereinafter referred to as a class The processing-related information stored in the control memory 45 is information on a pixel selected as a prediction tap in the classification adaptive processing (hereinafter, appropriately referred to as prediction tap formation information). . The processing-related information stored in the control memory 47 is a prediction coefficient set for calculating a prediction value in the classification adaptive processing.

The data generation circuit 41 sequentially sets pixels constituting an image (an image from which noise has been removed) finally obtained by the class classification adaptive processing as a pixel of interest, and assigns a control memory to the pixel of interest. The pixel indicated by the class tap formation information supplied from 42 is selected from the image of the data D (input image), and the selected pixel is supplied to the control signal generation circuit 43 as a class tap. For example, as shown in FIG. 7, pixels in a 3 × 3 matrix centering on a pixel X1 of the input image corresponding to the target pixel (pixels in a dotted frame in the drawing)
Is selected as the class tap.

The control signal generation circuit 43 detects the characteristic (for example, distribution) of the pixel value of the pixel of the input image (hereinafter, referred to as input pixel) constituting the class tap supplied from the data generation circuit 41, and The value pre-assigned to the feature is defined as the class of the pixel of interest as the control memory 45,
47.

By the way, since 8-bit data is generally assigned to a pixel, even in this example, if 8-bit data is assigned to an input pixel, a class tap is formed. For example, the number of pixel values of the pixels to be processed becomes enormous, and there arises a problem that the storage capacity of a memory or the like for storing coefficients must be increased.

Therefore, in the case of this example, the control signal generation circuit 43 actually performs a process of reducing (compressing) the number of bits of the pixels constituting the class tap as preprocessing for class classification. As a compression processing method of this number of bits, for example, ADRC (Adaptive Dynamic Range Coding)
There is processing.

In the ADRC processing, the maximum pixel value MAX and the minimum pixel value MIN are detected from the pixels constituting the processing block (class tap), and the pixel value MAX is detected.
A difference DR between the pixel value MIN and the pixel value MIN (= pixel value MAX−pixel value MIN) is calculated, and this DR is set as a local dynamic range DR of the processing block. Then, the pixel value MIN is subtracted from each pixel value constituting the processing block, and the subtracted value is calculated as DR
/ Are divided respectively 2 ^K. As a result, each pixel value forming the class tap, which is a processing block, is requantized to K bits smaller than the original number of allocated bits (8 bits). As a result, compared to the case where ADRC processing is not performed,
The number of classes can be reduced.

Note that the compression processing in the control signal generation circuit 43 is not limited to the ADRC processing, and it is also possible to use other methods such as vector quantization.

The control signal generation circuit 43 calculates the input pixels constituting the class tap thus obtained.
The class is detected from the K-bit pixel value, and the class code of the pixel of interest is determined based on the detection result.

The data generation circuit 44 calculates the prediction tap formation information supplied from the control memory 45 (of the prediction tap formation information stored in the control memory 45, The input pixel indicated by the prediction tap formation information stored at the address corresponding to the class code supplied from the generation circuit 43 is selected, and this is supplied to the arithmetic circuit 46 as a prediction tap. Note that, in this example, the prediction tap is a three-row 3
It is assumed that it is formed from pixels in a column.

The arithmetic circuit 46 supplies the pixel values (pixel values x ₁ , x ₂ ,...) Of the input pixels constituting the prediction tap supplied from the data generation circuit 44 and the control memory 47 at this time. A prediction coefficient set (a prediction coefficient set stored at an address corresponding to the class code supplied from the control signal generation circuit 43 among the prediction coefficient sets stored at this time in the control memory 47) (a prediction coefficient set w ₁ , W ₂ ,...) And the prediction coefficient set w
And each pixel value x is calculated according to Equation (1), which is a linear linear combination model defined by, for example, linear combination.
The predicted value E [y] of the target pixel y is calculated. The predicted value E
[y] is the processed data in this case,
Represents the pixel value of the finally generated image.

E [y] = w ₁ x ₁ + w ₂ x ₂ +... (1) It is to be noted that the calculation can be performed using a model based on nonlinear coupling.

The arithmetic circuit 46 supplies the processed data thus calculated to the output data output control unit 35.

As described above, the classification adaptive processing for removing noise is executed. The classification appropriate processing for removing noise is described in more detail in Japanese Patent Application Laid-Open No. Hei 7-115569 filed earlier by the present applicant.

Next, the operation of the processing execution unit 33 when executing the classification adaptive processing corresponding to the luminance correction processing will be described. That is, in the case of this example, class tap formation information as processing-related information stored in the control memory 42, predicted tap formation information as processing-related information stored in the control memory 45, and processing stored in the control memory 47. Each of the prediction coefficient sets as related information corresponds to a class classification adaptive process for correcting luminance.

The data generation circuit 41 supplies a luminance value of a pixel in one field or one frame of the input image to the control signal generation circuit 43, for example.

The data generation circuit 41 also includes a control memory 4
A class tap is formed on the basis of the class tap formation information supplied from 2 and supplied to the control signal generation circuit 43.

The control signal generation circuit 43 generates an n-bit code based on the luminance values of the pixels of one field or one frame supplied from the data generation circuit 41. Specifically, the luminance value is divided into s regions, and the frequencies in one supplied field or one frame are integrated for each region. Then, based on the integrated frequency, quantization of a bits is performed for each region, and a total of n (= s
× a) A code of bits is generated. The code generated here (hereinafter, referred to as a first class code)
Represents the bias of the distribution of the luminance value (whether it is biased toward dark or bright).

The control signal generation circuit 43 detects the maximum value and the minimum value of the luminance value from the input pixels constituting the class tap supplied from the data generation circuit 41, and detects the maximum value and the minimum value of the detected luminance value. , An m-bit code is generated. The code generated here (hereinafter, referred to as a second class code) indicates a state of so-called spatial luminance change.

The control signal generation circuit 43 further calculates an average value of the luminance values of the input pixels constituting the class tap supplied from the data generation circuit 41, shifts the calculated average value, and converts the average value into bits. And generate a third class code.

The control signal generation circuit 43 determines a final class code based on the generated first class code, second class code, and third class code,
It is supplied to the control memory 45 and the control memory 47.

Data generation circuit 44 in the case of this example
The processing of the control memory 47 is basically the same as the above-described case of executing the class classification adaptive processing for removing noise, and thus a detailed description thereof will be omitted.

As described above, the classification adaptive processing for correcting the luminance is executed. The classification appropriate processing for correcting the luminance is described in more detail in Japanese Patent Application Laid-Open No. Hei 9-147101 filed earlier by the present applicant.

[0100]

According to the information processing apparatus of the present invention, from input data input at a predetermined input speed, each of unit data constituting the input data is time-division multiplexed by N pieces. It generates time-division multiplexed data at N times speed, connects to N output destinations, obtains the generated time-division multiplexed data, and generates a plurality of different time-division multiplexed data according to the output destination. The signal processing is performed, and the N unit data is time-division-multiplexed to the time-division multiplexed data, so that the N unit data is processed according to the connected output destination for each of the N unit data. , The signal processing to be executed is selectively switched in accordance with the acquisition timing, so that each of the N unit data subjected to the signal processing is output to the corresponding output destination. Can .

[Brief description of the drawings]

FIG. 1 is a diagram showing a usage example of a data processing device 1 to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of time-division multiplexed input data.

FIG. 3 is a block diagram illustrating a configuration example of a data processing device 1 of FIG. 1;

FIG. 4 is a timing chart of data processing.

FIG. 5 is a block diagram illustrating a configuration example of a general information processing unit 12 in FIG. 3;

FIG. 6 is a block diagram illustrating a configuration example of a common processing execution unit 33 of FIG. 5;

FIG. 7 is a diagram for explaining a class tap.

[Explanation of symbols]

Reference Signs List 1 data processing device, 10 input control unit, 11 synchronization signal generation unit, 12 general information processing unit, 13 storage unit, 14 storage, 15 FIFO unit, 16
FIFO, 31 switching signal generation circuit, 32 processing related information management section, 33 processing execution section, 34 stored data input / output control section, 35 output data output control section,
41 data generation circuit, 42 control memory, 43
Control signal generation circuit, 44 data generation circuit, 45
Control memory, 46 arithmetic circuit, 47 control memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B013 AA18 5C021 PA62 PA72 PA78 PA82 RB00 RB03 RB07 RB08 SA00 XA43 YA01 YC03 YC07 YC08 YC09 YC14 ZA01 ZA02 5C059 KK06 MA28 MC18 MD04 PP16 TA60 TB08 TC02 TC14 TD34

Claims (4)

[Claims] 1. Time-division multiplexing at a speed of N times the input speed, wherein N pieces of unit data constituting the input data are time-division multiplexed from input data input at a predetermined input speed. Generating means for generating data; connecting means for connecting to the N output destinations; obtaining the time-division multiplexed data generated by the generating means; Executing means for executing a plurality of different signal processings according to the time-division multiplexing data; and performing time-division multiplexing on the time-division multiplexed data. The signal executed by the execution unit according to the timing at which each of the N unit data is acquired by the execution unit so that the signal processing is executed in accordance with the signal processing. Switching means for selectively switching processing; and output control for outputting each of the N unit data subjected to the signal processing by the execution means to the corresponding output destination via the connection means. And an information processing apparatus. 2. The execution unit executes a plurality of class classification adaptation processes as the signal processing, and the switching unit executes the class classification adaptation process executed by the execution unit according to the output destination. The information processing apparatus according to claim 1, wherein the information is selectively switched. 3. The classifier according to claim 3, wherein the execution unit forms a class tap based on the class tap formation information, forms a prediction tap based on the prediction tap formation information, executes the class classification adaptation processing, The information processing apparatus according to claim 2, wherein the controller switches the class tap formation information or the prediction tap formation information according to the output destination. 4. The switching means detects in which of the N unit data the unit data obtained by the execution means is arranged, and based on a result of the detection, the execution means executes the unit data. 2. The information processing apparatus according to claim 1, wherein the signal processing is switched.