JP2002006808A - Electronic device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new driving method capable of securing a high duty ratio and also capable of displaying a picture (video) normally even in the case where an electronic device has a sustenance period shorter than an address period, and its driving is hardly affected by the rounding of a signal waveform in a driving method in which digital gradation and time-dependent gradation are combined in the electronic device. SOLUTION: In this driving method, it is possible to set the length of a sustenance period 104 independently of the length of an address period 103 by providing a clear period 105 forcibly in a period before the address period of a next frame is started after a sustenance period 104 is completed in a sub- frame period 102 having a sustenance period shorter than the address period. Since this non-display period is provided by changing the potential of a holding capacitance line, driving of the non-display period is hardly affected by the rounding of the signal waveform because it is different from a method in which a non-display period is provided by changing the potential of a cathode wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a configuration of an electronic device. The present invention particularly relates to a driving method of an active matrix electronic device having a thin film transistor (TFT) formed on an insulator and an electronic device using the same.

[0002]

2. Description of the Related Art In recent years, as a flat panel display replacing an LCD (Liquid Crystal Display), an EL display using an electroluminescence (EL) element in a pixel portion has attracted attention, and active research is being conducted.

There are roughly two types of LCD drive systems. One is a passive matrix type used for STN-LCDs and the like, and the other is an active matrix type used for TFT-LCDs and the like. Similarly, in the EL display, there are roughly two types of driving methods. One is a passive matrix type and the other is an active matrix type.

[0004] In the case of the passive matrix type, wirings serving as electrodes are arranged above and below the EL element.
Then, a voltage is sequentially applied to the wiring, and a current is caused to flow through the EL element, thereby lighting the element. On the other hand, in the case of the active matrix type, each pixel has a TFT so that a signal can be held in each pixel.

FIG. 14 shows a configuration example of an active matrix type electronic device used for an EL display. FIG. 14A is an overall circuit configuration diagram, in which a pixel portion 1453 is provided in the center of a substrate 1450. To the left and right of the pixel part,
A gate signal line side driver circuit 1452 for controlling the gate signal line is provided. Gate signal line drive circuit 14
Although 52 may be arranged on one side, it is desirable to arrange both sides in consideration of the efficiency and reliability of circuit operation. Pixel section 1
Above 453, a source signal line side driver circuit 1451 for controlling the source signal line is provided. FIG. 14B shows an enlarged view of one pixel. Reference numeral 1401 denotes a T which functions as a switching element when writing a signal to a pixel.
FT (hereinafter referred to as switching TFT). 1
Reference numeral 402 denotes a TFT that functions as an element (current control element) for controlling a current supplied to the EL element 1403 (hereinafter, referred to as an electroluminescence driving TFT;
L drive TFT). For the operation of the TFT, a grounded source is preferable, and a manufacturing restriction of the EL element 1403 is used. Therefore, a P-channel TFT is used for the EL driving TFT, and the EL driving TFT is provided between the anode of the EL element 1403 and the current supply line 1407. A method of arranging the TFT 1402 is generally used, and is often used. Reference numeral 1404 denotes a storage capacitor for holding a signal (voltage) input from the source signal line 1406. The storage capacitor 1404 in FIG.
Is connected to the current supply line 1407, but a dedicated wiring may be used. T for switching
The gate terminal of the FT 1401 is connected to a gate signal line 1405.
The source terminal is connected to a source signal line 1406. In addition, a drain terminal of the EL driving TFT 1402 is connected to an anode or a cathode of the EL element 1403, and a source terminal is connected to a current supply line 1407.

An EL element has a layer containing an organic compound capable of obtaining electroluminescence (electroluminescence generated by applying an electric field) (hereinafter, referred to as an EL layer), an anode, and a cathode. Luminescence of an organic compound includes light emission when returning from a singlet excited state to a ground state (fluorescence) and light emission when returning from a triplet excited state to a ground state (phosphorescence). The present invention can also be applied to a light emitting device using.

In this specification, all layers provided between the anode and the cathode are defined as EL layers. Specifically, the EL layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer,
An electron transport layer and the like are included. Basically, the EL element has an anode /
It has a structure in which a light emitting layer / cathode is laminated in order. In addition to this structure, an anode / hole injection layer / light emitting layer / cathode or anode / hole injection layer / light emitting layer / electron transport layer / cathode Etc. in some cases.

In this specification, an element formed by an anode, an EL layer, and a cathode is called an EL element.

Next, the operation of the circuit of the active matrix type electronic device will be described with reference to FIG. First, when the gate signal line 1405 is selected, a voltage is applied to the gate electrode of the switching TFT 1401, and the switching TFT 1401 is turned on. Then, the signal (voltage) of the source signal line 1406 is changed to the storage capacitor 1
404. The voltage of the storage capacitor 1404 is EL
Since the voltage between the gate and the source of the driving TFT 1402 becomes V _GS , a current corresponding to the voltage of the storage capacitor 1404 flows through the EL driving TFT 1402 and the EL element 1403. As a result, the EL element 1403 is turned on.

The luminance of the EL element 1403, that is, the EL element
The amount of current flowing through the EL driving TFT 1402
V_GSCan be controlled by V_GSIs the storage capacity 1404
Which is input to the source signal line 1406
Signal (voltage). That is, the source signal line 1406
By controlling the signal (voltage) input to the
The luminance of the L element 1403 is controlled. Finally, the gate signal
When the line 1405 is in the non-selected state, the switching TFT
The gate of 1401 is closed and the switching TFT 140 is closed.
1 is turned off. At that time, the storage capacity 1404 stores
The accumulated charge is retained. Therefore, the EL driving TFT
1402 V_GSIs held as it is, and V _GSDepending on the
The current flows through the EL driving TFT 1402 and the EL element 1
Continue to 403.

Regarding the above contents, SID99 Digest: P
372: “Current Status and futureof Light-Emitting
Polymer Display Driven by Poly-Si TFT ”, ASIA DISP
LAY98: P217: “High Resolution Light Emitting Pol
ymer Display Driven by Low Temperature Polysilicon
Thin Film Transistor with Integrated Driver ”, Eu
ro Display99 Late News: P27: “3.8 Green OLED wit
h Low Temperature Poly-Si TFT ”etc.

By the way, there are an analog gray scale method and a digital gray scale method as a gradation expression method of an EL display. In the case of the former analog gradation method, an EL driving TFT
By changing the gate-source voltage V _GS of 1402, E
This is a method of controlling the current flowing through the L element 1403 and changing the luminance in an analog manner. On the other hand, in the latter digital gradation method, the gate-source voltage V _GS of the EL driving TFT is in a range where no current flows through the EL element (below the lighting start voltage) or a range where the maximum current flows (luminance). (Saturation voltage or higher). That is, the EL element is in only the light-on state and the light-off state.

In an EL display, a digital gray scale method is mainly used in which variation in characteristics such as a threshold value of a TFT does not affect display. However, in the case of the digital gradation method, only two gradation display can be performed as it is,
A plurality of techniques for increasing the number of gradations in combination with another method have been proposed.

One of them is a method that combines the area gradation method and the digital gradation method. The area gray scale method is a method of controlling the area of a lit portion to output a gray scale. That is, one pixel is divided into a plurality of sub-pixels, and the number and area of the lit sub-pixels are controlled to express gradation. The disadvantage of this method is that it is difficult to increase the resolution and increase the number of gradations because the number of sub-pixels cannot be increased. For the area gradation method, Eu
ro Display 99 Late News: P71: “TFT-LEPDwith Imag
e Uniformity by Area Ratio Gray Scale ”, IEDM 99:
P107: “Technology for Active Matrix Light Emitti
ng Polymer Displays ”.

As another scheme for increasing the number of gradations, there is a method of combining a time gradation method and a digital gradation method. The time gray scale method is a method of outputting a gray scale by using a difference in lighting time. That is, one frame period is divided into a plurality of sub-frame periods, and the number and length of the lit sub-frame periods are controlled to express gradation.

For a case where the digital gradation method, the area gradation method and the time gradation method are combined, see IDW'99: P171.
: “Low-Temperature Poly-Si TFT Driven Light-Emitt
ing-Polymer Displays and Digital Gray Scale for Un
iformity ”.

[0017]

FIG. 15 is a timing chart in a driving method combining digital gray scale and time gray scale. In FIG. 15A, the address (writing) period and the sustain (lighting) period are completely separated within the sub-frame period, whereas in FIG. 15B, they are not separated.

Normally, in a driving method using a time gray scale,
It is necessary to provide an address (write) period and a sustain (lighting) period for each bit. A driving method in which an address (write) period and a sustain (lighting) period are completely separated (a method of entering a sustain (lighting) period after an address (writing) period for one screen is completely completed in each subframe period) ), The ratio of the address (write) period within one frame period increases,
In addition, in the address (write) period, while a gate signal line of a certain row is selected, as shown in FIG. 15A, a period 1501 in which writing and lighting are not performed in another row is performed. Therefore, the duty ratio (the ratio of the length of the sustain (lighting) period within one frame period) is greatly reduced. There is no other way to shorten the address (write) period than to increase the operation clock, and there is a limit to multi-grayscale in consideration of the operation margin of the circuit. On the other hand, address (write) period and sustain (light)
In the driving method that does not separate the period from the period, for example, immediately after the end of the gate signal line selection period of the kth row, the EL element on the kth row enters the sustain (lighting) period. In the meantime, one of the pixels is lit. Therefore, it can be said that this is an advantageous driving method for further increasing the duty ratio.

However, if the address (writing) period and the sustain (lighting) period are not separated, the following problems occur. The length of one address (write) period is from the start of the gate signal line selection period of the first row to the end of the gate signal line selection period of the last row. At a certain point in time, it is not possible to select two different gate signal lines. Therefore, in a driving method in which the address (write) period and the sustain (lighting) period are not separated,
The sustain (lighting) period is at least the same as the address (writing) period (exactly, “from the end of signal writing on the first row of the gate signal line to the end of signal writing on the last row”). Length) or longer. Therefore, when increasing the number of gradations, the minimum unit of the sustain (lighting) period is limited. FIG.
In (B), the subframe period SF for the minimum bit
And time to address (writing) period Ta ₄ ends at _4, the only period from the first address (writing) period starts at the next frame period do not overlap, 1
The length of the portion indicated by 502 is the minimum unit,
If the sustain (lighting) period is shorter than this, display cannot be performed normally. Therefore, when the digital gradation method and the time gradation method are combined, the length of the sustain (lighting) period is determined by a ratio of a power of two. It becomes difficult.

According to the present invention, in a driving method mainly combining a digital gray scale and a time gray scale, a high duty ratio is ensured and a sustain (lighting) period shorter than an address (writing) period is used. It is an object of the present invention to provide a new driving method that can normally display an image (video).

[0021]

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention takes the following measures.

According to the driving method of the electronic device of the present invention, the sustain (lighting) is performed in a sub-frame period having a sustain (lighting) period shorter than the address (writing) period.
After the end of the period, the non-display period of the EL element is forcibly provided to prevent the overlap of the address (write) period until the start of the address (write) period of the next subframe period. The length of the (lighting) period can be set independently of the length of the address (writing) period. As a result, even when the sustain (lighting) period of the lower bits is shortened due to the increase in the number of gradations, overlapping of the address (writing) periods is avoided, and a normal image (video) can be displayed.

The configuration of the electronic device according to the present invention will be described below.

According to a first aspect of the present invention, there is provided a driving method of an electronic device according to the present invention, wherein one frame period includes n sub-frame periods SF.
_1, SF _2, ···, have SF _n, wherein n sub each frame period address (writing) period Ta _1,
Ta _2, ···, and Ta _n, sustain (turn on) periods Ts
_1, Ts _2, in the driving method of an electronic device having a · · · Ts _n, at least one sub-frame period among the n sub-frame periods, the said address (writing) period sustain (lighting) The subframe period SF _m (1 ≦ m ≦
an address (writing) period Ta _m at n), the sub-frame periods SF address at _{m + 1} (writing) period Ta _{m + 1}
If the bets overlap, after the completion of the sustain (lighting) period SF _m in the sub-frame period SF _m, to have a clear period Tc _m in the address (writing) period until the start of the period Ta m _{+ 1} Features.

According to a second aspect of the present invention, there is provided a driving method of an electronic device according to the present invention, wherein one frame period includes n sub-frame periods SF.
_1, SF _2, ···, have SF _n, wherein n sub each frame period address (writing) period Ta _1,
Ta _2, ···, and Ta _n, sustain (turn on) periods Ts
_1, Ts _2, in the driving method of an electronic device having a · · · Ts _n, at least one sub-frame period among the n sub-frame periods, the said address (writing) period sustain (lighting) has a duration that period overlap, j and the address (writing) period Ta _n in the subframe period SF _n of (0 <j) th frame, j
+1 th frame address in the sub-frame periods SF ₁ (write) If the period Ta ₁ and overlap the sustain (light) in the sub-frame period SF _n of j-th frame
After the end of the period SF _n, is characterized by having a clear period Tc _n in the period leading up to the start of the j + 1 th frame address in the sub-frame periods SF ₁ (writing) period Ta _1.

According to a third aspect of the present invention, there is provided a method of driving an electronic device according to the present invention, wherein one frame period includes n sub-frame periods SF.
_1, SF _2, ···, have SF _n, wherein n sub each frame period address (writing) period Ta _1,
Ta _2, ···, and Ta _n, sustain (turn on) periods Ts
_1, Ts _2, in the driving method of an electronic device having a · · · Ts _n, certain sub-frame period _{SF k (1 ≦ k ≦ n} )
, The length of the address (write) period is ta _k ,
As a sustain (lighting) the length ts _k of period 1 the length of the gate signal line selection period _{t g (ta k, ts k} , t g> 0), when the ta _k> ts _k is satisfied, SF _k Assuming that the length of the clear period of tc _k (tc _k > 0) is tc
_{c k ≧ ta k - (ts} k + t g) is characterized by the establishment.

According to a fourth aspect of the present invention, there is provided a method of driving an electronic device according to any one of the first to third aspects, wherein the clear signal is input during the clear period. Is provided by raising the potential of the storage capacitor line or lowering the potential of the storage capacitor line in response to a signal input from the storage capacitor line driving circuit.

According to a fifth aspect of the present invention, in the driving method of the electronic device according to the fourth aspect, the EL element is turned off during the clear period regardless of an image signal. Features.

According to a sixth aspect of the present invention, there is provided an electronic device comprising: a source signal line side driving circuit; a gate signal line side driving circuit;
A storage capacitor line driver circuit; a pixel portion; the pixel portion includes a plurality of source signal lines, a plurality of gate signal lines, a plurality of current supply lines, a plurality of storage capacitor lines, and a plurality of pixels. And the plurality of pixels each include a switching transistor, an EL driving transistor, a reset transistor, a storage capacitor, and an EL element, and a gate electrode of the switching transistor has a gate signal. One of a source region and a drain region of the switching transistor is electrically connected to a source signal line, and the other is electrically connected to a gate electrode of the EL driving transistor; A gate electrode of the reset transistor is electrically connected to a storage capacitor line, and a source region and a drain region of the reset transistor are One is electrically connected to the gate signal line, the other is electrically connected to the gate electrode of the EL driving transistor, and the storage capacitor has one electrode electrically connected to the current supply line. The other electrode is electrically connected to the gate electrode of the EL driving transistor, one of a source region and a drain region of the EL driving transistor is electrically connected to a current supply line, and the other is It is characterized by being electrically connected to one electrode of the EL element.

According to a seventh aspect of the present invention, in the electronic device according to the sixth aspect, the storage capacitance line is
The storage capacitor line drive circuit is electrically connected to the storage capacitor line drive circuit, and a signal having an amplitude is input from the storage capacitor line drive circuit.

The electronic device according to the present invention as set forth in claim 8 has the following features.
The frame period includes n sub-frame periods SF ₁ , SF ₂ ,
.., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta ₂ ,.
-, and Ta _n, a sustain (lighting) periods Ts _1, Ts _2,
.. Ts _n, and in at least one of the n sub-frame periods, a period in which the address (writing) period and the sustain (lighting) period overlap. , Subframe period SF _m
Address (writing) period Ta in (1 ≦ m ≦ n)
_When the address (write) period Tam _{+ 1} in the sub-frame period SF _{m + 1} overlaps with the address (write) period Ta _{m + 1} in the sub-frame period SF _{m + 1} , the address (write) period ends after the sustain (lighting) period SF _{m in} the sub-frame period SF _m ends. It is characterized in that operating the driving method having the clear period Tc _m in the period leading up to the start of writing) period Ta m _{+ 1.}

According to the ninth aspect of the present invention, there is provided an electronic device comprising:
The frame period includes n sub-frame periods SF ₁ , SF ₂ ,
.., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta ₂ ,.
-, and Ta _n, a sustain (lighting) periods Ts _1, Ts _2,
.. Ts _n, and in at least one of the n sub-frame periods, a period in which the address (writing) period and the sustain (lighting) period overlap. , j (0 <j) th frame of the sub-frame periods addresses in SF _n and (writing) period Ta _n, j + 1 th frame of the sub-frame periods SF ₁
If the address (writing) period Ta ₁ in the overlap, after the completion of the sustain (lighting) period SF _n in j-th frame of the sub-frame period SF _n, in the j + 1 th frame of the sub-frame periods SF ₁ Address (write)
In the period leading up to the start of the period Ta ₁ it is characterized in that operating the driving method having the clear period Tc _n.

[0033] The electronic device of the present invention according to claim 10 is:
One frame period includes n sub-frame periods SF ₁ and S
F ₂ ,..., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta ₂ ,
···, Ta _n and, sustain (turn on) period Ts _1, Ts
_2, and a · · · Ts _n, certain sub-frame period SF _k
In (1 ≦ k ≦ n), the length of the address (write) period is ta _k , the length of the sustain (lighting) period is ts _k ,
The length of one gate signal line selection period _{t g (ta k, ts k} ,
When t _k > ts _k holds as t _g > 0), SF _k
The length of the clear period having When tc _k (tc _k> 0) of always, tc _k ≧ ta _k - is characterized by (ts _k + t _g) is established.

An electronic device according to the present invention as defined in claim 11,
11. The electronic device according to claim 8, wherein the clear signal input in the clear period increases a potential of the storage capacitor line by inputting a signal from a storage capacitor line driving circuit. 12. Alternatively, it is provided by lowering the potential of the storage capacitor line.

An electronic device according to a twelfth aspect of the present invention comprises:
12. The electronic device according to claim 11, wherein the EL element is turned off during the clear period regardless of an image signal.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described.

As shown in FIG. 16, one terminal of the storage capacitor 1604 is connected to the current supply line 16.
07, and this current supply line is normally kept at a constant potential. Alternatively, as shown in FIG. 17, there is a method in which a storage capacitor line 1711 is arranged, and one terminal of the storage capacitor 1704 is connected to the storage capacitor line. In this case, the potential of the storage capacitor line 1711 is kept constant.

In the present invention, since the circuit configuration shown in FIG. 17 is used, no special structure is required. However,
The characteristic is that the potential of the storage capacitor line 1711 is not constant and a signal can be input using a circuit.

In the address (write) period and the sustain (lighting) period, the potential of the storage capacitor line 1711 is kept at a constant potential. And the EL driving TF
In the case where a non-display period is forcibly provided regardless of the gate voltage of T1703, the potential of the storage capacitor line 1711 is increased. (When the EL driving TFT 1702 is a P-channel type, the reverse operation is performed when an N-channel type is used.) This is hereinafter referred to as a clear signal, and the period during which the clear signal is input is cleared. Expressed as a period. With this operation, the gate-source voltage V _{GS of the} EL driving TFT 1702 electrically connected to the storage capacitor 1704 is obtained.
At the same time, and is forced to be in the OFF state.
The supply of the current to the L element 1703 is stopped, and a clear period can be set.

In order to keep the storage capacitor line 1711 at a constant potential during the address (writing) period and the sustain (lighting) period, it is desirable to set the potential to a certain low level. This is because, when the period during which the storage capacitor line is kept at a constant potential at 1711 is defined as period A, the potential of the storage capacitor line is further increased from the state of period A when a clear signal is input. In this case, it is necessary to further increase the potential. (When the EL driving TFT 1702 is a P-channel type. When an N-channel type is used, the opposite operation is performed. Therefore, it is desirable to keep the potential high in the A period.)

In the driving method of the present invention, the storage capacitor line 171
Since a clear period can be forcibly provided by inputting a clear signal to address 1 (address) (write)
Even when it is desired to provide a sustain (lighting) period shorter than the period, it can be easily realized by changing the length of the clear period. Therefore, in combination with the above-described effect of increasing the duty ratio, it can be said that the present invention is very effective for increasing the number of gradations.

Regardless of the signal input from the signal line, E
To forcibly turn off the L element 1703,
A method of reducing the potential difference between the anode 1709 and the cathode 1710 of the EL element 1703 to 0, the EL driving TFTs 1702 and E
A method of adding a current blocking TFT between the L element 1703 and turning off the current blocking TFT to cut off the current supply to the EL element 1703 can be cited. When the waveform of an input signal is rounded (a phenomenon in which a signal is delayed or dulled at the time of rising or falling of a pulse), the timing of each period is shifted, so that the influence becomes larger as the period becomes shorter. There is also a disadvantage that the aperture ratio of the pixel is reduced due to the point and the additional TFT. On the other hand, in the driving method of the present invention, the electric potential of the storage capacitor line is changed to release the electric charge of the storage capacitor so that the EL element is not turned on. Therefore, since it is not necessary to perform the operation of the potential of the signal line related to the image (video) signal in the non-display section, the above-mentioned rounding of the signal waveform does not affect and it is also necessary to add a TFT or the like. There is no lowering of the aperture ratio.

Next, the potential pattern of each part will be described. Referring to FIG. Also, the circuit will be referred to FIG.

In FIG. 18, reference numeral 1801 denotes a potential of the source signal line 1706, and 1802 denotes an EL driving TFT 1703.
1803 is a gate signal line 1705
1804 indicates the potential of the storage capacitor line 1711. Note that FIG. 18 illustrates a case where the polarity of the switching TFT 1701 is N-channel and the polarity of the EL driving TFT 1702 is P-channel. First, the potential 1804 of the storage capacitor line 1711 is kept at a certain constant potential. This potential is preferably kept low because there is an operation of raising it later. After that, the source signal line 1706,
A signal is input to the gate signal line 1705, and writing to each pixel is performed.

Here, FIG. 18A shows a TF for driving EL.
When the LO signal is input to the gate electrode of T1702,
FIG. 18B illustrates the case where a Hi signal is input to the gate electrode of the EL driving TFT 1702. FIG.
In (A), with the selection of the gate signal line 1705, EL
The LO signal is input to the gate electrode of the driving TFT 1702, the potential is reduced, the state is turned on, and the EL element 1703 is turned on.
Starts lighting. On the other hand, in FIG. 18B, the selection of the gate signal line 1705 causes the EL driving TFT 170
Since the Hi signal is input to the gate electrode of No. 2 and the device is turned off, the EL element 1703 does not light. Subsequently, the selection period of the gate signal line 1705 ends, and the gate signal line 1
Even after the potential 705 drops, the potential applied to the gate electrode of the EL driving TFT 1702 is maintained by the storage capacitor 1704. In the case of FIG.
Continues to light, and in the case of FIG.

Next, the operation of each section before and after the clear period in the present invention will be described. In FIG. 18, the potential 1804 of the storage capacitor line 1711 is raised at the timing indicated by the dotted line XX ′. Here, the storage capacitor line 1711
It is desirable that the amplitude of the potential 1804 be larger than the amplitude of the source signal line 1706. At this time, the selection period of the gate signal line 1705 ends, and the switching TFT
1701 is already in a non-conductive state,
04 is stored as it is, the potential 18 of the storage capacitor line 1711 connected to one terminal
When the voltage 04 increases, the potential at the other terminal, that is, the gate voltage 1802 of the EL driving TFT 1702 increases. Therefore, in FIG.
At the timing indicated by the dotted line X ', the EL driving TFT
The potential 1802 of the gate electrode 1702 increases. As a result, the EL driving TFT 1702 becomes non-conductive,
The current supply to the EL element 1703 is stopped, and the EL element 1703 is turned off. 18B, similarly, the storage capacitor line 171
With the increase in the potential 1804 of the EL drive TFT 1
The potential 1802 of the gate electrode 702 also increases, but in this case, there is no change in the non-display state.

By such an operation, the gate signal line 1705 is selected in the pixel portion of another row, and the source signal line 1 is selected.
The EL element 1703 can be forcibly set to the non-display state even during a period from 706 when a signal is being written. Therefore, the sustain (lighting) period can be freely set by changing the length of the clear period.

Although the case where the switching TFT 1701 is of the N-channel type has been described with reference to FIG. 18, the operation according to the driving method of the present invention can be normally performed without any problem when the P-channel type is used. Below, Figure 1
This will be described with reference to FIG. Also, the circuit will be referred to FIG.

First, the potential 1904 of the storage capacitor line 1711
Is kept constant. It is desirable to keep it low for the same reasons as described above. After that, signals are input to the source signal line 1706 and the gate signal line 1705,
Writing to each pixel is performed.

Here, FIG. 19A shows an EL driving TF.
When the LO signal is input to the gate electrode of T1702,
FIG. 19B illustrates the case where a Hi signal is input to the gate electrode of the EL driving TFT 1702. FIG.
In (A), with the selection of the gate signal line 1705, EL
The LO signal is input to the gate electrode of the driving TFT 1702, the potential is reduced, the state is turned on, and the EL element 1703 is turned on.
Starts lighting. On the other hand, in FIG. 19B, the selection of the gate signal line 1705 causes the EL driving TFT 170
Since the Hi signal is input to the gate electrode of No. 2 and the device is turned off, the EL element 1703 does not light. Subsequently, the selection period of the gate signal line 1705 ends, and the gate signal line 1
Even after the potential at 705 decreases, the potential applied to the gate electrode of the EL driving TFT 1702 is maintained by the storage capacitor. In the case of FIG. 19A, the EL element 1703 continues to light, and the potential of FIG. In this case, the light-off state continues.

Next, the operation of each section before and after the clear period in the present invention will be described. In FIG. 19, the potential 1904 of the storage capacitor line 1711 is raised at the timing indicated by the dotted line YY ′. At this time, in FIG. 19A, the selection period of the gate signal line 1705 ends, and the switching TFT 1701 is already in a non-conductive state. Therefore, the voltage between both terminals of the storage capacitor 1704 is stored as it is. Storage capacitance line 17 connected to one terminal
When the potential 1904 of No. 11 rises, the EL driving TF
The gate voltage 1902 at T1702 increases.
Therefore, in FIG. 19A, the potential 1902 of the gate electrode of the EL driving TFT 1702 increases at the timing indicated by the dotted line YY ′. Accordingly, the EL driving TFT 1702 is turned off, and the EL element 1703 is turned off.
The current supply to the power supply stops and the light is turned off. FIG. 19 (B)
In this case, the potential of the gate electrode of the EL driving TFT 1702 is raised at the same time when the potential of the storage capacitor line 1711 is raised.
902 also goes up. At this time, the switching TFT 17
The potential on the source side of 01 also increases. Since the polarity of the switching TFT 1701 is a P-channel type, the switching TFT 1701 is temporarily brought into a conductive state when the source-side potential increases. for that reason,
The switching TFT 1701 moves in a direction in which the potential between the source and the drain becomes equal. That is, the EL driving T
The gate electrode potential 1902 of the FT 1702 decreases. At this time, since the potential 1903 of the gate signal line 1705 is constant, the gate electrode potential 1
When 902 falls, the switching TFT 170
1, the source-side potential decreases, and the switching TFT 1701 moves in a direction in which the gate-source voltage decreases. When the voltage falls below the threshold voltage of the switching TFT 1701, the switching TFT 1701 returns to a non-conductive state. The switching TFT 1701 is P
In the case of the channel type, each unit operates as described above. In any case, when the potential of the storage capacitor line 1711 is increased, the EL driving TFT 1702 is turned off.

As described above, the switching TFT 1701
Can operate normally regardless of the polarity of the N-channel type or the P-channel type.

In the present embodiment, the present invention has been described by taking as an example a case where the time gray scale method and the digital gray scale method are combined. The EL element can be made non-display by the same method.

Embodiments of the present invention will be described below.

[Embodiment 1] FIG. 20A shows an example of the entire circuit configuration. A pixel portion is arranged at the center. FIG. 20B is a circuit diagram of one pixel surrounded by a dotted frame 2000.
Shown in A source signal line side driving circuit is arranged above the pixel portion. A gate signal line side driving circuit is arranged on the left side of the pixel portion. A storage capacitor line driving circuit is provided on the right side of the pixel portion.

An actual driving method will be described with reference to a timing chart. Here, for the sake of simplicity, when n-bit gradation is expressed by a method combining digital gradation and time gradation, n ³ = 2 ³ = 8
The expression of gradation will be described. Note that the circuit diagram is still referred to FIG.

FIG. 1 is a timing chart of the potentials of the gate signal line and the storage capacitor line in each row at that time. In the circuit used in this embodiment, the switching TFT 2
001 is an N-channel type. Therefore, in the gate signal line selection period, the potential of the gate signal line 2005 becomes high, and the switching TFT 2001 is turned on.

The description will be made step by step. First, in order to express an n-bit gray scale, one frame period needs to be divided into n sub-frame periods. In the present embodiment, since it is 3 bits, it is divided into three subframe periods SF ₁ - SF _3. Each sub-frame period has an address (writing) period Ta _{1 to} Ta ₃ and a sustain (lighting) period Ts _{1 to} Ts ₃ . The address (writing) period is a period required to perform writing for one screen, and therefore all have the same length. The length of the sustain (lighting) period is changed by a power of two. That is, in the case of FIG. 1, Ts ₁ : Ts ₂ : Ts ₃
= 4: 2: 1.

However, gradation display is possible without necessarily setting the length of the sustain (lighting) period to a ratio of a power of two.

In the timing chart of this embodiment, the address (writing) period and the sustain (lighting) period are not completely separated, and have a sustain (lighting) period shorter than the address (writing) period. . First, SF
_{At 1} , the gate signal lines 2005 are selected one row at a time, during which signals are written to the pixels. Writing for one row ends (gate signal line selection period ends).
When, the line enters the sustain (lighting) periods Ts _1.

[0060] sustain (lighting) in SF ₁ after the end of period Ts _1, enters the SF _2, likewise the gate signal line 2005 is selected line by line, the signal writing is performed to the pixel.
During this time, the potential of the storage capacitor line 2011 is kept constant.

[0061] After that, it enters the SF _3. In SF ₃ ,
As shown in FIG. 1, than the address (writing) period Ta _3, a short sustain (lighting) periods Ts _3. Therefore,
As in the case of the previous subframe period, when the sustain (lighting) period starts after the end of the address (writing) period and the next subframe period immediately starts after the end of the sustain (lighting) period, FIG. As shown in FIG.
_{Before third} address (writing) period Ta ₃ is terminated, the portion for the address SF ₁ in the next frame period (writing) period Ta ₁ is started, the address (writing) period different subframe periods overlap Appears. This period means that two different columns of gate signal lines are selected at the same time, and at such a timing, an image (video) cannot be displayed normally.

Then, as shown in FIG. 2B, Ts ₃
The EL element 2003 is raised by raising the potential of the storage capacitor line 2011 during a certain period (a period from the end of the sustain (lighting) period to the start of the next address (writing) period) after the end of the operation. A non-lighting period is forcibly provided. This, the clear period of the EL element 2003, clear period (Tc _n n: number of subframes) and denoted.
In FIG. 2 (B), that Tc ₃ after the end of Ts ₃ is provided, since the overlap of Ta ₃ and the next Ta ₁ can be avoided, image (video) can be displayed properly.

[0063] Incidentally, the clear period, at subframe period _{SF k (1 ≦ k ≦ n} ), an address (writing) shorter than the period Ta _k sustain (lighting) period T
When having a s _k, the address (writing) period length ta _k, sustain (lighting) the length ts _k of period 1 the length of the gate signal line selection period _{t g (ta k, ts k} , t _g >
0), the length of the clear period of SF _k is tc
When _k (tc _k> 0), _{always, tc k ≧ ta k - (} ts
_k + t _g ) must be at least as long as it holds.

[Embodiment 2] In this embodiment, Embodiment 1
An example in which there are a plurality of sustain (lighting) periods in which the number of gray scales is larger than that of the address (writing) period and which is shorter than the address (writing) period will be described. Since the circuit is the same as that of the first embodiment, FIG. 20 will be referred to continuously.

In this embodiment, the expression of ⁵ -bit (2 ⁵ = 32) gradation will be described. As in the case of the 3-bit gradation expression, the address (write) periods Ta _{1 to} Ta ₅ are all the same length, and the sustain (lighting) periods Ts _{1 to} Ts
₅ is Ts ₁ : Ts ₂ : Ts ₃ : Ts ₄ : Ts ₅ = 16: 8:
4: 2: 1. Of these, the lengths of Ts ₃ , Ts ₄ , and Ts ₅ are shorter than the address (write) period.

Immediately after the signal writing is completed, EL
In the driving method in which the lighting of the element 2003 is started, when the next address (writing) period starts after the sustain (lighting) period ends, as shown in FIG. A portion where the writing) period overlaps appears. In the figure, in the range indicated by a,
Two of Ta ₃ and Ta ₄ overlap, in the range indicated by b, two of Ta ₄ and Ta ₅ overlap, in the range indicated by c, and Ta ₄ and Ta _5, the next sub-frame period in 'and are three overlap (denoted in the range indicated by d, Ta ₅ and Ta ₁ Ta ₁ Ta _1)' are two overlap. As described above, as the number of gradations increases, the sustain (lighting) period of the minimum unit becomes shorter, so that three or more address (writing) periods may overlap. Thus, as in the first embodiment, after the sustain (lighting) period ends and before the next address (writing) period starts, the clear periods Tc ₃ , Tc ₄ and Tc ₅ are provided. This avoids duplication of the address (write) period and allows normal images (video)
Can be displayed.

[Embodiment 3] In this embodiment, the pixel circuit and the driving circuit provided around the pixel unit are provided on the same substrate.
FT (N-channel TFT and P-channel TFT)
Will be described in detail.

First, as shown in FIG. 4A, a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass is oxidized. A base film 5002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed. For example, a plasma CVD method _{SiH 4, NH 3, N 2} O silicon oxynitride film 5002a made from 10 to 20
0 [nm] (preferably 50 to 100 [nm]) is formed, similarly SiH _4, N ₂ O hydrogenated silicon oxynitride film 5002b made from 50 to 200 [nm] (preferably 100 to
150 [nm]). Although the base film 5002 has a two-layer structure in this embodiment, the base film 5002 may have a single-layer structure or a structure in which two or more insulating films are stacked.

The island-shaped semiconductor layers 5003 to 5006 are formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method.
The thickness of the island-shaped semiconductor layers 5003 to 5006 is 25 to 8
It is formed with a thickness of 0 [nm] (preferably 30 to 60 [nm]). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz], and the laser energy density is 100 to 400 [mJ / cm ² ] (typically, 2
00 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used, the pulse oscillation frequency is set to 1 to 10 [kHz], and the laser energy density is set to 30.
0 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / c]
m ² ]). And a width of 100 to 1000 [μm],
For example, a laser beam condensed linearly at 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 80 to 98 [%].

Next, island-shaped semiconductor layers 5003 to 5006
Is formed to cover the gate insulating film 5007. The gate insulating film 5007 is formed by a plasma CVD method or a sputtering method.
It is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm]. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 [Pa], and the substrate temperature was 30.
It can be formed by discharging at a high-frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm ² ] at 0 to 400 [° C.]. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed of Ta to a thickness of 50 to 100 [nm],
A second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

The Ta film is formed by a sputtering method by sputtering a Ta target with Ar. in this case,
When an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. Also, α
The phase Ta film has a resistivity of about 20 [μΩcm] and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 [μΩcm] and is not suitable for a gate electrode. . In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to the Ta α-phase is formed on a Ta base with a thickness of about 10 to 50 [nm]. Can be easily obtained.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
[μΩcm] or less is desirable. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, in the case of using the sputtering method, a W target having a purity of 99.9999 [%] is used, and a W film is formed by giving sufficient consideration so as not to mix impurities from the gas phase during film formation. Resistivity 9-20
[μΩcm] can be realized.

In this embodiment, the first conductive film 500
8 was Ta, and the second conductive film 5009 was W. However, there is no particular limitation, and any of Ta, W, Ti, Mo, Al, and Cu was used.
Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than the present embodiment is that the first conductive film is formed of tantalum nitride (T
aN), and the second conductive film is made of W,
Forming a first conductive film of tantalum nitride (TaN);
Preferably, the first conductive film is formed of tantalum nitride (TaN), and the second conductive film is formed of Cu.

Next, a mask 5010 made of a resist is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively Coupled)
d Plasma: Inductively coupled plasma) etching method,
CF ₄ and Cl ₂ are mixed as an etching gas, and RF (13.56 [MH]) of 500 [W] is applied to the coil-type electrode at a pressure of 1 [Pa].
z]) Power is supplied to generate plasma. 100 [W] RF (13.56 [MH] also on the substrate side (sample stage)
z]) Apply power and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and Ta
The film is etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, and the end portions of the first and second conductive layers are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 [nm] by over-etching. become. Thus, by the first etching process, the first conductive layer and the second conductive layer
Conductive layers 5011 to 5016 (first conductive layer 50
11a to 5016a and second conductive layers 5011b to 501
6b) is formed. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched to a thickness of about 20 to 50 [nm] to form a thinned region (FIG. 4A). .

Then, a first doping process is performed to add an impurity element imparting N-type (FIG. 4B). The doping may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and the acceleration voltage is 60 to
It is performed as 100 [keV]. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting the N-type. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5017 to 5025 are formed in a self-aligned manner. First
1 × 10 ²⁰ to 1 ×
An impurity element imparting N-type is added in a concentration range of 10 ²¹ [atoms / cm ³ ].

Next, a second etching process is performed as shown in FIG. Similarly, using the ICP etching method,
Mixing CF ₄ , Cl ₂ and O ₂ into the etching gas,
500 [W] RF (13.5) is applied to the coil type electrode at the pressure of [a].
6 [MHz]) power is supplied to generate plasma. On the substrate side (sample stage), 50 [W] RF (13.56 [MH]
z]) Power is applied and a self-bias voltage lower than that in the first etching process is applied. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 5026 to 5031 (first Conductive layers 5026a to 5031a and second conductive layers 5026b to 526a
031b) is formed. At this time, the gate insulating film 500
7, the second shape conductive layers 5026 to 5031
The region which is not covered by the above is further etched by about 20 to 50 [nm] to form a thinned area.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the dose is lower than that of the first doping process, and an impurity element imparting N-type is doped under a condition of a high acceleration voltage. For example, the acceleration voltage is set to 70 to 120 [keV], and 1 × 10 ¹³ [atoms / cm ² ]
4A, a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. The doping is performed in the second shape conductive layers 5026-5
030 is used as a mask for the impurity element, and doping is performed so that the impurity element is also added to a region below the second conductive layers 5026a to 5030a. Thus, the third impurity regions 5032 to 5041 overlapping with the second conductive layers 5026a to 5030a, the first impurity region
Of second impurity regions 5042 to 5042 between impurity regions
51 are formed. The impurity element imparting N-type is the second element.
In the impurity region, the concentration is set to 1 × 10 ¹⁷ to 1 × 10 ¹⁹ [atoms / cm ³ ], and in the third impurity region, the concentration is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [atoms / cm ³ ].
The concentration is set to 1 × 10 ¹⁸ [atoms / cm ³ ].

Then, as shown in FIG. 5B, island-shaped semiconductor layers 5004 and 500 forming a P-channel TFT are formed.
6 shows a fourth impurity region 5 having a conductivity type opposite to the first conductivity type.
052 to 5063 are formed. Second conductive layer 5027
b and 5030b are used as masks for impurity elements, and impurity regions are formed in a self-aligned manner. At this time, N
Island-shaped semiconductor layers 5003, 5 forming a channel type TFT
005 is entirely covered with a resist mask 5200. Each of the impurity regions 5052 to 5063 is doped with phosphorus at a different concentration, but is formed by an ion doping method using diborane (B ₂ H ₆ ), and the impurity concentration in each of the regions is 2 × 10 ²⁰ to 50 ×. 2 × 10 ²¹ [atoms / c
m ³ ].

Through the above steps, impurity regions are formed in the respective island-shaped semiconductor layers. Second overlapping with the island-shaped semiconductor layer
Conductive layers 5026 to 5030 function as gate electrodes. 5031 functions as an island-shaped source signal line.

In order to control the conductivity type in this way, FIG.
As shown in (C), a step of activating the impurity element added to each of the island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed in a nitrogen atmosphere of not more than [ppm] at 400 to 700 [° C.], typically 500 to 600 [° C.]. In this embodiment, the heat treatment is performed at 500 [° C.] for 4 hours. However, 50
When the wiring material used for 26 to 5031 is weak to heat,
Activation is preferably performed after an interlayer insulating film (mainly composed of silicon) is formed in order to protect wirings and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG. 6A, the first interlayer insulating film 5064 is formed from a silicon oxynitride film by 100 to 100.
It is formed with a thickness of 200 [nm]. After forming a second interlayer insulating film 5065 made of an organic insulating material thereon,
Contact holes are formed in the interlayer insulating film 5064, the second interlayer insulating film 5065, and the gate insulating film 5007, and each wiring (including connection wiring and signal line) 5066 to
After patterning and forming 5071 and 5073, the pixel electrode 5072 in contact with the connection wiring 5071 is formed by patterning.

As the second interlayer insulating film 5065, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5065 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, an acrylic film is formed with a thickness that can sufficiently flatten a step formed by a TFT. Preferably, it is 1 to 5 [μm] (more preferably, 2 to 4 [μm]).

The contact holes are formed by dry etching or wet etching. The contact holes reach the N-type impurity regions 5017 to 5021 and 5023 to 5025 or the P-type impurity regions 5052 to 5063, the contact holes reach the wiring 5031, A contact hole (not shown) reaching the current supply line and a contact hole (not shown) reaching the gate electrode are formed.

Further, wiring (including connection wiring and signal line) 5
066 to 5071, 5073, the Ti film is 100 [n
m], an aluminum film containing Ti is 300 [nm], and a Ti film 1
A laminate film having a three-layer structure in which 50 nm is continuously formed by a sputtering method and patterned into a desired shape is used. Of course,
Other conductive films may be used.

Further, in this embodiment, an ITO film having a thickness of 110 [nm] was formed as the pixel electrode 5072, and was patterned. Contact is established by arranging the pixel electrode 5072 so as to be in contact with and overlap with the connection wiring 5071. Alternatively, a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5072 becomes the anode of the EL element (FIG. 6).
(A)).

Next, as shown in FIG. 6B, an insulating film containing silicon (a silicon oxide film in this embodiment) is formed to a thickness of 500 [nm], and is formed at a position corresponding to the pixel electrode 5072. An opening is formed, and a third interlayer insulating film 5074 is formed. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the EL layer due to the step becomes a significant problem.

Next, the EL layer 5075 and the cathode (MgA
g electrode) 5076 is continuously formed using a vacuum evaporation method without opening to the atmosphere. Note that the thickness of the EL layer 5075 is 80
The thickness of the cathode 5076 is 180 to 300 [nm] (typically 20 to 200 [nm] (typically 100 to 120 [nm]).
0 to 250 [nm]).

In this step, an EL layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the EL layer has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, it is preferable that a metal mask is used to hide portions other than the desired pixels, and that the EL layer and the cathode are selectively formed only in necessary portions.

That is, first, a mask for hiding all pixels other than the pixels corresponding to red is set, and the EL layer and the cathode for emitting red light are selectively formed using the mask. Next, a mask for hiding all pixels other than pixels corresponding to green is set, and the EL layer and the cathode for emitting green light are selectively formed using the mask. Next, similarly, a mask for covering all pixels other than the pixels corresponding to blue is set, and the EL layer and the cathode for emitting blue light are selectively formed using the mask. Note that all the masks are described herein as being different, but the same mask may be used again. EL is applied to all pixels.
Processing is preferably performed without breaking vacuum until a layer and a cathode are formed.

Here, a method of forming three kinds of EL elements corresponding to RGB is used. However, a method of combining a white light emitting EL element and a color filter, a blue or blue-green light emitting EL element and a phosphor (fluorescent And a method in which an EL element corresponding to RGB is stacked on a cathode (a counter electrode) using a transparent electrode.

Note that a known material can be used for the EL layer 5075. As a known material, it is preferable to use an organic material in consideration of a driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the EL layer. In this embodiment, E
An example using a MgAg electrode as the cathode of the L element is shown,
Other known materials may be used.

Next, a protective electrode 5077 is formed to cover the EL layer and the cathode. As the protective electrode 5077, a conductive film mainly containing aluminum may be used. The protective electrode 5077 may be formed by a vacuum evaporation method using a mask different from that used when the EL layer and the cathode are formed. After the EL layer and the cathode are formed, they are preferably formed continuously without being released to the atmosphere.

Finally, a passivation film 5078 made of a silicon nitride film is formed to a thickness of 300 [nm]. Although the protection electrode 5088 actually serves to protect the EL layer from moisture and the like, the reliability of the EL element can be further improved by forming the passivation film 5078 further.

Thus, an active matrix electronic device having a structure as shown in FIG. 6B is completed. In the manufacturing process of the active matrix type electronic device according to the present embodiment, a source signal line is formed by Ta and W which are materials forming a gate electrode, and a source and a drain are formed due to a circuit configuration and a process. Although the gate signal line is formed of Al which is a wiring material forming the electrode, a different material may be used.

By the way, the active matrix substrate of this embodiment exhibits extremely high reliability by arranging the TFT having the optimum structure not only in the pixel portion but also in the drive circuit portion, and the operating characteristics can be improved. In the crystallization step, N
It is also possible to increase the crystallinity by adding a metal catalyst such as i. Thus, the driving frequency of the source signal line driving circuit can be increased to 10 MHz or more.

First, a TFT having a structure in which hot carrier injection is reduced so as not to lower the operation speed as much as possible,
N-channel type TF of CMOS circuit forming drive circuit section
Used as T. In addition, as the drive circuit here,
It includes a shift register, a buffer, a level shifter, a latch in line-sequential driving, a transmission gate in point-sequential driving, and the like.

In the case of this embodiment, the active layer of the N-channel TFT is composed of a source region, a drain region, a GOLD region,
The GOLD region includes a DD region and a channel formation region, and overlaps with the gate electrode via a gate insulating film.

Also, a P-channel type TFT of a CMOS circuit
Since there is almost no concern about deterioration due to hot carrier injection, it is not necessary to provide an LDD region. Needless to say, it is also possible to provide an LDD region similarly to the N-channel type TFT and take measures against hot carriers.

In addition, in the case where a CMOS circuit in which a current flows bidirectionally through the channel forming region, that is, a CMOS circuit in which the roles of the source region and the drain region are exchanged is used in the driver circuit, N In the channel type TFT, it is preferable to form an LDD region on both sides of the channel formation region so as to sandwich the channel formation region. An example of such a transmission gate is a transmission gate used for dot-sequential driving. In the case where a CMOS circuit that requires an off-current value to be kept as low as possible is used in a driving circuit, a CMOS
The N-channel TFT forming a circuit preferably has a structure in which a part of an LDD region overlaps with a gate electrode through a gate insulating film. As such an example, a transmission gate used for dot-sequential driving is also mentioned.

When the structure shown in FIG. 6B is actually completed, the protective film (laminate film, ultraviolet curable resin film, etc.) having high airtightness and low degassing is used to prevent further exposure to the outside air. It is preferable to package (enclose) with an optical sealing material. At this time, the reliability of the EL element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

When the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting terminals routed from elements or circuits formed on the substrate to external signal terminals. To complete the product. Such a state in which the product can be shipped is referred to as an electronic device in this specification.

According to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the island-shaped semiconductor layer pattern, the first wiring pattern (the gate wiring, the island-shaped source wiring). , A capacitor wiring), a mask pattern of an n-channel region, a contact hole pattern, and a second wiring pattern (including a pixel electrode and a connection electrode). As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

[Embodiment 4] In this embodiment, an example in which an electronic device of the present invention is manufactured will be described.

FIG. 7A is a top view of an electronic device using the present invention, and FIG. 7B is a cross-sectional view of FIG. 7A taken along the XX ′ plane. In FIG. 7A, reference numeral 4001 denotes a substrate; 4002, a pixel portion; 4003, a source signal line side driver circuit; 4004, a gate signal line side driver circuit; the respective driving circuits are wirings 4005, 4006, and 4007;
Through the FPC 4008 to be connected to an external device.

At this time, in the pixel portion, it is preferable that the cover member 400 is formed so as to surround the driving circuit and the pixel portion.
9, a sealing material 4010, and a sealing material (also referred to as a housing material) 4011 (shown in FIG. 7B).

FIG. 7B shows a cross-sectional structure of the electronic device of this embodiment, in which a TFT for a driving circuit (here, an N-channel type TFT) is provided on a substrate 4001 and a base film 4012.
4013 and a TFT 4014 for a pixel portion.
(However, here, only the EL driving TFT for controlling the current to the EL element is shown). These TFTs may use a known structure (top gate structure or bottom gate structure).

A TFT for a driving circuit is manufactured by using a known manufacturing method.
4013, when the pixel portion TFT 4014 is completed, a pixel electrode 4016 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 4014 is formed on an interlayer insulating film (planarization film) 4015 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4016
Is formed, an insulating film 4017 is formed, and the pixel electrode 40 is formed.
An opening is formed on 16.

Next, an EL layer 4018 is formed. The EL layer 4018 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light emitting layer (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask,
Color display becomes possible. In addition, the color conversion layer (CC
There is a method combining M) and a color filter, and a method combining a white light emitting layer and a color filter, and any method may be used. Needless to say, the electronic device can emit light of a single color.

After forming the EL layer 4018, a cathode 4019 is formed thereon. Cathode 4019 and EL layer 4018
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4018 and the cathode 40
It is necessary to devise a method of continuously forming the film 19 or forming the EL layer 4018 in an inert atmosphere and forming the cathode 4019 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4019,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed on the EL layer 4018 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4019 is connected to the wiring 4007 in a region indicated by 4020. A wiring 4007 is a power supply line for applying a predetermined voltage to the cathode 4019,
It is connected to the FPC 4008 through the conductive paste material 4021.

In the region indicated by 4020, the cathode 40
In order to electrically connect the wiring 19 and the wiring 4007, it is necessary to form a contact hole in the interlayer insulating film 4015 and the insulating film 4017. These are interlayer insulating films 4015
May be formed at the time of etching (at the time of forming a contact hole for a pixel electrode) or at the time of etching of an insulating film 4017 (at the time of forming an opening before an EL layer is formed). When the insulating film 4017 is etched, etching may be performed all at once up to the interlayer insulating film 4015. In this case, if the interlayer insulating film 4015 and the insulating film 4017 are the same resin material, the shape of the contact hole can be made good.

The passivation film 4022 and the filler 402 cover the surface of the EL element thus formed.
3. A cover material 4009 is formed.

Furthermore, a sealing material 4 is placed inside the cover 4009 and the substrate 4001 so as to surround the EL element portion.
011 is provided, and a sealing material (second sealing material) 4010 is formed outside the sealing material 4011.

At this time, the filler 4023 also functions as an adhesive for bonding the cover member 4009.
As the filler 4023, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4023 because a moisture absorbing effect can be maintained. Further, by disposing an antioxidant or the like having an effect of capturing oxygen inside the filler 4023, deterioration of the EL layer may be suppressed.

Further, the filler 4023 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 4022 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 4009, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberga
ss-Reinforced Plastics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic film can be used. When PVB or EVA is used as the filler 4023, it is preferable to use a sheet having a structure in which aluminum foil of several tens [μm] is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 4009 needs to have translucency.

The wiring 4007 is made of a sealing material 401.
1 and the sealant 4010 and the substrate 4001, and electrically connected to the FPC 4008. Although the wiring 4007 has been described here, the other wiring 4007
5 and 4006 are also electrically connected to the FPC 4008 under the sealant 4011 and the sealant 4010 in the same manner.

In this embodiment, the sealing material 4011 is attached so as to cover the side surface (exposed surface) of the filling material 4023 after the filling material 4023 is provided and then the cover material 4009 is adhered. Lumber 4
After attaching 011, the filler 4023 may be provided. In this case, an inlet for a filler is provided to communicate with a space formed by the substrate 4001, the cover material 4009, and the sealing material 4011. Then, the gap is vacuumed (1
0 ^-2 [Torr] or less), fill the filling material into the water tank by immersing the injection port in the filling tank, and then make the pressure outside the gap higher than the pressure inside the gap. I do.

[Embodiment 5] FIG. 8 shows a more detailed sectional structure of a pixel portion in an electronic device of the present invention.

In FIG. 8, an N-channel TFT is used as a switching TFT 4502 provided on a substrate 4501 in this embodiment. In this embodiment, a double gate structure is used. However, since there is no significant difference between the structure and the manufacturing process, the description is omitted. However, there is an advantage that the double gate structure has a structure in which two TFTs are substantially connected in series, and the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, a P-channel TFT may be used.

Further, an N-channel TFT is used as the EL driving TFT 4503. Switching TFT4502
The drain wiring 4504 of FIG.
It is electrically connected to the gate electrode 4506 of the L driving TFT 4503.

By the way, the drive voltage of the electronic device is high (1
0 [V] or more), the TFT constituting the driving circuit is
In particular, since there is a high risk of deterioration due to hot carriers or the like in the N-channel type, as shown in FIG. 6B of the third embodiment, the N-channel type TFT has a drain side or both a source side and a drain side. A structure in which an LDD region (GOLD region) is provided at a position overlapping a gate electrode with a gate insulating film interposed therebetween is extremely effective. On the other hand, when the drive voltage is low (10 [V] or less), there is almost no concern about deterioration due to hot carriers, and therefore, there is no need to particularly provide a GOLD region as shown in FIG. 8 of this embodiment. However,
The switching TFT 4502 in the pixel portion has O
In order to keep the FF current low, on the drain side of the N-channel TFT, or on both the source side and the drain side,
L at a position that does not overlap with the gate electrode via the gate insulating film
The structure in which the DD region is provided is extremely effective. At this time,
As for the EL driving TFT 4503, there is no particular need to provide an LDD region.
When the LDD region is formed in the TFT 2, the EL driving TFT 45
A special mask is required to cover the portion 03 with the resist. Therefore, in this embodiment, in order to avoid an increase in the number of masks, the EL driving TFT 4503 is formed in the same structure (structure having an LDD region) as the switching TFT 4502.

Here, the T having the structure shown in this embodiment is
The FT creation process will be described. FIG. 9 is referred to for the description.

FIG. 9 (A) shows an example in which the processing up to the state shown in FIG. 4 (B) is completed according to the third embodiment. Through the steps so far, first impurity regions 4701 to 4705 are formed. Subsequently, the first conductive film made of a Ta film and the second conductive film made of a W film were etched as shown in FIG. 9B to form an island-shaped semiconductor layer in FIG. 9A. Inside the first impurity region, second impurity regions 4706 to 4711 having a lower concentration than the first impurity region are formed. The second impurity regions 4706 to 4711 formed here become the above-described LDD regions.

Thereafter, according to the third embodiment again, FIG.
(B) The active matrix substrate may be completed through the following steps.

In this embodiment, the EL driving TFT 45 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

The wiring (not shown) including the gate electrode 4506 of the EL driving TFT 4503 is
The drain wiring 4512 of the FT 4503 partially overlaps with an insulating film interposed therebetween, and a storage capacitor is formed in that region. This storage capacitor is connected to the gate electrode 4 of the EL driving TFT 4503.
A function of holding a voltage applied to the 506.

Switching TFT 4502 and EL
A first interlayer insulating film 451 is formed on the driving TFT 4503.
4 is provided thereon, and a second interlayer insulating film 4515 made of a resin insulating film is formed thereon.

Reference numeral 4517 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
03 is formed so as to partially cover the drain region, and is electrically connected. As the pixel electrode 4517, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

Next, an organic resin film 4516 is formed on the pixel electrode 451.
7 and patterning a portion facing the pixel electrode 4517, an EL layer 4519 is formed. Although not shown here, R (red), G (green), B (blue)
The light-emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.

Although there are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, OG”
elsen, E. Kluge, W. Kreuder and H. Spreitzer: “Polym
ersfor Light Emitting Diodes ”, Euro Display, Procee
dings, 1999, pp. 33-37 ”and JP-A-10-92576.

As specific light-emitting layers, cyanopolyphenylenevinylene is used for a red light-emitting layer, polyphenylenevinylene is used for a green light-emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light-emitting layer. Good. The film thickness is 30 to 150
[Nm] (preferably 40 to 100 [nm]).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this example. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

The EL element 4510 is completed when the anode 4523 is formed. Note that the EL element 45 here is used.
Reference numeral 10 denotes a pixel electrode (cathode) 4517 and a light emitting layer 451
9 and the storage capacitor formed by the hole injection layer 4522 and the anode 4523.

In this embodiment, a passivation film 4524 is further provided on the anode 4523.
As the passivation film 4524, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. This increases the reliability of the electronic device.

As described above, the electronic device described in this embodiment has a pixel portion composed of pixels having a structure as shown in FIG. 8, and a switching TFT having a sufficiently low off-current value.
And an EL driving TFT resistant to hot carrier injection. Therefore, an electronic device having high reliability and capable of displaying an excellent image can be obtained.

E having the structure described in this embodiment is
In the case of the L element, light generated in the light emitting layer 4519 is radiated in a direction opposite to the substrate on which the TFT is formed as indicated by an arrow.

[Embodiment 6] In this embodiment, Embodiment 5 will be described.
In the pixel portion shown in FIG. 8, a structure obtained by inverting the structure of the EL element 4510 will be described. Figure 10 for explanation
Is used. It should be noted that the only difference from the structure of FIG. 8 is the EL element portion and the TFT portion, and the other description will be omitted.

In FIG. 10, the switching TFT 4
Reference numeral 502 denotes an N-channel TFT formed by the method described in the fifth embodiment. As the EL driving TFT 4503, a P-channel TFT formed by a known method is used. Here, the switching TFT and the EL driving TFT are:
It is desirable to use one having the same polarity.

In this embodiment, the pixel electrode (anode) 4525
Is used as a transparent conductive film. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the third interlayer insulating film 4 made of a resin film
After 526 is formed, a light emitting layer 4528 is formed.
On top of this, potassium acetylacetonate (acacK
) And a cathode 4530 made of an aluminum alloy.

Thereafter, as in the fifth embodiment, a passivation film 4532 for preventing the oxidation of the organic EL material is formed, and thus the EL element 4531 is formed.

E having the structure described in this embodiment
In the case of the L element, light generated in the light emitting layer 4528 is emitted toward the substrate on which the TFT is formed, as indicated by an arrow.

[Embodiment 7] In order to implement the driving method of the present invention, as shown in FIG.
1 needs to be placed. In such a structure, FIG.
Since the number of wirings is increased as compared with a pixel portion having a structure in which one terminal of the storage capacitor 1604 is connected to the current supply line 1607 as shown in (1), the aperture ratio is disadvantageous. Therefore, in this embodiment, an example in which the driving method of the present invention is performed using a pixel having a structure in which the number of wirings in the pixel portion is reduced by sharing a current supply line with a gate signal line will be described. It should be noted that a pixel having a common structure of a current supply line and a gate signal line, which is described in the present embodiment, is disclosed in Japanese Patent Application 2000
The one described in JP-087683 is used.

Referring to FIG. FIG. 11 shows an example of a circuit configuration for implementing the driving method of the present invention using a pixel having a common structure of a current supply line and a gate signal line. A pixel portion 1154 is provided in the center of the substrate 1150. A source signal line side driver circuit 1151 is provided above the pixel portion 1154. A gate signal line side driver circuit 1151152 is provided on the left side of the pixel portion 1154. On the right side of the pixel portion, a storage capacitor line driving circuit 115
3 are arranged. FIG. 11B is a circuit diagram of one pixel. 1101 is a switching TFT, 11
02 is an EL driving TFT, 1103 is an EL element, 110
4 is a storage capacitor, 1105 is a gate signal line, 1106 is a gate signal line one row before the gate signal line 1105, 1107
Denotes a source signal line, and 1108 denotes a storage capacitor line.

The structural feature is that the EL driving TFT 110
One of the two source regions and the drain region is connected to the gate signal line 1106 in the previous row. In FIG. 110B, the gate signal line 1106 is k−1
Assuming that the row and gate signal line 1105 are scanned on the k-th row, the gate signal line 1106 on the (k-1) -th row is scanned first. Scanning is performed, and during scanning of the gate signal line 1105 in the k-th row, the gate signal line 110
In 6, the scanning has already been completed and the potential is constant. Focusing on this point, supply of current to the EL element 1103 controlled by the gate signal line 1105 in the k-th row is performed using the gate signal line 1106 in the (k-1) -th row.

By the way, the EL driving TFT 1102 is
Either an N-channel type or a P-channel type may be used. However, as described above, considering the good source ground and the structural restrictions of the EL element,
It is desirable to use a channel type. In this embodiment, E
The description will be made assuming that the TFT 1102 for L driving uses a P-channel type.

Although the reason will be described later, the switching TFT 1101 is, in this case, an EL driving TFT 1102.
It is necessary to use a TFT having the same polarity as that of.

Hereinafter, the actual driving will be described.
FIGS. 12 and 13 show timing charts. The example is a display of a 3-bit gradation, and a sustain (lighting) period Ts ₃
Is shorter than the address (write) period. Although there is a difference in the structure of the pixel portion between the circuit of the first embodiment and the circuit of the present embodiment, in order to avoid duplication of the address (write) period, the potential of the storage capacitor line 1108 is raised to increase the clear period (clear). In other words, the driving as described in the first embodiment can be performed by providing a period. The gate signal line 1106 in the (k-1) th row has a constant potential after the end of the selection period,
Until the next selection period comes, current is supplied to the EL element 1103 controlled by the gate signal line 1105 in the k-th row.

Here, the polarity of the above TFT will be described. Previously, it was stated that the switching TFT 1101 and the EL driving TFT 1102 need to have the same polarity. That is, in the case of this embodiment, the EL driving TFT 11
02 uses a P-channel type, which means that the switching TFT 1101 also needs to be a P-channel type. Assuming that the switching TFT 1101 is of an N-channel type here, the switching TFT 1101 needs to be turned on by a switching TF
A Hi signal must be input to the gate electrode of T1101. That is, the gate signal lines 1105 and 1106
Becomes Hi potential in the selected state and LO potential in the non-selected state. Since the EL driving TFT 1102 is a P-channel type, in order to supply a current to the EL element
The EL driving TFT 110 is more than the anode 1110 of the L element.
2, that is, the potential of the gate signal line 1106 must be high. So, as mentioned above,
When the switching TFT 1101 is an N-channel type,
In the method of setting the potential of the gate signal line to drive it, since the LO potential is set in the non-selection period, it becomes impossible to supply current to the EL element 1103. Therefore, when the EL driving TFT 1102 is a P-channel type,
The switching TFT 1101 also needs to be a P-channel type.

In the circuit configuration of this embodiment, the E of the pixel controlled by the gate signal line 1105 in the k-th row is used.
The current is supplied to the L element 1103 by connecting to the gate signal line 1106 in the (k-1) th row. However, any gate signal line in a non-selected state can be used. Similar driving is possible. In consideration of the case where the signal waveform of the gate signal line is distorted, it is desirable to supply the current not by the adjacent gate signal lines but by the gate signal lines separated by at least one column. Since an increase in the number of wirings causes a decrease in the aperture ratio, the best method can be selected depending on the circuit configuration, the characteristics of the TFT element, and the like.

[Embodiment 8] In the present invention, the storage capacitor line drive circuit for controlling the potential of the storage capacitor line has a configuration in which an independent circuit is arranged in the example of Embodiment 1, but FIG.
As shown in (A), the circuit may be configured as one circuit. Incidentally, it is desirable to arrange the gate signal line side driving circuits on both sides of the pixel portion in terms of driving. Therefore, as shown in FIG. 21B, the gate signal line side driving circuit and the storage capacitor line driving circuit may be formed as one circuit, and may be arranged on both sides.

[Embodiment 9] In the present invention, by using an EL material capable of utilizing phosphorescence from triplet excitons for light emission, external light emission quantum efficiency can be remarkably improved. As a result, the power consumption and the life of the EL element can be reduced,
And weight reduction becomes possible.

Here, a report is shown in which the triplet exciton is used to improve the external emission quantum efficiency. (T.Tsutsui, C.Ada
chi, S. Saito, Photochemical Processes in Organized
Molecular Systems, ed.K.Honda, (Elsevier Sci.Pu
b., Tokyo, 1991) p.437.) The molecular formula of the EL material (coumarin dye) reported in the above article is shown below.

[0164]

Embedded image

(MABaldo, DFO'Brien, Y. You, A. Sho
ustikov, S. Sibley, METhompson, SRForrest, Natu
re 395 (1998) p.151.) The molecular formula of the EL material (Pt complex) reported by the above paper is shown below.

[0166]

Embedded image

(MABaldo, S. Lamansky, PEBurrrows,
METhompson, SRForrest, Appl.Phys.Lett., 75 (19
99) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Wa
tanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguch
i, Jpn. Appl. Phys., 38 (12B) (1999) L1502.) The molecular formula of the EL material (Ir complex) reported by the above-mentioned paper is shown below.

[0168]

Embedded image

As described above, if the phosphorescence emission from the triplet exciton can be used, it is possible in principle to realize an external light emission quantum efficiency three to four times higher than the case where the fluorescence emission from the singlet exciton is used. . Note that the configuration of this embodiment is the same as that of Embodiments 1 to
Any of the configurations of the eighth embodiment can be freely combined and implemented.

[Embodiment 10] An EL display to which the method of driving an electronic device according to the present invention is applied is a self-luminous type, so that it has better visibility in a bright place than a liquid crystal display.
Moreover, the viewing angle is wide. Therefore, it can be used as a display portion of various electronic devices. For example, to watch a TV broadcast or the like on a large screen, the diagonal is 30 inches or more (typically 40 inches or more).
It is preferable to use the method for driving an electronic device of the present invention in a display portion of an EL display of inches or more.

The EL display includes all information display devices such as a personal computer display device, a TV broadcast reception display device, and an advertisement display device. In addition, the electronic device driving method of the present invention can be used for display portions of various electronic devices.

Such electronic devices of the present invention include a video camera, a digital camera, a goggle type display device (head mounted display), a navigation system,
Sound playback devices (car audio, audio components, etc.), notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), and an image reproducing apparatus provided with a recording medium (specifically, a digital video disc (DV
D) and the like, a device having a display capable of reproducing a recording medium and displaying its image). In particular, for a portable information terminal that is often viewed from an oblique direction, a wide viewing angle is regarded as important, and it is desirable to use an EL display. FIGS. 22 and 23 show specific examples of these electronic devices.
Shown in

FIG. 22A shows an EL display.
A housing 3301, a support 3302, a display portion 3303, and the like are included. The electronic device and the driving method of the invention can be applied to the display portion 3303.
Can be used. Since the EL display is a self-luminous type, it does not require a backlight and can be a display portion thinner than a liquid crystal display.

FIG. 22B shows a video camera, which includes a main body 3311, a display section 3312, an audio input section 3313, operation switches 3314, a battery 3315, and an image receiving section 331.
6 and so on. The electronic device and the driving method of the invention can be used in the display portion 3312.

FIG. 22C shows a part (one side on the right) of the head mounted EL display, which includes a main body 3321, a signal cable 3322, a head fixing band 3323, and a display section 33.
24, an optical system 3325, a display device 3326, and the like. The electronic device and the driving method of the invention can be used in the display device 3326.

FIG. 22D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD, etc.) 3332, operation switch 33
33, a display unit (a) 3334, a display unit (b) 3335, and the like. The display unit (a) 3334 mainly displays image information, and the display unit (b) 3335 mainly displays character information. The electronic device and the driving method of the present invention employ the display unit (a) 3334 and the display unit (b). ) 3335. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 22E shows a goggle type display device (head mounted display), which includes a main body 3341, a display portion 3342, and an arm portion 3343. The electronic device and the driving method of the invention can be used in the display portion 3342.

FIG. 22F shows a personal computer, which includes a main body 3351, a housing 3352, a display portion 3353,
A keyboard 3354 and the like. The electronic device and the driving method of the invention can be used in the display portion 3353.

If the emission luminance of the EL material becomes high in the future, it becomes possible to enlarge and project the light containing the output image information with a lens or the like and use it for a front type or rear type projector.

[0180] The electronic device may be the Internet or C.
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is very high, the EL display is preferable for displaying moving images.

In an EL display, a light-emitting portion consumes power. Therefore, it is desirable to display information so that the light-emitting portion is reduced as much as possible for power saving. Therefore, when an EL display is used for a portable information terminal, particularly a display unit mainly for character information such as a mobile phone or a sound reproducing device, the display is driven so that character information is formed by a light emitting portion with a non-light emitting portion as a background. It is desirable to do.

FIG. 23 (A) shows a mobile phone,
01, audio output unit 3402, audio input unit 3403, display unit 3404, operation switch 3405, antenna 3406
including. The electronic device and the driving method of the present invention employ the display unit 34.
04. Note that the display portion 3404 can reduce power consumption of the mobile phone by displaying white characters on a black background.

FIG. 23B shows an audio reproducing apparatus, specifically, a car audio system.
2. Including operation switches 3413 and 3414. The electronic device and the driving method of the invention can be used in the display portion 3412. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus.
Note that the display portion 3414 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable sound reproducing device.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. In addition, any of the configurations shown in the first to ninth embodiments may be applied to the electronic apparatus of the present embodiment.

【The invention's effect】

The effect of the present invention will be described. First, according to the present invention, even during a period when a signal is input to the pixels in a certain row,
The pixels in another row can be set to the non-display state. Thereby, the address (write) is written in the pixels of each row.
Since a sustain (lighting) period shorter than the period can be freely set, multiple gradations can be realized.

In the driving method of the present invention, the EL
Since the operation of hiding the element is performed by changing the potential of the storage capacitor line, a constant potential is always applied to the cathode wiring. Since the signal is not a pulse signal as in the related art, various problems caused by the rounding of the voltage waveform of the cathode ray can be avoided.

Further, in the configuration of the pixel portion, it is not necessary to newly add a transistor, a capacitor, a wiring, and the like. for that reason,
The image quality can be improved without lowering the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a timing chart illustrating a driving method according to the present invention described in a first embodiment.

FIG. 2 is a timing chart illustrating a driving method according to the present invention described in the first embodiment.

FIG. 3 is a timing chart illustrating a driving method according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a manufacturing process of an electronic device described in Embodiment 3.

FIG. 5 is a diagram illustrating an example of a manufacturing process of an electronic device described in Embodiment 3.

FIG. 6 is a diagram illustrating an example of a manufacturing process of an electronic device described in Embodiment 3.

FIGS. 7A and 7B are a top view and a cross-sectional view of an electronic device described in Embodiment 4. FIGS.

FIG. 8 is a cross-sectional view of a pixel portion of an electronic device described in Embodiment 5.

FIG. 9 is a diagram illustrating an example of a manufacturing process of an electronic device described in Embodiment 5.

FIG. 10 is a cross-sectional view of a pixel portion of an electronic device described in Embodiment 6.

FIG. 11 is a circuit configuration example of an electronic device according to a seventh embodiment.

FIG. 12 is a timing chart illustrating a driving method according to the present invention described in a seventh embodiment.

FIG. 13 is a timing chart illustrating a driving method according to the present invention described in a seventh embodiment.

FIG. 14 is a circuit configuration example of an electronic device.

FIG. 15 is a timing chart illustrating division of a frame period in a time gray scale.

FIG. 16 is a circuit configuration example of an electronic device.

FIG. 17 is a circuit configuration example of an electronic device.

FIG. 18 is a diagram illustrating a signal potential of each unit in the driving method of the present invention.

FIG. 19 is a diagram for explaining signal potentials at various parts in the driving method of the present invention.

FIG. 20 is a circuit configuration example of the electronic device described in Embodiment 1.

FIG. 21 is a circuit configuration example of an electronic device described in Embodiment 8;

FIG. 22 illustrates an example of an electronic device to which the method for driving an electronic device of the present invention described in Embodiment 10 is applied.

FIG. 23 illustrates an example of an electronic device to which the method for driving an electronic device of the present invention described in Embodiment 10 is applied.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641E 680 680A 680P 680S 680V H05B 33/14 H05B 33/14 A F term ( Reference) 3K007 AB05 BA06 CA03 CB01 DA02 EB00 5C080 AA06 BB05 EE29 FF11 JJ02 JJ04 JJ06 KK01 KK20 KK43 KK47 5C094 AA21 BA03 BA27 CA19 CA24 EA04 EA05 EA07 EB05

Claims (26)

[Claims] 1. One frame period has n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, a sustain (lighting) periods Ts _1, Ts _2, in the driving method of an electronic device having a ... Ts _n, at least one subframe of the n subframe periods in the period, having a duration of the sustain (lighting) period and the address (writing) periods are overlapping, the address (writing) period Ta _m in the sub-frame period _{SF m (1 ≦ m ≦ n} ), sub If the address in the frame period SF m _{+ 1} and (writing) period Ta m _{+ 1} overlap, after the completion of the sustain (lighting) period SF _m in the sub-frame period SF _m, the address (writing Method of driving an electronic device characterized by having a period Ta m _{+ 1} of clear period Tc _m in the period leading up to the start. 2. One frame period has n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, a sustain (lighting) periods Ts _1, Ts _2, in the driving method of an electronic device having a ... Ts _n, at least one subframe of the n subframe periods in the period, having a duration of the sustain (lighting) period and the address (writing) periods are overlapping, j (0 <j) th frame of the sub-frame periods addresses in SF _n (writing) and duration Ta _n , j + 1 when the frame of the address in the sub-frame periods SF ₁ and (writing) period Ta ₁ overlap, sustain (lighting) of the j-th frame of the sub-frame period SF _n periods SF After _n the end, the driving method of an electronic device characterized by having the j + 1 th frame address in the sub-frame periods SF ₁ (writing) period the clear period to the start of the period Ta ₁ Tc _n. 3. One frame period has n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, the sustain (lighting) periods _{Ts 1, Ts 2, ··· Ts} n and the method of driving an electronic device having a certain subframe period _{SF k (1 ≦ k ≦ n} ),
Address (writing) the length ta _k periods, as a sustain (lighting) the length ts _k of period 1 the length of the gate signal line selection period _{t g (ta k, ts k} , t g> 0), ta _k
When> ts _k is satisfied, the length of the clear period of SF _k is defined as tc _k (tc _k > 0)
When, _{always, tc k ≧ ta k - (} ts k + t g) method of driving an electronic device, characterized in that is established. 4. The method for driving an electronic device according to claim 1, wherein the clear signal input in the clear period is based on a signal input from a storage capacitor line driving circuit. A method for driving an electronic device, which is provided by increasing the potential of a storage capacitor line or decreasing the potential of a storage capacitor line. 5. The method for driving an electronic device according to claim 4, wherein the electroluminescent element is turned off regardless of an image signal during the clearing period. 6. A source signal line side drive circuit, a gate signal line side drive circuit, a storage capacitor line drive circuit, and a pixel portion, wherein the pixel portion has a plurality of source signal lines and a plurality of gates. A signal line, a plurality of current supply lines, a plurality of storage capacitor lines, and a plurality of pixels, each of the plurality of pixels including a switching transistor, an electroluminescence driving transistor, a storage capacitor, A luminescence element, a gate electrode of the switching transistor is electrically connected to a gate signal line, and one of a source region and a drain region of the switching transistor is electrically connected to a source signal line; The other one is electrically connected to a gate electrode of the electroluminescence driving transistor, and the storage capacitor is one electrode The other electrode is electrically connected to the storage capacitor line, and the other electrode is electrically connected to a gate electrode of the electroluminescence driving transistor. One of a source region and a drain region of the electroluminescence driving transistor has a current supply. An electronic device, wherein the electronic device is electrically connected to a line and the other is electrically connected to one electrode of the electroluminescence element. 7. The electronic device according to claim 6, wherein the storage capacitor line is electrically connected to the storage capacitor line drive circuit, and a signal having an amplitude is input from the storage capacitor line drive circuit. An electronic device, comprising: 8. One frame period has n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , wherein the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, a sustain (lighting) periods Ts _1, Ts _2, and a ... Ts _n, at least one sub-frame period among the n sub-frame periods, the address It has a period in which the a (writing) period sustain (lighting) periods are overlapping, the address (writing) period Ta _m in the sub-frame period _{SF m (1 ≦ m ≦ n} ), the sub-frame period SF m ₊ If the address (writing) period Ta m _{+ 1} at ₁ overlap, after the completion of the sustain (lighting) period SF _m in the sub-frame period SF _m, the start of the address (writing) period Ta m _{+ 1} Until Electronic device characterized in that it operates by a driving method having a clear period Tc _m. 9. One frame period has n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , and the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, a sustain (lighting) periods Ts _1, Ts _2, and a ... Ts _n, at least one sub-frame period among the n sub-frame periods, the address It has a period in which the a (writing) period sustain (lighting) periods are overlapping, j (0 <j) th frame of the sub-frame periods addresses in SF _n and (writing) period Ta _n, j + 1 th frame If the address in the sub-frame periods SF ₁ and (writing) period Ta ₁ overlap, sustain at j th frame of the sub-frame period SF _n (lit) after the end of the period SF _n, the j + 1 frame Electronic device characterized in that it operates by a driving method having a clear period Tc _n in the period leading up to the start address (writing) period Ta ₁ in the eyes of the subframe periods SF _1. 10. One frame period includes n sub-frame periods SF ₁ , SF ₂ ,..., SF _n , wherein the n sub-frame periods are address (write) periods Ta ₁ , Ta _{2, respectively.} , ..., and Ta _n, a sustain (lighting) periods Ts _1, Ts _2, and a ... Ts _n, at subframe period _{SF k (1 ≦ k ≦ n} ),
Address (writing) the length ta _k periods, as a sustain (lighting) the length ts _k of period 1 the length of the gate signal line selection period _{t g (ta k, ts k} , t g> 0), ta _k
When> ts _k is satisfied, the length of the clear period of SF _k is defined as tc _k (tc _k > 0)
When, _{always, tc k ≧ ta k - (} ts k + t g) electronic apparatus characterized by holds. 11. The electronic device according to claim 8, wherein the clear signal input in the clear period is a storage capacitor line in response to a signal input from a storage capacitor line driving circuit. The electronic device is provided by increasing the potential of the storage capacitor line or decreasing the potential of the storage capacitor line. 12. The electronic device according to claim 11, wherein the electroluminescent element is turned off during the clear period regardless of an image signal. 13. An electroluminescent display using the method for driving an electronic device according to claim 1. Description: 14. A video camera using the method for driving an electronic device according to claim 1. Description: 15. A head mounted display using the method for driving an electronic device according to claim 1. Description: 16. A driving method for an electronic device according to claim 1, wherein the driving method comprises the steps of:
VD player. 17. A personal computer using the method of driving an electronic device according to claim 1. Description: 18. A mobile phone using the method for driving an electronic device according to claim 1. Description: 19. A car audio using the method for driving an electronic device according to claim 1. Description: 20. An electroluminescent display using the electronic device according to claim 6. Description: 21. A video camera using the electronic device according to any one of claims 6 to 12. 22. A head mounted display using the electronic device according to claim 6. Description: 23. A DVD player using the electronic device according to claim 6. Description: 24. A personal computer using the electronic device according to claim 6. Description: 25. A mobile phone using the electronic device according to claim 6. Description: 26. A car audio using the electronic device according to any one of claims 6 to 12.