JP2001350674A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of preventing access to a PCI(protocol control information) device reset hardware-wise and not set with configuration information and suppressing the occurrence of multiple failures. SOLUTION: This computer system is provided with a device management table 9 retaining the status data of an IO(input-output) device 7 provided in a computer body 1 and in a PCI extended box 2, a RAS processing section 8 conducting error processing in reference to the device management table 9 when receiving an error interrupt signal (a), a determining means 8a determining whether the PCI extended box 2 is reset or not when an abnormality occurs on the PCI device. If the PCI extended box 2 is determined to be reset, the RAS processing section 8 conducts specific error processing on the I/O devices 7b and 7c in the PCI extended box 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly, to a PC to which power is supplied separately from a computer main body.
The present invention relates to a computer system to which an I expansion bus (hereinafter, referred to as a PCI expansion box) is connected.

[0002]

2. Description of the Related Art In a computer system to which a PCI bus, which is a general-purpose I / O bus, is connected, when a PCI error interrupt notification is received, a failed input / output I / O device or bridge is specified and appropriate error processing is performed. R that implements
The OS includes an AS processing unit.

FIG. 17 shows, for example, Japanese Patent Application Laid-Open No. HEI 24/723.
FIG. 4 is a block diagram illustrating a configuration of a conventional computer system having a RAS processing unit disclosed in Japanese Patent Application Publication No. 4 (JP-A) No. 4 (1999). FIGS. 18 and 19 are flowcharts showing the operation of the RAS unit and the device driver provided in the conventional computer system of FIG. 17, respectively. 17, 001 is a computer system, and 008a, 008b, and 008c are host bus 005 and host bridge 00 of the computer system 001.
6, an input / output I / O device 002 existing on a PCI bus 007 connected via
a, a 008b, and 008c, which are RAS processing units that receive an error interrupt signal a and perform appropriate error processing.
Reference numeral 003 denotes a device management table for recording the status of each input / output I / O device 008.
A device ID 003a for identifying the device 008 and status data 003b indicating the status are held. 004a, 0
04b and 004c denote device drivers for operating each input / output I / O device 008.

Next, the contents of error processing performed by a conventional RAS processing unit will be described with reference to a flowchart shown in FIG. When a failure occurs in the input / output I / O device 008, the RAS processing unit 002 receives the error interrupt notification notified to the RAS processing unit 002 by the error interrupt signal a.
First, an input / output I / O device 008 in which a failure has occurred is specified (step A1), and the process is changed depending on whether the device has been specified (step A2). If the device could not be specified, the failed input / output I / O device 008
Is notified (step A4), and the process ends. If the device can be specified, the status data 003b of the corresponding device in the device management table 003 is changed to NG (step A3), and the process ends.

Next, the operation of the device driver 004 which operates asynchronously with the flowchart of the RAS processing section 002 will be described with reference to the flowchart shown in FIG.
Upon receiving the I / O request (step A5), the device driver 004 issues the I / O request to the input / output I / O
The device status 003b of the device management table 003 corresponding to the device 008 is referred to (step A6) and confirmed (step A7). At this time, the state 003b of the device changes to O
If it is K, the input / output processing is performed as it is (step A
8) If NG, the input / output processing is interrupted (step A).
9) By doing so, the failed input / output I / O device 00
8 can be avoided.

[0006]

In a computer system to which a PCI expansion box to which power is supplied separately from the computer main body is connected, the power of the PCI expansion box is momentarily stopped and only the PCI expansion box is H / W ( Hardware) reset (PCI bus initialization), or the power supply of the PCI expansion box is cut off for some reason,
Conventional RAS processing unit 0 in which the problem of not returning occurs
In the error processing of 02, only the handling of a failure occurring in the input / output I / O device 008 is considered, and the processing when the PCI expansion box is reset or when the power supply to the PCI expansion box is cut off is considered. I didn't.
Therefore, when the power of the PCI expansion box is reset or the power is cut off, the RAS processing unit 002
In the error processing for identifying the failed input / output I / O device 008 performed in step 2, an access is made to a PCI device that has been reset and the configuration information has not been initialized,
There has been a problem that multiple failures (errors occurred during error processing) may occur, for example, by accessing a configuration space that has become inaccessible from S.
Although the processing when multiple failures occur is not described, a method of forcibly stopping the system may be employed. Another problem is that error processing cannot be performed in accordance with the importance of the input / output I / O devices arranged in the PCI expansion box.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and prevents access to a PCI device which has been reset in a hardware manner and has no configuration information set, thereby preventing the occurrence of multiple failures. The purpose is to obtain a computer system that can be suppressed.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a computer system to which a PCI expansion box to which power is supplied separately from a computer main body is connected.
One or more input / output I / O devices provided in the I expansion box, a device management table for holding status data of each input / output I / O device, and an error interrupt notification from one of the input / output I / O devices Input / output I / O
An error processing unit for specifying an apparatus and performing error processing with reference to the device management table, and resetting the PCI expansion box when an error occurs in the PCI expansion box or an input / output I / O device in the PCI expansion box. Determination means for determining whether or not the operation has been performed.
An error processing unit is a computer system that performs a specific error process on all input / output I / O devices provided in the PCI expansion box when it is determined that the CI expansion box has been reset.

When it is determined that the PCI expansion box has been reset, a degenerate operation process is performed as a specific error process.

[0010] The determination means performs the determination asynchronously with the actual I / O request to the input / output I / O device.

In addition, the power supply apparatus further includes a power-off detection unit that detects that power supply to the PCI expansion box has been interrupted, and notifies the error processing unit of the power supply abnormality.

When it is determined that the PCI expansion box has been reset, a shutdown process is performed as a specific error process.

Also, a system initialization ROM that operates first when the computer system is started up, and a configuration that records configuration information set for the input / output 1 / O device in the PCI expansion box by the system initialization ROM. Further comprising information recording means,
When it is determined that the PCI expansion box has been reset, the configuration information is reset for each input / output I / O device in the PCI expansion box as specific error processing.

An upper limit is set for the number of times the configuration information is reset.

Further, there is further provided an error processing switching means for selecting the contents of a specific error processing to be executed by the error processing means.

When a plurality of PCI expansion boxes are connected, the system further comprises error processing definition means for setting specific error processing contents for each PCI expansion box.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a configuration of a computer system according to a first embodiment of the present invention. In FIG. 1, 1 is a computer system, 2 is a PCI expansion box, and the computer system 1 and the PCI expansion box 2 are respectively Separate power supplies 3a and 3b are supplied. The host bus 4 provided in the computer system 1 includes:
It is connected to a PCI expansion bus 5 provided in the PCI expansion box 2 via a host bridge 6. 7a,
Reference numerals 7b and 7c denote input / output I / O devices. The input / output I / O device 7a exists on the host bus 4, and the input / output I / O device 7
b and 7c exist on the PCI expansion box 2. Reference numeral 8 denotes a RAS processing unit that receives a PCI error interrupt notification from the input / output I / O devices 7a, 7b, 7c and executes appropriate processing.
Reference numeral a denotes a degenerated operation processing unit that performs a degenerate operation as error processing. Reference numeral 9 denotes a device management table for recording the status of the input / output I / O device 7, an item 9 a storing data for identifying each input / output I / O device 7, and an input / output I / O device 7.
An item 9b indicating the position on the bus where the O device 7 exists; an item 9c for recording a number for identifying a process or thread requesting I / O to the I / O device 7; Item 9d indicating the state of the / O device 7.
Since the initialization of the device management table is information that can be obtained in the process of configuring the computer system according to the PCI rules when the computer system is started, it is assumed here that the device management is ready.

Next, the processing flow will be described with reference to FIG.
A number for identifying a process or a thread that issues an I / O request to the input / output I / O device 7 is registered in the item 9c of the device management table 9 (step S1). If an error occurs in the PCI device 7b, 7c or the PCI bus 5 while an I / O request is being made to the input / output I / O device 7,
The RAS processing unit 8 is notified by the error notification interrupt signal a (step S2). Upon receiving the error notification interrupt signal a, the RAS processing unit 8 first determines whether or not the PCI expansion box 2 has been reset, by determining whether or not the configuration space of the host bridge 6 has been reinitialized H / W. And the process branches (step S3). If it is determined that the PCI expansion box 2 has been reset, the process requesting the I / O I / O devices 7b and 7c of the PCI expansion box 2 by referring to the item 9c of the device management table 9 Alternatively, the thread is stopped, and the item 9d of the device management table 9 corresponding to the input / output I / O devices 7b and 7c on the PCI expansion box 2 is changed to NG (step S4a).
As a result, the degenerate operation (step S
Perform 5). If it is determined that the PCI expansion box 2 has not been reset, the same processing as that of the RAS processing unit of the conventional example is performed. That is, the PCI devices 7b,
The input / output I / O device 7 in which the failure has occurred is identified by sequentially examining the status on the 7c. Thereafter, by referring to the item 9c of the device management table 9 corresponding to the input / output 1 / O device 7 in which the failure has occurred, the process or the I / O request to the input / output 1 / O device 7 in which the error has occurred or The thread is stopped, the item 9d of the corresponding device management table 9 is changed to NG (step S4b), and the degenerate operation (step S5) is performed.

As described above, in the present embodiment,
The RAS processing unit refers to the configuration space,
Since it is determined whether or not the PCI expansion box has been reset, if the PCI expansion box has been reset, in the processing for specifying the failed I / O device performed by the RAS processing unit, H / W It is possible to prevent an access to the initialized PCI device from occurring, and to prevent multiple failures from occurring.

Embodiment 2 FIG. 3 is a block diagram showing the configuration of the computer system according to the second embodiment of the present invention. In the figure, the same components as those of the first embodiment shown in FIG. Is attached. In the figure, reference numeral 10 denotes a PC asynchronous with an I / O request to the input / output I / O device 7 arranged in the PCI expansion box 2.
A periodic check means for determining whether or not the I extension box 2 has been reset at a predetermined constant cycle is shown. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG. When the periodic check unit 10 is activated, the information of the configuration space of the host bridge 6 is used to determine P
It is determined whether or not the CI extension box 2 has been reset, and the process branches (step S10). If the PCI expansion box 2 has not been reset, after sleeping for a predetermined period of time (step S11), step S10 is performed again.
Is performed. If it is determined in step S10 that the PCI expansion box 2 has been reset, the RAS processing unit 8 is notified that the PCI expansion box has been reset (step S12). In the RAS processing unit 8 notified that the PCI expansion box 2 has been reset, the RAS processing unit 8 shown in FIG.
As shown in the flowchart of (b), if there is a process or thread requesting I / O in the input / output I / O devices 7b and 7c in the PCI expansion box 2, the operation is stopped (step S4a). Further, by changing the item 9d of the device management table 9 of the corresponding input / output I / O device 7 to NG (step S4a), the degeneration processing is performed (step S5).

As described above, in the present embodiment,
By adding a periodic check means 10 for determining at regular intervals whether or not the PCI expansion box has been reset,
There is an effect that it is possible to know whether or not the PCI expansion box has been reset asynchronously with an I / O request to an input / output I / O device in the CI expansion box.

Embodiment 3 FIG. FIG. 5 is a block diagram showing a configuration of a computer system according to the third embodiment of the present invention. In the figure, the same components as those in the above embodiment are denoted by the same reference numerals. In the figure, 11 is
A power-off detection unit that monitors the power supply 3b of the PCI expansion box 2 and notifies the RAS processing unit 8 when power supply is interrupted is shown. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG.
In the flowchart of FIG. 6, steps for performing the same processing as in the above-described embodiment are denoted by the same step numbers, and detailed description thereof will be omitted. As shown in FIG. 6A, the power-off detecting means 11 detects that the power supply to the PCI expansion box 2 has been interrupted (step S2).
1) Then, the RAS processing unit 8 is notified that a power failure has occurred (step S22). As shown in FIG. 6B, the RAS processing unit 8 notified of the power-off of the PCI expansion box 2 from the power-off detection unit 11 sends the I / O devices 7b and 7c on the PCI expansion box 2 to the I / O devices 7b and 7c. If there is a process or thread requesting / O, it stops.
Further, by changing the item 9d of the device management table 9 of the corresponding input / output I / O device to NG (step S4a), the degenerate operation is performed (step S5).

As described above, in the present embodiment,
By adding a power-off detection unit that notifies the RAS processing unit when the power-off of the PCI expansion box occurs,
When the power supply to the expansion box is interrupted, the effect is obtained that the degraded operation becomes possible without accessing the configuration space that cannot be referenced from the OS.

Embodiment 4 FIG. 7 is a block diagram showing the configuration of a computer system according to the fourth embodiment of the present invention. In the figure, the same components as those in the above embodiment are denoted by the same reference numerals. In the figure, 8b is R
A shutdown processing unit for performing shutdown processing for access to the PCI expansion box 2 when the AS processing unit 8 determines that the PCI expansion box 2 has been reset is shown. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG.
In the flowchart of FIG. 8, steps for performing the same processing as in the above-described embodiment are denoted by the same step numbers, and detailed descriptions thereof will be omitted. Input / output I / O
A number for identifying a process or a thread that makes an I / O request to the device 7 is registered in the item 9c of the device management table 9 (step S1). If an error occurs in the PCI device 7b, 7c or the PCI bus 5 while an I / O request is being made to the input / output I / O device 7, the RAS processing unit 8 is notified by an error interrupt signal a ( Step S
2). Upon receiving the error interrupt notification, the RAS processing unit 8
The process branches by determining whether the PCI expansion box 2 has been reset (step S3). PC
If it is determined that the I extension box 2 has been reset, the input / output I / O devices 7 b and 7 on the PCI extension box 2 are referred to by referring to item 9 c of the device management table 9.
c, stop the process or thread that is requesting I / O, and set the corresponding item 9d of the device management table 9 to NG.
(Step S4a), the computer system is normally terminated by executing a shutdown process (Step S6). If it is determined that the PCI expansion box 2 has not been reset, the same error processing (step S4b) as in the conventional RAS processing unit is performed, and the degenerate operation (step S5) is performed.

As described above, in the present embodiment,
If the PCI expansion box has been reset, RA
By changing to perform the shutdown processing as the error processing performed by the S processing unit, even if an abnormal state occurs in which the PCI expansion box is reset,
There is an effect that the computer system can be normally terminated.

Embodiment 5 FIG. 9 is a block diagram showing a configuration of a computer system according to the fifth embodiment of the present invention. In the figure, the same components as those in the above embodiment are denoted by the same reference numerals. In the figure, 8c is R
The figure shows a PCI device re-setting processing means for performing a reset process of the configuration information when the AS processing unit 8 determines that the PCI expansion box 2 is reset. Reference numeral 13 denotes a system initialization ROM that operates first when the computer system starts up, and stores configuration information 14 in a PCI device so that the host bridge 6 and the input / output I / O device 7 can be accessed from an OS (not shown). Set to 6 and 7. Item 9e of the device management table 9 indicates the configuration information 14 set in each input / output I / O device 7 by the system initialization ROM. Reference numeral 12 denotes configuration information 1 set for each bridge by the system initialization ROM 13
4 is a bridge information table for holding information 12a for identifying a bridge and configuration information 12b. The device management table 9
Item 9e of the bridge information table and item 12b of the bridge information table
It is set at the time of initialization, and here it is assumed that it has already been registered. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG. In the flowchart of FIG. 10, steps for performing the same processing as described above are given the same step numbers, and detailed descriptions thereof will be omitted. A number for identifying a process or a thread that issues an I / O request to the input / output I / O device 7 is registered in the item 9c of the device management table 9 (step S1). If an abnormality occurs in a PCI device or a PCI bus while an I / O request is being made to the input / output I / O device 7, the RAS processing unit 8 is notified by an error interrupt signal a (step S2). Upon receiving the error interrupt notification, the RAS processing unit 8 first determines whether the PCI expansion box 2 has been reset (step S3).
Is performed, the process branches. If it is determined that the PCI expansion box 2 has been reset, the PCI devices 6, 7b, 7c existing on the PCI expansion box 2
, The configuration information is reset by referring to the item 12b of the bridge information table 12 and the item 9e of the device management table 9 (step S4c).
And exit. If it is determined that the PCI expansion box 2 has not been reset, the same process (step S4b) as the conventional RAS process is performed, and the degenerate operation is performed (step S5).

As described above, in the present embodiment,
If the PCI expansion box has been reset,
By adding a PCI device reset processing means for resetting configuration information to a PCI device arranged on the I extension box, the computer system is degraded even if a single momentary blackout occurs in the PCI extension box. There is an effect that continuous operation can be performed in a normal state without processing.

Embodiment 6 FIG. FIG. 11 is a block diagram showing a configuration of a computer system according to the sixth embodiment of the present invention. In the figure, the same components as those in the previous embodiment are denoted by the same reference numerals. 8d is a PC that performs a process of resetting configuration information on a PCI device.
It shows a reset count check function that holds the reset count and the upper limit count executed by the resetting processing means 8c of the I device. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG. In the flowchart of FIG. 12, steps for performing the same processing as those described above are denoted by the same step numbers, and detailed description thereof will be omitted. I / O I / O device 7
Before making an O request, a number for identifying the process or thread that issues the I / O request is registered in the item 9c of the device management table 9 (step S1), and the I / O device 7 receives the I / O request. Make a request. I / O I / O device 7
While executing the / O request, the PCI devices 6, 7
When an error occurs in the b, 7c or the PCI bus 5, the RAS processing unit 8 is notified by an error interrupt signal a (step S2). RA that received the error interrupt notification
The S processing unit 8 branches the processing by determining whether or not the PCI expansion box 2 has been reset (step S3). If the PCI expansion box 2 has not been reset, the same process (step S4b) as the conventional RAS process is performed, and the degenerate operation (step S5) is performed. If it is determined that the PCI expansion box 2 has been reset, the process branches by further checking whether or not the number of resets has exceeded the upper limit (step S7). If the number of resets does not exceed the upper limit,
The configuration information is reset for the PCI device existing on the I extension box 2 by referring to the bridge information table item 12b and the device management table item 9e (step S4c), and the process ends.
If the number of resets exceeds the upper limit, the process or thread that is requesting I / O to the input / output I / O device on the PCI expansion box 2 is stopped, and the PCI expansion box 2
The item 9d of the device management table 9 corresponding to the above input / output I / O devices 7b and 7c is changed to NG (Step S)
4a), the degeneration operation is performed (step S5).

As described above, in the present embodiment,
By setting an upper limit on the number of times the configuration information is reset in the PCI device, the process of resetting the configuration information in the PCI device on the PCI expansion box is continuous if the PCI expansion box is frequently reset. This has the effect that it is possible to avoid the occurrence of the problem.

Embodiment 7 FIG. FIG. 13 is a block diagram showing the configuration of a computer system according to the seventh embodiment of the present invention. In the figure, the same components as those in the above embodiment are given the same symbols. In the figure, 16 is R
This is a reset process definition variable in which a variable that specifies the content of the error process performed by the AS processing unit 8 is stored. The reset process definition variable 16 specifies one of a degenerate operation process, a shutdown process, and a PCI device resetting process. Reference numeral 8e denotes an error processing switching unit that determines error processing to be performed by the RAS processing unit 8 while referring to the reset processing definition variable 16. still,
The reset process definition variable 16 reads out (reads) a definition that specifies an error process selected by the user and is stored in a file or the like in the external storage device 15 when the computer system starts up. Here, the reset processing definition variable 16
Is set to a predetermined value. Other components are the same as those described above.

Next, the processing flow will be described with reference to FIG. In the flowchart of FIG. 14, steps for performing the same processing as those described above are given the same step numbers, and detailed descriptions thereof are omitted. I / O I / O device 7
Before making an O request, a number for identifying the process or thread that issues the I / O request is registered in the item 9c of the device management table 9 (step S1), and the I / O device 7 receives the I / O request. Make a request. I / O I / O device 7
If an error occurs in the PCI device or the PCI bus while the / O request is being issued, the error interrupt signal a
Is notified to the RAS processing unit 8 (step S2).
Upon receiving the error interrupt notification, the RAS processing unit 8
The process branches by determining whether or not the extension box has been reset (step S3). PCI
If it is determined that the extension box 2 has not been reset, the same processing as the conventional RAS processing (step S4b)
And the degenerate operation (step S5) is performed.

If it is determined that the PCI expansion box 2 has been reset, the error processing switching means 8e refers to the reset processing definition variable 16 to branch the error processing contents (step S8).

When the degenerate operation is specified in the reset process definition variable 16, item 9 of the device management table 9
With reference to c, the process or thread that requests I / O to the input / output I / O devices 7b and 7c on the PCI expansion box 2 is stopped. Also, the corresponding device management table 9
Is changed to NG (step S4a), and then the degenerate operation is performed (step S5).

When the shutdown process is specified in the reset process definition variable 16, the I / O request is sent to the input / output I / O devices 7b and 7c on the PCI expansion box 2 by referring to the item 9c of the device management table 9. Stop the running process or thread. Further, the item 9d of the corresponding device management table 9 is changed to NG (step S4a).
After that, a shutdown process is performed (step S
6).

When the resetting of the configuration information is specified in the reset processing definition variable 16, the bridge information table item 12b for the bridge 6 and the input / output I / O device 7 existing on the PCI expansion box 2 is set. The configuration information is reset by referring to the item 9e of the device management table (step S4c).
finish.

As described above, in the present embodiment,
By providing error processing switching means for changing the content of error processing performed by the RAS processing unit on the user side,
There is an effect that error processing according to the importance of the input / output I / O device on the PCI expansion box can be performed.

Embodiment 8 FIG. FIG. 15 is a block diagram showing a configuration of a computer system according to the eighth embodiment of the present invention. In the figure, the same components as those in the above embodiment are denoted by the same reference numerals. Reference numerals 2a and 2b denote PCI expansion boxes connected to the host bus 4 via the host bridges 6a and 6b, respectively. For the sake of convenience, it is assumed that there are two PCI expansion boxes in the figure).
3c is supplied. Reference numerals 7a to 7e denote input / output I / O devices, and the locations of existing buses are registered in item 9b of the device management table 9. Reference numeral 17 denotes a reset process definition table, and item 1 for identifying a PCI extension box
7a and an item 17b indicating the content of error processing. Reference numeral 8e denotes an error switching unit that determines error processing to be performed by the RAS processing unit 8 with reference to the reset processing definition table 17. Note that the user definition stored in the external storage device 15 file format or the like is read (read) at the time of starting the computer system, and the reset processing definition table 17 is generated. Therefore, the reset processing definition table has already been initialized here. It is assumed that
The other components are the same as those described above.

Next, the processing flow will be described with reference to FIG. In the flowchart of FIG. 16, steps that perform the same processing as described above are given the same step numbers, and detailed descriptions thereof are omitted. Before making an I / O request to the input / output device 7, a number identifying the process or thread that issues the I / O request is entered in item 9 of the device management table 9.
c (step S1), and issues an I / O request to the input / output I / O device 7. While issuing an I / O request to the input / output I / O device 7, a PCI device or a PCI
When an abnormality occurs in the bus, the RAS processing unit 8 is notified by an error interrupt signal a (step S2). Upon receiving the error interrupt notification, the RAS processing unit 8 repeats the determination whether the PCI expansion box has been reset (step S3) until the reset PCI expansion box is determined (steps S9a-S9b).

In steps S9a-S9b, all P
If it is determined that the CI extension box has not been reset, processing similar to the conventional RAS processing (step S4)
b) is performed, and the degenerate operation (step S5) is performed.

If a reset PCI expansion box can be specified between steps S9a and S9b, the error processing switching means 8e refers to the reset processing table 17 and designates the PCI expansion box specified as having a failure. The processing branches depending on the error processing being performed (step S4e).

When the degenerate operation is specified as the error processing content, the items 9b and 9 in the device management table 9
By referring to c, the PCI box 2 in which the failure occurred
The process or thread that is requesting I / O to the above input / output I / O device 7 is stopped. Further, the item 9d of the corresponding device management table 9 is changed to NG (step S4a).
After that, the degenerate operation is performed (step S5).

If the shutdown processing is specified as the error processing content, the failure PCI is referenced by referring to the items 9 b and 9 c of the device management table 9.
The process or thread that is requesting I / O to the input / output I / O device 7 on the expansion box 2 is stopped. After changing the item 9d of the corresponding device management table 9 to NG (Step S4a), the shutdown process is performed (Step S6).

If the resetting of the configuration information is specified as the content of the error processing, the bridge information table is sent to the bridge 6 and the input / output I / O device 7 existing on the PCI expansion box 2 where the failure has occurred. The configuration information is reset (step S4c) by referring to item 12b of item 12e and item 9e of the device management table 9, and the process ends.

As described above, in the present embodiment,
In the system in which a plurality of PCI expansion boxes are connected, error processing corresponding to the degree of importance of the failed PCI expansion box can be performed by enabling the content of the error processing performed by the RAS processing unit to be set for each PCI expansion box. Has the effect of being able to perform

[0050]

According to the present invention, there is provided a computer system to which a PCI expansion box to which power is supplied separately from a computer main body is connected, wherein one or more input / output devices provided in the computer main body and the PCI expansion box are provided. An I / O device, a device management table for holding status data of each input / output I / O device, and, when an error interrupt notification is received from any of the input / output I / O devices, the input / output I / O device To identify
An error processing means for performing error processing with reference to the device management table, and whether or not the PCI expansion box has been reset when an abnormality has occurred in the PCI expansion box or an input / output I / O device in the PCI expansion box. Determining means for determining whether or not the PCI expansion box has been reset, the error processing means including a specific error processing for all input / output I / O devices provided in the PCI expansion box. , It is possible to prevent access to the input / output I / O device in the PCI expansion box which is reset in H / W and has no configuration information set, thereby avoiding occurrence of multiple failures. The effect is obtained.

Further, when it is determined that the PCI expansion box has been reset, the degenerate operation processing is performed as a specific error processing. Therefore, the input / output I / O in the H / W reset PCI expansion box is performed. This has the effect of preventing access to the O device and avoiding multiple failures.

Further, since the determination means performs the determination asynchronously with the actual I / O request to the input / output I / O device, it is asynchronous with the actual I / O request to the PCI expansion box. The effect is obtained that it is possible to know that the PCI expansion box has been reset.

[0053] Further, since the power supply to the PCI expansion box is detected to be interrupted and power failure detection means for notifying the error processing means of the power failure is further provided.
Even if the power supply to the PCI expansion box is interrupted,
As a computer system, the effect of enabling continuous degenerate operation is obtained.

Further, when it is determined that the PCI expansion box has been reset, the shutdown processing is executed as a specific error processing. Therefore, when the PCI expansion box is reset, the computer system can be normally shut down. Is obtained.

A system initialization ROM that operates first when the computer system starts up, and a configuration that records configuration information set for the input / output 1 / O device in the PCI expansion box by the system initialization ROM. Further comprising information recording means,
When it is determined that the PCI expansion box has been reset, the configuration information is reset for each input / output I / O device in the PCI expansion box as a specific error processing. Thus, even if a single momentary blackout occurs, it is possible to continuously operate without degenerate operation.

Since the upper limit of the number of times of resetting the configuration information is set, when an intermittent momentary power failure occurs in the power supply of the PCI expansion box, the resetting process of the configuration information is continuously performed. An effect is obtained that the execution can be avoided.

Further, since the apparatus further comprises an error processing switching means for selecting the content of a specific error processing to be executed by the error processing means, the importance of the input / output I / O device arranged on the PCI expansion box and the system The effect is obtained that it is possible to select the error processing according to the configuration.

When a plurality of PCI expansion boxes are connected, error processing definition means for setting specific error processing contents for each PCI expansion box is further provided. This makes it possible to execute an error process according to the above.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing a processing procedure of the computer system according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a computer system according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a processing procedure of the computer system according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a computer system according to Embodiment 3 of the present invention.

FIG. 6 is a flowchart illustrating a processing procedure of the computer system according to the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a computer system according to Embodiment 4 of the present invention.

FIG. 8 is a flowchart showing a processing procedure of the computer system according to the fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a computer system according to Embodiment 5 of the present invention.

FIG. 10 is a flowchart showing a processing procedure of the computer system according to the fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a computer system according to Embodiment 6 of the present invention.

FIG. 12 is a flowchart illustrating a processing procedure of a computer system according to Embodiment 6 of the present invention.

FIG. 13 is a block diagram showing a configuration of a computer system according to Embodiment 7 of the present invention.

FIG. 14 is a flowchart illustrating a processing procedure of the computer system according to the seventh embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a computer system according to Embodiment 8 of the present invention.

FIG. 16 is a flowchart showing a processing procedure of the computer system according to the eighth embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a conventional computer system.

And FIG. 18 is a flowchart illustrating a processing procedure of a conventional computer system.

FIG. 19 is a flowchart showing a processing procedure of a conventional computer system.

[Explanation of symbols]

1 Computer system main body, 2 PCI expansion box, 3
a, 3b power supply, 4 host bus, 5 PCI expansion bus,
6 Host bridge, 7a, 7b, 7c I / O I / O
Device, 8 RAS processing section, 8a degeneration operation processing, 8b
Shutdown, 8c PCI device reset processing,
8d reset number check function, 8e error processing switching means, 9 device management table, 10 fixed cycle check means, 11 power cutoff detection means, 12 bridge table, 13 system initialization ROM, 14 configuration information, 15 external storage device, 16 reset process definition variable, 17 reset process definition table.

Continued on the front page (72) Inventor Yasuyuki Ibaraki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5B011 DA01 EA02 EB03 EB06 GG01 JA02 KK01 5B014 EA04 EB03 FA09 FA16 FB04 GD05 GD25 GD34 GD35 GD37 GE05 HC03 HC08 HC09 5B083 AA08 BB01 BB03 CD07 DD09 DD10 DD13 EE01 EE06 EE07 GG08

Claims (9)

[Claims] 1. A PC to which power is supplied separately from a computer main body
A computer system to which an I / O expansion box is connected, wherein one or more input / output I / O devices provided in the computer main body and the PCI expansion box, and status data of each of the input / output I / O devices When receiving an error interrupt notification from any of the input / output I / O devices, the input / output I / O device is identified and error processing is performed with reference to the device management table. Error determination means for determining whether or not the PCI expansion box has been reset when an abnormality has occurred in the PCI expansion box or the input / output I / O device in the PCI expansion box. When the determination unit determines that the PCI expansion box has been reset, the error processing unit determines whether the PCI expansion box has been reset. Computer system and performing specific error processing with respect to all of the above input-output I / O device provided within. 2. The computer system according to claim 1, wherein when it is determined that the PCI expansion box has been reset, a degenerate operation process is performed as the specific error process. 3. The computer system according to claim 1, wherein the determination unit performs the determination asynchronously with an actual I / O request to the input / output I / O device. 4. A power cut-off detecting means for detecting that power supply to said PCI expansion box has been cut off and notifying said error processing means of said power supply abnormality. The computer system according to any one of the above. 5. The computer system according to claim 1, wherein when it is determined that the PCI expansion box has been reset, a shutdown process is performed as the specific error process. 6. A system initialization ROM that operates first when the computer system starts up, and configuration information set for the input / output 1 / O device in the PCI expansion box by the system initialization ROM. Configuration information recording means for recording, and when it is determined that the PCI expansion box has been reset, as the specific error processing, a configuration is performed for each of the input / output I / O devices in the PCI expansion box. 2. The method according to claim 1, further comprising resetting the translation information.
6. The computer system according to any one of claims 1 to 5. 7. The computer system according to claim 6, wherein an upper limit is set for the number of times the configuration information is reset. 8. An apparatus according to claim 1, further comprising an error processing switching means for selecting the content of said specific error processing to be executed by said error processing means.
The computer system according to any one of the above. 9. The system according to claim 1, further comprising an error processing definition unit configured to set the content of the specific error processing for each of the PCI expansion boxes when a plurality of the PCI expansion boxes are connected. 9. The computer system according to any one of 1 to 8.