JP2001345703A - Digital-to-analog converter and digital-to-analog converting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital-to-analog converter having a small circuit scale of a noise shaper for reducing a conversion error of an adder of a plurality of 1-bit digital-to-analog converters and an analog output signal of the digital-to- analog converter and a digital-to-analog converting method having a short processing time. SOLUTION: The digital-to-analog converter comprises a signal generator for outputting (n) or (n-1) pieces (n is integer of 2 or more) of a quantization signals equal to quantization signals generated from (n) pieces of second noise shapers for differentiating the value of an output signal of a delay unit of the noise shaper, based on an input signal of the shaper and the output signal of the delay unit of the shaper, and a unit for generating (m) pieces of addition signals obtained by adding (n-1) pieces of the quantization signals and at least a part of the quantization signals of the second noise shaper or at least a part of the (n) pieces of the quantization signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter for converting a digital signal into an analog signal.

[0002]

2. Description of the Related Art Generally, for example, 44.1 kHz (f
s) It is extremely difficult to make a digital-to-analog converter for a sampling 16-bit audio signal band (20 kHz band) as it is. Such first
Digital / analog conversion device is 2 to the 16th power = 65
It has 536 1-bit digital / analog converters (referred to as "D / A converters") and adders for analog output signals of these converters. Such a second
The digital / analog conversion device of (2) multiplies the analog output signal of the LSB D / A converter by 2 k times (0 ≦ k ≦
15) Output analog output signal with weight of 1)
It has six D / A converters and an adder for their analog output signals.

Therefore, the output signal of the D / A converter of the MSB of the second digital / analog converter is the D / A of the LSB.
The output signal of the A converter has a weight of 2 15 = 32768 times. Therefore, a variation of 1/32768 = 0.00304% of the output signal of the MSB D / A converter produces the same result as the change of the output signal of the LSB D / A converter. That is, the output level of the output signal of the MSB D / A converter and the addition accuracy of the adder must be smaller than 0.00304%. However, 65536 D
It is extremely difficult to make a / A converter and a D / A converter with an accuracy of 0.00304% or less.

[0004] Therefore, for example, 44.1 kHz that has been put into practical use
Digital / analog converters for audio signals of 16 bits with z (fs) sampling generally include an oversampling device. The oversampling device converts an input signal into data having a higher frequency (higher time-axis accuracy) than the input signal and a smaller number of bits of each sampled data (lower amplitude resolution). Thereby, high conversion accuracy can be realized using a D / A converter having a low amplitude resolution. Therefore, an inexpensive and highly accurate digital / analog converter having a D / A converter (for example, a PWM device) with a simple configuration can be realized.

[0005] For example, the digital / digital for audio signal of 16 bits at 44.1 kHz (fs) sampling described above.
The analog converter is actually 2.8 MHz (64 f
s) Replaced by a sampling digital / analog converter. Although the digital / analog converter has a higher frequency (sampling rate) and lower amplitude resolution than the original digital / analog converter, both digital / analog converters are substantially equivalent (16 bit). Accuracy). An audio signal (2.8 MHz (64 f.
s) sampling) is subjected to noise shaping processing, so that the sampling accuracy is substantially the same as a 16-bit audio signal at 44.1 kHz (fs) sampling with a small number of bits (even if the amplitude resolution is low). Have. The noise shaper reduces the quantization error by quantizing the oversampled audio signal by a quantizer and feeding back an error generated by the quantization (referred to as quantization error or quantization noise).

For example, the S / N of a secondary noise shaper having a quantized output bit number of n and an oversampling rate of M
Is represented by the following equation. S / N = 10 · log ₁₀ [{15 / (2 · π ⁴ )} · (2 ⁿ −1) ² · M ⁵ ] (unit is dB) (1) For example, M = 64 times (2.8 MHz ( S / N = 102.7, where n = 4 bits
dB (S / N equivalent to about 10 bits). As described above, by performing the noise shaping process on the oversampled signal by the noise shaper, it is possible to realize a highly accurate and inexpensive digital / analog conversion device.

[0007] FIGS. 10 and 11 include the above technique.
1 shows a conventional digital / analog converter. The conventional digital / analog converter shown in FIGS. 10 and 11 performs bit compression by performing noise shaping processing on an oversampled signal. The conventional digital / analog converter has realized an inexpensive and highly accurate digital / analog converter.

[Description of Overall Configuration of Conventional Digital / Analog Converter (FIG. 10)] FIG. 10 shows a conventional digital / analog converter.
FIG. 2 shows a block diagram of an analog conversion device. 10, 1001 is an input terminal, 1002 is a digital filter, 1003 is a first noise shaper, 1004 is a decoder, and 1005 is a plurality of 1-bit digital / analog converters (referred to as “1-bit D / A converters”). ), 100
6 is an adder and 1007 is an output terminal. The operation will be described below.

A digital filter 1002, which is a low-pass filter, converts an input digital signal such as a video signal or an audio signal input from an input terminal 1001 into a p-fold (p is an integer of 2 or more) sampling frequency. In addition, an unnecessary band of fs / 2 or more (fs is the sampling frequency of the input digital signal) of the input digital signal is attenuated. This is because the frequency components in the unnecessary band cause aliasing (return signal) by digital / analog conversion and deteriorate the signal.

[0010] The first noise shaper 1003 reduces the number of bits of the output signal of the oversampled digital filter 1002. First noise shaper 10
Numeral 03 quantizes the output signal of the digital filter 1002 (limits the word length (the number of bits per sampling data)), and feeds back a quantization error generated at the time of quantization inside the first noise shaper 1003. “Quantizing (limiting the word length of the output signal)” means reducing the number of bits representing the amplitude component of the input digital signal for each sampling data.

More specifically, the first noise shaper 100
3 has at least an adder and a quantizer. The adder outputs a signal (first noise shaper 1003) obtained by passing a quantization error (output signal of the quantizer) through a shaping filter.
Typically have a shaping filter of any configuration. ) And the input signal are added by the adder, and the addition result is sent to the quantizer. The quantizer quantizes the addition result (limits the data word length), outputs the quantization result as an output signal of the first noise shaper 1003, and
A quantization error obtained by subtracting the quantization result from the addition result is fed back to the adder.

For example, the oversampling rate M = 64
The double (2.8 MHz (64 fs) sampling) first noise shaper 1003 outputs an output signal having 12 output gradations ("gradation" means level). For example, the first noise shaper 1003
, 0, 1, 2,..., And 6 are output. The output signal having 12 output tones has an S / N of about 100 dB (2n = 11) according to the equation (1). First noise shaper 100
3 is input to the decoder 1004. The decoder 1004 outputs (c +) of m PWM signals (oversampling frequency (for example, 2.8 MHz (64 fs))).
1) An analog signal having a 1-bit resolution of twice the clock is output (c is the number of gradations of the PWM signal). The m PWM signals output from the decoder 1004 are m D / D signals.
1-bit D / A converter group 100 composed of A converters
5 and converted into m analog signals. Adder 1006 adds m analog signals and outputs an added signal.

In the specification and claims, for example, an apparatus including the entire configuration of FIG. 1 (embodiment of the present invention) or FIG. 10 (conventional example) is referred to as a “digital / analog conversion apparatus”. , A block for performing digital / analog conversion in the digital / analog conversion device
An analog converter (referred to as "D / A converter")
Distinguish between the two.

[Explanation of Decoder Configuration (FIG. 11)] FIG.
FIG. 1 shows a configuration diagram of a decoder 1004 in the digital / analog conversion device shown in FIG. In FIG. 11, reference numeral 1101 denotes an input terminal; 1102, a level converter;
103 is a second noise shaper and 1107 is a data converter. The second noise shaper 1103 includes the adder 1
104, a quantizer 1105, and a shaping filter 1106.

The input terminal 1101 of the decoder 1004 is
An input signal (output signal of the first noise shaper 1003) having the number of gradations k (for example, k = 12) is input. For example,-
, 0, 1, 2,..., And 6 are input. Level converter 110
2 converts the signal of the number of gradations k input from the input terminal 1101 into a continuous positive integer value X starting from 0. For example, if the input signal is a -12 value signal of -5 to +6, 5 is added to the signal to convert it to a 12-value signal of 0 to 11 (a continuous positive integer value starting from 0).

Next, the operation of the second noise shaper 1103 (FIG. 11) will be described. The adder 1104 adds the output signal X of the level converter 1102 and the output signal of the shaping filter 1106 which are continuous positive integer values starting from 0 (for example, 0 to 11). And the quantizer 1
Numeral 105 quantizes and outputs the output signal (addition result) of the adder 1104 (quantized signal), and feeds back a quantization error (an error between the addition result and the quantization result) to the shaping filter 1106. In the case of the conventional example, the following equation is obtained. Quantization error = addition result− (quantized signal × k) k is a threshold value of the quantizer and is equal to the number of gradations of the input signal. The quantizer 1105 divides the output signal of the adder 1104 by a threshold k (for example, k = 12) and outputs (quantizes) a quotient (integer). The quantization error (the remainder of the division) is input to the shaping filter 1106. Typically,
As described above, the number of gradations of the output signal X of the level converter 1102 is equal to the threshold value of the quantizer. For example, the number of gradations of the output signal X of the level converter 1102 is 12 (0 to 11), and the threshold value of the quantizer is k = 12.

[0017] The decoder 1004 of FIG.
(K is the number of gradations of the input signal X). K second size shapers 110 shown in FIG.
The initial value of the output signal (delay signal) of the delay device included in the shaping filter 1106 is 0, 1, 2, 3 from the top.
... Set to (k-1). For example, the output signal of the shaping filter 1106 is 0, 1, 2, 3,.
If (k−1) and the first output signal X of the level converter 1102 is 5, the output signal of the adder 1104 is 5, 6, 7,... (K + 4) from the top.

The quantizer 1105 which receives these values outputs quantized signals Q (0), Q (1), Q (2),.
(K-1) is output. 5 where (k + 4) is input from k
Quantizers 1105 output the quantized signal 1 (Q (k
(−5) to Q (k−1)) and (k−5) quantizers 1105 inputting 5 to (k−1) output a quantized signal 0 (Q (0) to Q (k) -6)). Also, the quantizer 1105 which has input these values outputs a quantization error.
The quantization errors of the k quantizers 1105 in FIG. 11 are 5, 6, 7,..., (K−1), 0, 1,. Each quantization error is always from 0 to (k−
Take all values up to 1). Thus, the k second
, The sum of the quantization errors generated by the noise shaper 1103 always has a constant value. The output signal Q of the quantizer 1105 in FIG. 11 takes, for example, any one of −1, 0, 1, and 2 (a possible value of the output signal Q depends on the configuration of the shaping filter 1106). .

The number of data converters 1107 is k (for example, k
= 12), the output signal (quantized signal Q) of the second noise shaper 1105 is converted into n signals by the following means. The converter 1107 receives k quantized signals, extracts m quantized signals for every n signals, and adds them (n ≦ k, k ≦ m × n) (addition signal). Specifically, the following addition signal W (j) (0 ≦ j ≦ n−1) is generated. W (0) = Q (0) + Q (n) + Q (2n) +... + Q (m × n) W (1) = Q (1) + Q (n + 1) + Q (2n + 1) +. m × n + 1):: W (n−1) = Q (n−1) + Q (2n−1) +... + Q (m × n + n−1) (Q (i) divides i by k Let i 'be the remainder
The i′-th second noise shaper 110 from the top in FIG.
3 means the quantized signal Q. For example, if k = 12, Q (15) = Q (3). )

As described above, Q (i) takes one of the values -1, 0, 1, or 2, but the addition signal W (j) is the addition value of Q (i) which is widely dispersed. , Each addition signal W
(J) satisfies 0 ≦ W (j) ≦ m. Also, all W
The sum of (j) ΣW (j), ie the sum of all Q (i) ΣQ (i), matches the value X of the digital input signal, but each Q (i) has an oversampling period (eg, It is output as an output pattern of the primary noise shaper every 1 / 2.8 MHz (1/64 fs). This can be attributed to variations in individual 1-bit D / A converters 1005,
Alternatively, the noise in the audio band is reduced by multiplying the error between the input terminals of the adder 1006 by the first-order differential characteristic, and the linearity of the digital / analog conversion device (analog when the digital input signal is gradually increased from 0 to the maximum value) Output signal linearity).

Next, the obtained n added signals W (j) (the number of gray scales is c) are respectively processed by a PWM device.
Oversampling frequency (for example, 2.8 MHz (6
4fs)) is converted into a 1-bit signal of a clock of (c + 1) times and output (PWM signal). For example, W
If the number of gradations in (j) is c = 7 (0 to 6), PW is performed with a clock that is (c + 1) = 8 times the oversampling period
It is converted to an M signal. The PWM signal is the data converter 1
107 and the output signal of the decoder 1004.

According to the input signal of W (j) = 0-6, PW
The M device outputs 1 in one to seven clock periods of the eight-times clock, and outputs zero in the remaining seven to one clock periods. In order to prevent the performance of the PWM device from deteriorating, a clock of (c + 1) times the oversampling period is used, and all zero output signals and all one output signals that eliminate the edge of the signal within one sample data period are not used. .
When W (j) = i (for example, i = 2), (0 ≦ W (j)
≦ c−1), oversampling period (for example, 1 /
2.8 MHz (1/64 fs)) (c + 1)
A high output signal (1) is output during (i + 1) (for example, three) periods of the eight clock periods (for example, eight),
The row output signal (0) is output during (ci) (for example, 5) periods.

The n 1-bit D / A converters 1005 (FIG. 10) receive n PWM signals as output signals of the decoder 1004 (FIG. 10). n 1-bit D / A
The converter 1005 converts the n PWM signals into n analog signals and outputs the analog signals. Next, an adder 1006 (FIG. 1)
0) adds the output analog signals of the n 1-bit D / A converters 1005, and outputs the added analog signal from the output terminal 1007. The added analog signal is output from the output terminal 1007. The above is the configuration of the conventional digital / analog converter.

In another prior art example, the decoder uses (k
-1) There are two second noise shapers 1103 (one less than the embodiment of FIG. 11). The quantizer 1105 included in the second noise shaper has a threshold value of k−1
Then, the output signal of the adder 1104 is divided by (k-1) (for example, k-1 = 12-1 = 11), and a quotient (integer) is output (quantized). The initial values of the delay devices included in the shaping filters 1106 of the (k−1) second noise shapers 1103 are 0, 1, 2, 3,.
Set to (k-2). For example, the output signals of the shaping filter 1106 are 0, 1, 2, 3,.
-2), and if the first output signal of the level converter 1102 is 5, the output signal of the adder 1104 is 5, 6, 7,... (K + 3) from the top.

The quantizer 1105 receiving these values outputs quantized signals Q (0), Q (1),... Q (k−2). The five quantizers 1105 inputting (k−1) to (k + 3) output the quantized signal 1 (Q (k−
6) to Q (k−2)) and 5 to (k−2), (k−6) quantizers 1105 output a quantized signal 0 ((Q (0) to Q (k)). -7))). Also, the quantizer 1105 which has input these values outputs a quantization error. The quantization error of the (k-1) quantizers 1105 is:
5, 6, 7 ..., (k-2), 0, 1, ... 4 from the top
It is. Each quantization error is always from 0 to (k
Take all values up to -2). Therefore, the sum of the quantization errors generated by the (k-1) second noise shapers 1103 always has a constant value.

In another conventional example, the obtained n added signals W (j) are respectively oversampled by a dynamic element matching device (DEM device) (for example, 2.8 MHz (64f)).
s)) is converted into a (c-1) -bit signal of a clock (c-1) times that of (c-1), and is output (DEM signal). The DEM device will be described later. The DEM signal is an output signal of the data converter 1107 and an output signal of the decoder 1004.

[0027]

However, in the above conventional configuration, at least (k-
1) There is a problem that two second noise shapers are required, and the circuit scale becomes large. SUMMARY OF THE INVENTION An object of the present invention is to provide a D / A conversion device and a D / A conversion method which are small, inexpensive, high-speed processing and high in accuracy, and which solve the above-mentioned conventional problems. Another object of the present invention is to provide a small-scale, high-speed, high-precision D / A conversion method suitable for a digital / analog conversion method including software processing in a computer or a microcomputer.

[0028]

According to a first aspect of the present invention, an input digital signal is low-pass filtered and the sampling frequency of the digital signal is multiplied by p (p is an integer of 2 or more). A first filter having a digital filter and a first feedback path for quantizing an output signal of the digital filter, outputting a first quantized signal, and feeding back a first quantization error generated by the quantization;
, A decoder that inputs the first quantized signal and outputs m (m is an integer of 2 or more) addition signals, and outputs a plurality of analog signals based on the m addition signals. A plurality of digital / analog converters to generate,
An output unit having an adder for adding the plurality of analog signals, wherein the decoder adds an output signal of a second feedback path to the first quantized signal. A second quantizer for quantizing the subtracted or subtracted signal to generate a second quantized signal and a second quantization error, and delaying the second quantization error to generate a delayed signal. A second noise shaper having at least one delay unit in the second feedback path, and n different delay signal values based on the first quantized signal and the delayed signal ( n is an integer of 2 or more) generated by the second noise shaper.
A signal generating device that outputs the same n or (n−1) third quantized signals as the quantized signal of (a), the (n−1) third quantized signals and the second An apparatus for generating the m number of added signals obtained by adding at least a part of the quantized signal or at least a part of the n number of the third quantized signals;
A digital / analog conversion device characterized by having:

The digital / analog conversion device of the present invention comprises:
Typically, it has one second noise shaper (there may be two or more second noise shapers), and the first quantized signal and the one that the second noise shaper has Or, based on the output signals of two or more delay units, typically n (or (n-1)) by one signal generator
(A digital-to-analog converter for generating a quantized signal) (two or more signal generators may be used). Although the conventional decoder has n second noise shapers (for example, when the first quantized signal has 12 gradations (0 to 1)
If 1), the conventional digital / analog converter is 1
It had two (or eleven) second noise shapers. The decoder of the present invention typically has one second noise shaper, one signal generator, and a storage unit for storing the quantized signal. The present invention has an effect that a digital-to-analog converter with the same performance can be realized at a lower cost and a smaller size than before by using a decoder smaller than the conventional one.

The added signal may be a signal obtained by adding a part of the n third quantized signals generated by the signal generating device, and one second quantized signal generated by the second noise shaper. Signals and (n-1) third signals generated by the signal generation device
May be a signal obtained by adding a part of the quantized signal of. That is, the second quantized signal output from one second noise shaper may be used for the purpose of generating an addition signal,
You do not need to use it. The “first quantized signal” input by the second noise shaper and the signal generator may be the first quantized signal itself output by the first noise shaper, or, as in the embodiment, the first quantized signal. A signal obtained by level-converting the first quantized signal output by the noise shaper may be used. This is because the signal obtained by level conversion of the first quantized signal is also substantially the first quantized signal. The “second quantized signal” and the “third quantized signal” are substantially the same. For the purpose of clarifying the source of the quantized signal, in the specification and the claims, the quantized signal generated by the second noise shaper is referred to as a second quantized signal, and the signal generation is performed. The quantized signal generated by the device is called a third quantized signal.

According to a second aspect of the present invention, the second noise shaper is configured such that k · Q = X + (Z ⁻¹ −1) ²
ER (X is the first quantized signal, and Z ⁻¹ is Z
Representing a first-order delay of the transformation, Q is a second quantized signal, k is a quantization threshold, and ER is an error signal due to quantization. 2) performing a second-order noise shaping process represented by the following equation:
It is an analog converter.

The present invention has the effect of realizing a high-precision digital-to-analog converter that is hardly affected by relative conversion errors due to variations in digital-to-analog converters and adders for analog signals.

According to a third aspect of the present invention, the m
Of the (n-1) third quantized signals and the second quantized signals, each of which adds n / m or more of the quantized signals for every m signals. Addition signal,
Alternatively, among the n third quantized signals, n
3. An added signal obtained by adding / m or more of the quantized signals, wherein the added signal is such that at least a part of the quantized signals to be added are different from each other. Digital / analog converter.

Each of the m added signals is a signal obtained by adding the quantized signals uniformly dispersed as described above from the quantized signals. Thereby, the maximum value of the addition signal can be reduced. Typically, assuming that the number of gradations of the quantized signal of the first noise shaper is k, ｛(k /
m) +1｝ gradation. For example, k = 11 gradations and n =
12, when m = 2 (an addition signal of an odd-numbered quantization signal and an addition signal of an even-numbered quantization signal), each of the m addition signals has seven gradations (0 to 6). . Since the quantized signal of the second noise shaper is, for example, -2, -1, 0 or 1, if the added signal of the quantized signal in the biased portion is generated, the number of gradations is larger than 7. Become.

By reducing the number of gradations of the addition signal, the circuit scale of a plurality of digital / analog converters for generating a plurality of analog signals based on the m addition signals is reduced, or a DEM device is provided. Since the clock rate of the D / A converter etc. constituting
Deterioration of D / A conversion accuracy can be prevented, and the influence of variations in analog circuits can be almost eliminated. The present invention has an effect that an inexpensive, small-sized, high-precision digital / analog converter can be realized.

According to a fourth aspect of the present invention, the m
When each of the number of added signals (hereinafter referred to as “the added signal”) is the number of output gradations c (c is an integer of 2 or more) of the added signal, (c−1) 1-bit And converting the 1-bit output signal into (c-1) 1
Each of the (c-1) 1-bit output signals is converted into an analog signal by a bit digital / analog converter within one sampling period of the addition signal. The digital / analog converter according to any one of claims 1 to 3, wherein the signal is converted into an analog signal at least once by all the 1-bit digital / analog converters.

With the above arrangement, when the number of output gradations is c (for example, c = 7 (0 to 6)), (c-1) (for example, 6
) 1-bit digital-to-analog converters and other analog elements can eliminate relative conversion errors. The present invention has an effect that a highly accurate digital / analog conversion device can be realized.

According to a fifth aspect of the present invention, the signal generating device repeatedly adds or subtracts a constant number to the delay signal based on the first quantized signal and the delay signal. , The value of the delay signal differs.
N or (n−1) identical to the second quantized signals generated by the second noise shaper (n is an integer of 2 or more)
The digital / analog conversion device according to any one of claims 1 to 4, wherein the digital / analog conversion device outputs three third quantized signals.

The decoder of the present invention typically has one second
And a single high-speed signal generator with a simple configuration capable of generating a third quantized signal and a storage unit for storing the quantized signal. The present invention has an effect that a high-precision digital-to-analog conversion device that is inexpensive, small-sized, and can operate at high speed can be realized by using a smaller decoder than before.

The signal generator of the digital / analog converter of the present invention receives the first quantized signal and the delay signal of one or more delay units of the second noise shaper. A first third quantized signal Q based on the first quantized signal and one or more delay signals
(0) is calculated and output. Next, a fixed number of 1 is added to or subtracted from one or more delayed signals, and a second third signal is added based on the resulting new delayed signal and the first quantized signal. Is calculated and output. By repeating this, n or (n-1) third
Is output. "Repeat this"
It means to execute more than once. "Adding or subtracting a certain number to or from the delayed signal" includes overflow of the value of the delayed signal. For example, in general, adding 1 to the maximum delay signal overflows to 0, or subtracting 1 from the minimum delay signal overflows to the maximum signal.

According to a sixth aspect of the present invention, there is provided a digital filter step for performing low-pass filtering on an input digital signal and p times the sampling frequency of the digital signal (p is an integer of 2 or more), The digital filter
A first noise shaper step having a first feedback step of quantizing the signal generated in the step to generate a first quantized signal and feeding back a quantization error generated by the quantization; A decoder step of inputting one quantized signal and generating m (m is an integer of 2 or more) added signals; and inputting the m added signals to a plurality of digital / analog converters to generate a plurality of added signals. A digital / analog conversion method comprising: a digital / analog conversion step of generating an analog signal; and an output step having an addition step of adding the plurality of analog signals, wherein the decoder step comprises:
A signal obtained by adding or subtracting the signal generated in the second feedback step to the first quantized signal is quantized to obtain a second signal.
A second quantization step of generating a second quantization error and a second quantization error, and at least one delay step of delaying the second quantization error to generate a delay signal. A feedback step
And n (where n is an integer of 2 or more) second noise shaper steps that differ in the value of the delayed signal based on the first quantized signal and the delayed signal. Is the same as the second quantized signal generated by
Generating a number of (n-1) third quantized signals and / or at least a part of the (n-1) third quantized signals and the second quantized signals. The n
Generating the m number of added signals by adding at least a part of the number of third quantized signals.

The digital / analog conversion method of the present invention comprises:
For example, the present invention can be applied to a digital-to-analog conversion method using software on a microcomputer or a personal computer. The digital / analog conversion method of the present invention comprises:
It has one second noise shaper step (or may have two or more second noise shaper steps), for example, the first quantized signal and the second noise shaper step Generates n (or (n-1)) quantized signals by a signal generation step based on one or more delay signals of one or more delay steps.

Although the conventional decoder step has n second noise shaper steps (for example, if the quantized signal which is the output signal of the first noise shaper is 12
For gray levels (0 to 11), the conventional digital / analog conversion step has 12 (or 11) second noise shaper steps. ), The decoder step of the invention typically comprises one second noise shaper
Steps and 12 (or 11 or 10) signal generation steps. Generally, the signal generation step is a second
Processing time is shorter than the noise shaper step of

Therefore, the present invention has an effect of realizing a digital / analog conversion method in which processing time by software is short. Therefore, for example, a microcomputer can realize digital / analog conversion processing by software which cannot be caught by the conventional method.
Also, by implementing the digital-to-analog conversion method of the present invention on a computer, for example, it is possible to secure a margin of processing capability of the computer as compared with the conventional method. You can do it.

According to a seventh aspect of the present invention, in the signal generating step, a constant number is repeatedly added or subtracted to the delay signal based on the first quantized signal and the delay signal. The same n or (n−1) as the second quantized signals generated by the n (n is an integer of 2 or more) second noise shaper steps having different values of the delay signal 7. The digital / analog conversion method according to claim 6, wherein three third quantized signals are generated.

Although the conventional decoder step has n second noise shaper steps (for example, if the quantized signal which is the output signal of the first noise shaper is 12
For gray levels (0 to 11), the conventional digital / analog conversion step has 12 (or 11) second noise shaper steps. ), The decoder step of the invention typically comprises one second noise shaper
Steps and 12 (or 11 or 10) signal generation steps.

In the signal generation step of the digital / analog conversion method of the present invention, the first quantized signal and one or more delay signals are input. A first third quantized signal Q (0) is calculated and generated based on the first quantized signal and one or more delay signals. Then, 1
A constant number of 1 is added to or subtracted from one or more delayed signals, respectively, and a second third quantization is performed based on the resulting new delayed signal and the first quantized signal. The signal Q (1) is calculated and generated. By repeating this, n
Or (n-1) third quantized signals are output.

Therefore, the present invention has an effect of realizing a digital / analog conversion method in which processing time by software is short. Therefore, for example, a microcomputer can realize digital / analog conversion processing by software that cannot be caught by the conventional method.
Further, for example, by implementing the digital-analog conversion method of the present invention on a computer, it is possible to secure a margin of processing capability of the computer as compared with the conventional method, and for example, the computer simultaneously executes other processes in parallel. I can do it.

The signal generating step first generates a third quantized signal (without adding or subtracting a certain number) based on, for example, the first quantized signal and the delay signal, and generates the generated quantized signal. You may memorize | store in a memory | storage part. Next, a fixed number is added to or subtracted from the first quantized signal and the delayed signal to generate a third quantized signal, and the process is repeated. In the signal generating step, first, for example, a third quantized signal is generated by adding or subtracting a certain number to or from the first quantized signal and the delayed signal, and the generated quantized signal is stored in the storage unit. Is also good.
Next, a fixed number is added to or subtracted from the first quantized signal and the delayed signal to generate a third quantized signal, and the process is repeated.

According to an eighth aspect of the present invention, there is provided a digital filter step for performing low-pass filtering on an input digital signal and p times the sampling frequency of the digital signal (p is an integer of 2 or more); The digital filter
A first noise shaper step having a first feedback step of quantizing the signal generated in the step to generate a first quantized signal and feeding back a quantization error generated by the quantization; A decoder step of inputting one quantized signal and generating m (m is an integer of 2 or more) added signals; and inputting the m added signals to a plurality of digital / analog converters to generate a plurality of added signals. A digital / analog conversion method comprising: a digital / analog conversion step of generating an analog signal; and an output step having an addition step of adding the plurality of analog signals, wherein the decoder step comprises:
A second quantization step of generating a second quantization signal and a second quantization error by quantizing a signal obtained by adding or subtracting a generation signal of a second feedback step to the first quantization signal; A second noise shaper step having at least one delay step of delaying the second quantization error to generate a delayed signal; a second noise shaper step having the first feedback step; A signal generation step of generating the m number of added signals based on a value of a conversion table determined based on the quantized signal and the delay signal.

The present invention can be applied to a digital-to-analog conversion method using software on a microcomputer or a personal computer, for example. The digital / analog conversion method of the present invention has a conversion table for obtaining an addition signal based on the first quantized signal and the delay signal. The digital / analog conversion method of the present invention uses a conventional digital / analog conversion method.
It has a decoder step that has a very short processing time compared to the analog conversion method. The present invention has an operation of realizing a digital / analog conversion method capable of high-speed processing by software. Therefore, for example, a microcomputer can realize digital / analog conversion processing by software which cannot be caught by the conventional method. Also, for example, by performing the digital-analog conversion method of the present invention on a computer, it is possible to secure a margin of computer processing power more than the conventional method,
For example, the computer can simultaneously execute other processes in parallel.

In the digital / analog conversion method according to the eighth aspect, typically, the addition signal is directly obtained from the conversion table. The “addition signal” in the digital / analog conversion method according to claim 6.
This means that the signals have the same value as the above, and do not mean that the signals obtained from the conversion table are added to the signals obtained. For example, a value of the conversion table (preferably, the value of the conversion table is m
Are the added signals. ) Is read.

[0053]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of the present invention. << Embodiment 1 >> [Description of Overall Configuration of Digital / Analog Converter (FIG. 1)] FIG. 1 is a block diagram of a digital / analog converter according to a first embodiment of the present invention. In FIG. 1, 11
Is an input terminal, 12 is a digital filter, 13 is a first noise shaper, 14 is a decoder, 15 is a first output unit,
16 is a second output unit, 17 is a first adder, and 18 is an output terminal. Hereinafter, the operation will be described.

The digital filter 12, which is a low-pass filter, converts an input digital signal such as a video signal or an audio signal input from the input terminal 11 into a p-fold (p is an integer of 2 or more) sampling frequency. In addition, an unnecessary band of fs / 2 or more (fs is the sampling frequency of the input digital signal) of the input digital signal is attenuated.

Next, the first noise shaper 13 bit-compresses the oversampled output signal of the digital filter 12. The first noise shaper 13 quantizes the output signal of the digital filter 12 (limits the word length), and feeds back a first quantization error generated at the time of quantization inside the first noise shaper 13. Specifically, the first noise shaper 13 has at least an adder and a quantizer. The adder inputs a signal obtained by passing a first quantization error (output signal of the quantizer) through a shaping filter (the first noise shaper 13 typically has a shaping filter having an arbitrary configuration). The signal and the signal are added by an adder, and the addition result is sent to a quantizer. The quantizer quantizes the addition result (limits the data word length), outputs the quantization result (first quantized signal) as an output signal of the first noise shaper 13, and outputs the result from the addition result. The first quantization error obtained by subtracting the first quantization signal is fed back to the adder. Error between the addition result and the first quantization signal (first quantization error)
May be positive or negative.

For example, the oversampling rate M = 64
The double (2.8 MHz sampling (64 fs)) first noise shaper 13 outputs an output signal (first quantized signal) having 12 output gradations. For example, the first noise shaper 13 outputs -5, -4, ..., 0, 1, 2,.
.. Output a signal of any one of the 12 values of 6. An output signal (first quantized signal) having 12 output gradations is
According to the equation (1), it has an S / N of about 100 dB (n of 2).
Power = 11).

The output signal (first quantized signal) of the first noise shaper 13 is input to the decoder 14. The decoder 14 outputs two output signals W (0) and W (1) (oversampling frequency (for example, 2.8 MHz (64 f
s)) and the number of gradations is 7 (0, 1, 2,.
・ The signal of 6) is output. 2 output from the decoder 14
The output signals (addition signals) are input to the first output unit 15 and the second output unit 16. The first output unit 15 and the second output unit 16 have the same configuration. Each of the first output unit 15 and the second output unit 16 includes six D / A converters and an adder that adds six analog signals, and outputs two output signals of the decoder 14 to two. And convert them into analog signals. The adder 17 adds the two analog signals and outputs the added signal from an output terminal 18.

[Explanation of Decoder Configuration (FIG. 2)] FIG. 2 shows a configuration diagram of the decoder 14 in the digital / analog converter shown in FIG. The decoder eliminates the influence of conversion errors of the plurality of D / A converters and the adder of the analog output signal of the D / A converter, and minimizes the number of signals input to the plurality of D / A converters. And multiple D / A
The purpose is to make the operation clock of the converter and the like as low as possible. In FIG. 2, reference numeral 21 denotes a level converter, 2
2 is a second noise shaper, 23 is a data converter, 20
1 is an adder, 202 is a second quantizer, 203 is a subtractor, 204 and 205 are delay units, 206 is a double multiplier, and 207 is a subtractor.

The decoder 14 outputs the number of gradations k (for example, k = 1
2) The input signal (the output signal (first quantized signal) of the first noise shaper 13) is input. For example, -5,-
6,..., 0, 1, 2,... The level converter 21 converts the input signal of the number of gradations k into a continuous positive integer value starting from 0. For example, if the input signal is a signal of 12 gradations of -5 to +6, 5 is added to this signal, and 1 of 0 to 11 is added.
The signal is converted into a two-tone signal (a continuous positive integer value starting from 0).

[Description of Second Noise Shaper 22 (FIG. 2)] Next, the operation of the second noise shaper 22 will be described. The second noise shaper 22 forms a second-order noise shaper. The adder 201 is a level converter 21 that is a continuous positive integer value starting from 0 (for example, 0 to 11).
And the output signal of the shaping filter (constituted by delay units 204 and 205, double multiplier 206 and subtractor 203). And
The second quantizer 202 quantizes the output signal S (addition result) of the adder 201 with a threshold k and outputs the result (second quantized signal Q), and the subtracter 203 outputs a second quantization error ( The error (ER between the addition result and the quantization result) is fed back to the shaping filter. The second quantizer 202 divides the output signal S of the adder 201 by a threshold value k (for example, k = 12) and outputs (quantizes) a quotient (integer) Q. The subtractor 203 calculates a second quantization error, and inputs the second quantization error to the above-mentioned shaping filter. The second quantization error is calculated by the following equation. Second quantization error ER = (second quantized signal Q × k) −addition result S (2)

The configuration of the shaping filter will be described.
The second quantization error ER is input to the delay unit 204.
The delay unit 204 outputs a first-order delay signal Z1 = Z− ¹ · ER of the second quantization error ER. Primary delay signal Z1 = Z
^{The −1} · ER is sent to the delay unit 205, the double multiplier 206, and the data converter 23. The delay unit 205 receives the primary delay signal Z1 = Z ⁻¹ · ER and receives the secondary delay signal Z2.
= Z− ² · ER is output. Secondary delay signal Z2 = Z- ²
The ER is sent to the subtractor 207 and the data converter 23. The double multiplier 206 generates a first-order delayed signal Z ⁻¹ · ER
And outputs 2 · Z ⁻¹ · ER. Subtractor 207
Subtracts twice the output signal 2 · Z− ¹ · ER of the multiplier 206 from the second-order delayed signal Z2 = Z− ² · ER, and subtracts the result (Z− ² · ER−2 · Z− ¹ · ER). ) (The output signal of the shaping filter).

The adder 201 has an input signal X and an output signal (Z− ² · ER−2 · Z− ¹ · E) of the shaping filter.
R) is added. Addition signal S = X + (Z− ² · ER−2 · Z− ¹ · ER) (3) By substituting equation (3) into equation 2, k · Q = X + (Z− ² · ER−2 · Z ^{− 1} · ER) + ER = X + (Z ⁻ 1−1) ² · ER (4)

When the number of gradations (the number of possible levels) of the output signal X of the first noise shaper 13 is k, the second quantizer 202 receives the input signal S of the second quantizer 202. Is −k−1 (−13 in the embodiment) or less, −2
When the input signal S is −k to −1 (−12 to −− in the embodiment).
1) is output, -1 is output when the input signal S is 0 to k-1 (0 to 11 in the embodiment), and +1 is output when the input signal S is k or more (12 or more in the embodiment). It is composed of

In the conventional example of FIG. 11, the second noise shaper group 1103 (for example, 12) and the data converter 1
107 were present. The output signal of the level converter 1102 in FIG. 11 is input to all k (12) second noise shapers 1103. Since the delay devices of the twelve second noise shapers 1103 sequentially have different initial values of 0 to 11, the quantization errors of the second noise shapers 1103 become continuous values of 0 to 11. For example, when the quantization error of the first second noise shaper is 0, the quantization errors of the other second noise shapers are 1 to 11 in order, and the quantization error of the first second noise shaper is 5 In the case of, it is a continuous value of 6 to 11, 0 to 4.

The present inventor has calculated the second quantized signal Q and the second quantized error ER of k (12) second noise shapers 1103 (FIG. 11) by one second noise shaper. It has been found that it can be obtained based on the signal of the shaper 22 (FIG. 2). Therefore, the decoder 14 of the present invention includes one second noise shaper, and k (or (k−)) signals are generated based on the delay signal of the delay unit of the second noise shaper.
Output signals of 1) or (k-2) second noise shapers are obtained and output by a device (or an easy method) smaller than the conventional one.

[Description of Data Converter 23 (FIG. 5)] The basic concept of the data converter 23 will be described. k second
(In the embodiment, only one second noise shaper actually exists). First-order delay signals Z1 (0) and 2 of the first second noise shaper
The initial value of the next delay signal Z2 (0) is set to Z1 (0) = 0 and Z1 (0).
2 (0) = 0, the initial values of the primary delay signal Z1 (1) and the secondary delay signal Z2 (1) of the second second noise shaper are Z1 (1) = 1 and Z2 (1) = 1 ,..., The primary delay signal Z1 (k−1) of the k-th second noise shaper
And the initial value of the secondary delay signal Z2 (k-1) is Z1 (k-
1) = k−1 and Z2 (k−1) = k−1 (set to a value that increases by 1 in order). In this case, the output signal S (j) of each adder 201 = X + Z2
(J) -2 · Z1 (j) is as follows ((3)
formula). S (0) = X + Z2 (0) −2 · Z1 (0) = X + 0−2 × 0 = X S (1) = X + Z2 (1) −2 · Z1 (1) = X + 1-2 × 1 = X−1 S (2) = X + Z2 (2) −2 · Z1 (2) = X + 2-2 × 2 = X−2 :: S (k−1) = X + Z2 (k−1) −2 · Z1 (k−1) = X + (k-1) -2 x (k-1) = X- (k-1) (5)

The second quantization error ER (j) = Q × k−S (j) output from each subtracter 203 is as follows (formula (2)). ER (0) = Q × k−X ER (1) = Q × k−X + 1 ER (2) = Q × k−X + 2: ER (k−1) = Q × k−X + (k−1) ( 6) When the second quantization error ER (j) is equal to or larger than k,
It becomes the value which subtracted k. For example, if ER (j) in the equation (6) becomes ..., k-1, k, k + 1, k + 2, ..., ER (j) becomes ..., k-1, 0, 1, 2, ...
··become. In another embodiment, when the second quantization error ER (j) is equal to or larger than (k-1), (k-1)
Minus the value.

The above primary delay signal Z1 becomes the secondary delay signal Z2 of the next clock, and the above second quantization error ER
Becomes the primary delay signal of the next clock. Accordingly, the primary delay signal Z1 and the secondary delay signal Z2 of the k second noise shapers 22 in the next oversampling period
Is as follows. Z1 (0) = ER (0), Z2 (0) = 0 Z1 (1) = ER (0) +1, Z2 (1) = 1:: Z1 (k-1) = ER (0) + (k− 1), Z2 (k-1) = k-1 (7)

By setting the initial values of the primary delay signal and the secondary delay signal in the k second noise shapers expressed by the equation (4) to values that increase by one in order (0
~ (K-1)), the k primary delay signals and the k secondary delay signals are always values that increase by one in order from the top (the second quantization error ER (j) is k In the above case, k is subtracted, so that 0 ≦ ER ≦ k−1 is always satisfied, and the primary delay signal of one second noise shaper 22 expressed by the equation (4) and Based on the secondary delay signal, the values of the primary delay signal and the secondary delay signal of each of the other virtual (k-1) second noise shapers can be obtained.

It should be noted that, for the second noise shapers having an appropriate shaping filter other than the second noise shaper 22 in FIG. 2, the initial value of the delay signal of each noise shaper is set to a value that increases by one in order. By doing so (0 to (k-1)), the k delayed signals always have values that increase by one in order from the top. Delay signal = k-1 to 1
Is added and when the delay signal = k, overflow occurs and the delay signal returns to 0. Therefore, by knowing the value of each delay signal of one second noise shaper, the other (k-1)
The value of each delay signal of the second noise shaper can be easily obtained. The initial values of the primary delay signal and the secondary delay signal of the k second noise shapers may be set to values that are sequentially reduced by one. In addition, any appropriate constant value can be selected, and the value can be increased or decreased by the constant value. An arbitrary appropriate value is a value in which the second quantization error ER has the same occurrence rate as all the values from 0 to (k-1).

FIG. 5 shows a data converter 23 according to the first embodiment.
FIG. 2 shows a schematic configuration of the pulse converter 32 (FIG. 3). The data converter 23 generates a third quantized signal based on the first quantized signal and the delayed signal of the second noise shaper while repeatedly adding a fixed number of 1 to the delayed signal. A second noise shaper 50, counters 51 and 52 with presets, a 12-stage shift register 53,
And the adders 54 and 55 constitute the data converter 23. The 6-bit pulse converters 56 and 57 constitute the pulse converter 32. In the first embodiment, k = 12
It is.

The operation of the data converter 23 will be described. First, the counter with preset 51 outputs the primary delay signal Z1 =
Z- ¹ · ER (output signal of the delay unit 204) is input from a preset terminal, and ZZ1 = Z1 is output (preset) from the output terminal. Similarly, the counter with preset 52 outputs the secondary delay signal Z2 = Z− ² · ER (delay unit 205
Is output from the preset terminal, and ZZ2 = Z2 is output (preset) from the output terminal. The second noise shaper 50 receives the input signal X and the output signals ZZ1 and ZZ2 of the preset counters 51 and 52.

The counters 51 and 52 with presets
Overflows at the threshold value k, and the output signal returns to 0.
That is, when one clock signal CLK1 is input while the output signal ZZ1 (or ZZ2) of the preset counter 51 (or 52) is k−1, the output signal ZZ1 is output.
(Or ZZ2) becomes 0.

The second noise shaper 50 includes an adder 50
1, a quantizer 502, a subtractor 503, and a double multiplier 504 are included. The double multiplier 504 receives the output signal ZZ1 of the counter 51 with preset and outputs 2 × ZZ1. The subtractor 503 is a counter 5 with a preset.
The output signal 2 × ZZ1 of the double multiplier 504 is subtracted from the output signal ZZ2 of 2 and the subtraction result (ZZ2-2 × ZZ)
1) is output. The adder 501 receives the input signal X and the result of the subtraction (ZZ2-2 × ZZ1), and outputs the result of the addition (X
+ ZZ2-2 × ZZ1).

The quantizer 502 calculates the addition result (X + Z
Z2-2 × ZZ1), and outputs a quantized signal Q (0). As described above, the quantized signal Q (j) is -2,
Takes any value of -1, 0, or 1. Quantized signal Q
(0) is input to the 12-stage shift register 53. 1
The two-stage shift register 53 has 12 stages of registers, each stage having, for example, 2-bit data. The output terminal of each register is connected to the input terminals of the adders 54 and 55 and to the input terminal of the next stage register. 2-bit data 0b10 (2) of each stage represents -2, 0b11 (3) represents -1, and 0b00 (0) represents 0.
And 0b01 (1) represents 1. In the 2-bit data, 2 is the complement of -2 and 3 is the complement of -1. When one clock pulse CLK2 is input, data of each stage is shifted by one stage. Quantized signal Q
(0) is loaded into the first-stage register. The above operation is performed at an oversampling frequency (for example, 2.8 MHz).
(64 fs)) 12 times the clock cycle (1/33.
9 MHz = about 30 ns).

Next, one clock pulse CLK1 is inputted to the clock input terminals of the counters 51 and 52 with preset. Each time one clock pulse CLK1 is input, the value of the output signal of each of the preset counters 51 and 52 increases by one. The output signal of the counter with preset 51 becomes ZZ1 = Z1 + 1, and the output signal of the counter with preset 52 becomes ZZ2 = Z2 + 1. The second noise shaper 50 is similar to the above,
The quantized signal Q (1) is output. Quantized signal Q (1)
Is input to the 12-stage shift register 53. One clock pulse CLK2 is input, and the quantized signal Q (0)
Shifts to the second-stage register, and the quantized signal Q (1) is loaded into the first-stage register.

Next, one clock pulse CLK1 is input to the clock input terminals of the counters 51 and 52 with preset. Each time one clock pulse CLK1 is input, the value of the output signal of each of the preset counters 51 and 52 increases by one. The output signal Q of the counter 51 with preset becomes ZZ1 = Z1 + 2, and the output signal Q of the counter 52 with preset becomes ZZ2 = Z2 + 2.
become. The second noise shaper 50 outputs the quantized signal Q (2) in the same manner as described above. If ZZ1 = Z
When 1 + j = k or ZZ2 = Z2 + j = k (k is a threshold value of the quantizer), the output signal ZZ1 or 5 of the counter 51 is obtained.
2 output signal ZZ2 becomes 0.

The above operation is repeated every clock cycle 12 times the oversampling frequency (1 / 33.9 MHz = about 30 ns). Finally, Q (0), Q (1),.
1) is loaded. Q (j) = X + ZZ2 (j) −2 × ZZ1 (j) (8) Q (0), Q (1),. 2 equal to the quantized signal Q of the noise shaper 22.

The adders 54 and 55 receive every other Q (j), add them, and add
(0) (added signal of Q (j) where j is an even number) and W
(1) Output (addition signal of Q (j) where j is an odd number). The addition signals W (0) and W (1) are represented by the following equations.

[0080]

(Equation 1)

[0081]

(Equation 2)

W (0) and W (1) are data converter 2
3 and the output signal of the decoder 14.

As described above, Q (i) is -2, -1, 0,
Or 1; however, since the addition signal W (j) is an addition value of Q (i) widely dispersed, each addition signal W (j)
(J) satisfies 0 ≦ W (j) ≦ 6. Also, W (0) +
The value of W (1) matches the input signal X of the decoder 14, but each W (j) represents the output pattern of the secondary noise shaper every oversampling period (for example, 1 / 2.8 MHz (1/64 fs)). Is output as This means that the noise in the audio band is reduced by multiplying the variation of the individual 1-bit D / A converters 33 or the error between the input terminals of the adders 34 and 17 by the second-order differential characteristic, and Improve the linearity of the converter (the linearity of the analog output signal when the digital input signal is gradually increased from 0 to the maximum value).

The values of W (0) and W (1) are 0-6.
It does not exceed the range of (gradation number 7). Therefore, as will be described later, the number of 1-bit D / A converters for converting the added signals W (0) and W (1) into analog signals can be made as small as possible (six). Further, the clock frequency of the 1-bit D / A converter can be reduced as much as possible (to be a frequency (384 fs) which is six times the oversampling frequency (64 fs)). By lowering the clock frequency of the D / A converter, heat generation of the D / A converter is suppressed, and the D / A conversion accuracy of a changing input signal is particularly improved.

[First Output Unit 15 and Second Output Unit 16
Description (FIGS. 3, 4 and 5)] FIG. 3 shows a schematic configuration of the first output unit 15 (or the second output unit 16) (FIG. 1). The first output unit 15 and the second output unit 16 have the same configuration. 32 is a pulse converter, 33 is one of six
Bit digital / analog converter (1 bit D / A
Converters) and 34 are adders. The pulse converter 32
The output signal W (j) of the decoder 14 is input (0 ≦ W
(J) ≦ 6, j = 0 or 1), 6-bit output signal R
(0) to R (5) are output from the six output terminals. First
The output unit 15 and the second output unit 16 of the dynamic
An element matching device (DEM device) is configured. By describing the first output unit 15 and the second output unit 16, a DEM device having no linearity distortion due to variations in elements will be described. 6-bit output signals R (0) to R output from six output terminals
(5) is input to each of the same number of 1-bit D / A converters 33. The output signals of the six 1-bit D / A converters 33 are added by an adder 34, which is an adder for analog signals. The added analog signal Y (j) (j
= 0 or 1) is output.

The added analog signal Y (0) (the output signal of the first output unit 15) and Y (1) (the second output unit 1)
6 are added by the adder 17 (FIG. 1), and the added signal (the output signal of the digital / analog converter) is output from the output terminal 18.

As described above, the pulse converter 32 includes the 6-bit pulse converters 56 and 57. In FIG.
The 6-bit pulse converter 56 outputs the output signal W of the adder 54.
(0) is input, and the 6-bit pulse converter 57
5, the output signal W (1) is input. W (0) input
Is W (0) = i, the 6-bit data R (0) to R (0)
(5): R (0) to R (i-1) are 1, R (i) to R
(5) is converted to 0. Specifically, the conversion is performed as follows. When W (0) = 0, R (0) = 0, R (1) = 0, R (2) = 0,... R (5) = 0 When W (0) = 1, R (0) 0) = 1, R (1) = 0, R (2) = 0,..., R (5) = 0 When W (0) = 2, R (0) = 1, R (1) = 1 , R (2) = 0,... R (5) = 0: When W (0) = 6, R (0) = 1, R (1) = 1, R (2) = 1,. .. R (5) = 1 When W (1) = i is inputted, similarly,
The bit data R (6) to R (11) are R (6) to R (R).
(I + 5) is converted to 1, and R (i + 6) to R (11) are converted to 0.

The six output terminals of the 6-bit pulse converter 56 output output signals R (0) to R (5), respectively.
The six output terminals of bit pulse converter 57 output signal R
(6) to R (11) are output. Clock pulse C that is 6 times the oversampling frequency (64 fs)
LK3 (384 fs = 16.9 MHz, for example) is input to the 6-bit pulse converters 56 and 57. The six output terminals of the 6-bit pulse converters 56 and 57 rotate the respective output signals as described below when the clock pulse CLK3 is input. R (0) → R (5), R (1) → R (0),... R (5) → R (4) R (6) → R (11), R (7) → R (6) ),... R (11) → R (10) In the oversampling period (1/64 fs), 6
The clock pulses CLK3 are input, and the above rotation is repeated six times.

FIG. 4 shows six 1-bit D / A converters (DACn0 to DACn) when W (0) = 2 and W (0) = 5.
ACn5) 33 (6 bit pulse converter 56
6 shows a timing chart of the output signals of the six output terminals of the adder 34) and the output signal Y (0) of the adder 34. As shown in FIG. 4, by rotating six signals R (0) to R (5) six times, an oversampling period (1/1) is obtained.
64 (fs), the output signal Y (0) of the adder 34 has the same value over the entire period of the six output periods (1/384 fs), and all of the six output terminals are oversampled. Six Rs within a period (1/64 fs)
(I) (0 ≦ i ≦ 5) is output once. Therefore, 6
Of the 1-bit D / A converters 33 and the adder 3
4 are completely canceled within the oversampling period (1/64 fs).

The decoder 14 converts the 12-gradation input signal X into two 6-gradation output signals W (0) and W (1).
, The first output unit 15 and the second output unit 16 (DEM device) have 12 gradations of data.
The gradation is reduced from gradation to 6 gradations. When 12 gradations are output by one DEM device, a 12-bit output signal is converted to 1/64 within an oversampling period of 1/64 fs.
It is necessary to rotate with a clock having a cycle of (64 × 12) fs = 1/768 fs, and the circuit scale is also doubled. In the first embodiment, the operation speed is reduced by half and the circuit scale is reduced by half as compared with the case where 12 gray levels are output by one DEM device. When the operation speed of the D / A converter is reduced, the dynamic D / A conversion accuracy is improved, and the amount of generated heat is also reduced.

A first feature of the present invention is that an apparatus (the present invention) which typically has one second noise shaper is capable of generating n (n is an arbitrary integer of 2 or more) output signals (n (Equivalent to the output signals of the second noise shaper). Second noise shaper 22 of the first embodiment
Is a second-order noise shaper represented by Expression (4), but is not limited thereto. For any second noise shaper 22 having a suitable shaping filter, the digital / analog device of the present invention typically comprises one second noise shaper,
An n number of output signals (corresponding to the n number of output signals of the second noise shaper) are output using the delay signal or the like of the second noise shaper. “The second noise shaper 22 having an appropriate shaping filter” means the second noise shaper 22 having a normal shaping function. For example, the second noise shaper 22 which does not operate normally such as oscillation of a feedback loop is eliminated.

In the first embodiment, the quantized signal Q of the second noise shaper 22 is not directly output, and all the output signals are the quantized signals of the second noise shaper 50. However, the quantized signal Q of the second noise shaper 22 is also output as Q (0), and the second noise shaper 50
Can output the quantized signals Q (1) to Q (11). In the first embodiment, the number of gradations k (0 to 1)
Although k (12) output signals are output from the input signal X of 1), (k-1) (11) output signals may be output.

A second feature of the present invention is that the second noise shaper 22 has a configuration represented by the following equation (4). As described above, the first output unit 15 and the second output unit 16 have relative conversion errors (errors from the average value of the output unit) ε0 and ε1, respectively, due to variations in analog elements. ε0 = W (0) − {W (0) + W (1)} / 2 ε1 = W (1) − {W (0) + W (1)} / 2 Therefore, the following equation is established. ε0 + ε1 = 0 (11)

Assuming that the analog conversion coefficient of the first output unit 15 is (A / k) · (1 + ε0) and the analog conversion coefficient of the second output unit 16 is (A / k) · (1 + ε1), the adder 17 Output signal (output signal of the digital / analog converter) YOUT = Y (0) + Y (1) is as follows. YOUT = A ・ (1 + ε0) ・ W (0) + A ・ (1 + ε1) ・ W (1) (12) Equations (9), (10) and (4) are substituted.

[0095]

(Equation 3)

In the equation (13), the second term is the equation (11)
Becomes more zero. The third term, the second quantization error ER
The sum of (i) is always constant (for example, 0 + 1 + 2 +
... + (k-1) = constant). Therefore, the second quantization error
Differentiation of the sum of differences ER (i) (1-Z^-1) Is always zero
is there. Therefore, the second derivative (1-Z^-1) ²Is always zero
You. The fourth term is the conversion errors ε0 and ε1 and the second quantization error.
The second derivative of the product of the difference ER (1-Z^-1)²It is. Second
The second derivative of the product of the quantization error ER (1-Z^-1)²Is low
The value is small at high frequencies and large at high frequencies. Toes
And the effects of the conversion errors ε0 and ε1 are small in the low frequency range.
In addition, performance degradation in the required band (conversion errors ε0 and ε1
And the noise increase due to the above) is sufficiently small. As above
In addition, the second noise filter having the characteristic represented by the expression (4)
Is a data converter that has a very small effect of the conversion error.
Implement a container.

Embodiment 2 FIGS. 6 to 9 show a digital / analog conversion apparatus and a digital / analog conversion method according to a second embodiment of the present invention. [Description of Overall Configuration of Digital / Analog Converter (FIG. 6)] FIG. 6 is a block diagram of a digital / analog converter according to a second embodiment of the present invention. In FIG. 6, 11
Is an input terminal, 12 is a digital filter, 13 is a first noise shaper, 61 is a microcomputer, 33 is 1
Bit D / A converters (DAC), 34 and 17 are adders (analog adders), and 18 is an output terminal.

Blocks having the same configuration as in the first embodiment are denoted by the same reference numerals. Therefore, input terminal 1
1, digital filter 12, first noise shaper 1
3, 1-bit D / A converter (DAC) 33, adders (analog adders) 34 and 17, and output terminal 18
Are the same as the blocks of the same reference numerals in the first embodiment.
The microcomputer 61 has an input unit 62, a central processing unit 63, a storage unit 64, and an output unit 65. The central processing unit receives the signal input from the input unit 62 or the storage unit 6
4 to process the signal read from the
5 or stored in the storage unit 64.

The microcomputer 61 executes the same function as the decoder 14 and the pulse converter 32 in the first embodiment by software. The microcomputer 61 uses, for example, a cycle (1/384 fs) of 1/6 times the oversampling cycle in the flowchart of FIG.
If fs = 44.1 kHz, processing must be performed within 59 μs). Therefore, at the time of filing, it is necessary to employ an extremely high-performance microcomputer. However, the cost of the microcomputer that can be used in the second embodiment is expected to decrease rapidly in the future. Also, the third
The other embodiment in which the microcomputer 61 is replaced with a personal computer as exemplified in the embodiment can be sufficiently put into practical use even at the time of filing. Hereinafter, a flowchart of the software operation of the microcomputer 61 will be described.

[Explanation of Flowchart of Noise Shaper Process (FIG. 7)] FIG. 7 is a flowchart of the noise shaper process (corresponding to the function of the second noise shaper 22). The initial values of the primary delay signal Z1 and the secondary delay signal are set to Z1 = 0 and Z2 = 0 (step 71).
In the software processing, the storage unit 64 plays the role of a delay unit. When a new input signal (first quantized signal) X is input, an interrupt signal is input at the same time as step 72.
The following steps are performed. An input signal (first quantized signal) X is input from the input unit 62, and the level of the input signal X is converted. For example, if X is a value between -5 and 6, then X =
Level conversion is performed by the equation of X + 5, and X is changed from 0 to 11. (Step 72). Next, the primary delay signal Z1
And the secondary delay signal Z2 is read from the storage unit 64, and
= X + Z2-2 × Z1 (S corresponds to the output signal of the adder 201 in FIG. 2), the quotient of the second quantized signal Q = S / k (Q is the output signal of the second quantizer 202) ) And a second quantization error ER = k · Q−S (ER
Corresponds to the output signal of the subtractor 203. ) Is calculated (step 73).

Next, the values of the secondary delay signal Z2 and the primary delay signal Z1 are updated. The secondary delay signal Z2 is set to Z2 = Z1, and the primary delay signal Z1 is set to Z1 = ER (step 7).
4). Next, Q, Z1, and Z2 are stored in the storage unit 64 (step 75). This completes the process. When a new input signal X is input, an interrupt signal is input at the same time, and the steps after step 72 are executed again. The above processing is executed every oversampling cycle (1/64 fs).

[Explanation of Flowchart of Data Conversion Processing (FIG. 8)] When the processing in FIG. 7 is completed (step 75 is completed), the processing in FIG. 8 is performed. FIG. 8 shows a flowchart of the data conversion process (corresponding to the function of the data converter 23). First, input signal X and step 7
The primary delay signal Z1 and the secondary delay signal Z2 stored in step 5 are read out, and the primary delay signal ZZ1 and the secondary delay signal ZZ2 for the flowchart of FIG.
= Z2 (step 81). Next, the counter j is set to j
= 0 is initialized (step 82).

Next, it is checked whether or not j ≧ 12 holds (step 83). If j ≧ 12 (j <1
2) Go to step 84. In step 84, S
(J) = X + ZZ2-2 × ZZ1 is calculated (at first j
= 0). Further, the quotient of the quantized signal Q (j) = S (j) / k is calculated. Q (j) is stored in the storage unit 64 (the above is step 84). Next, the primary delay signal ZZ1 and the secondary delay signal ZZ2 are incremented (ZZ1 = ZZ1).
+1 and ZZ2 = ZZ2 + 1). The primary delay signal ZZ1 and the secondary delay signal ZZ2 overflow at the threshold value k and return to zero. That is, the primary delay signal ZZ1 (or the secondary delay signal Z
When Z2) is incremented by one in the state of k-1, the primary delay signal ZZ1 (or the secondary delay signal ZZ2) becomes 0 (step 85). The counter j is incremented (j = j + 1) (step 86). Step 83
And the steps 83 to 86 are repeated.

If ZZ1 = 12, ZZ1 = 0
To Similarly, when ZZ2 = 12, ZZ2 = 0. Therefore, ZZ1 and ZZ2 take different values from 0 to 11.

When j = 12 (j ≧ 12), the process jumps from step 83 to step 87. When jumping to step 87, Q (0) to Q (11) are stored in the storage unit. j is the sum W of Q (j) with even values
(0) and the sum W (1) of Q (j) where j is an odd value is obtained (step 87). This is the same as the expressions (9) and (10).

[0106]

(Equation 4)

Store W (0) and W (1) (step 88). W (0) and W (1) are data converters 23
And the output signal of the decoder 14. This completes the process. The above processing is executed every oversampling cycle (1/64 fs).

[Explanation of Flowchart of Pulse Conversion Processing (FIG. 9)] FIG. 9 shows a pulse conversion processing (pulse converter 32).
Function. 3) shows a flowchart. The flowchart of FIG. 9 is executed every six times the period of the oversampling period (1/384 fs). The flowchart of FIG. 9 is started by a timer interrupt generated at a cycle of 1/384 fs. Therefore, six timer interrupts are generated within one oversampling period. In step 91, it is checked whether d <6 holds. d is a counter indicating the number of timer interrupts within one oversampling period (1/64 fs) (d = 0 to 5). If d <6 holds, the routine proceeds to step 93. If d <6 does not hold (d
= 6), and d = 0 is set (step 92).

At step 93, it is checked whether or not d 成立 0 holds. If d ≠ 0 does not hold (d =
0), and proceed to step 94. In step 94, the output signal R of the output unit 65 of the microcomputer 61
(0) to R (5) are set. W (0) is W
When (0) = i, 6-bit data R (0) to R (5)
Among them, R (0) to R (i-1) are 1, R (i) to R (i)
(5) is set to 0. Specifically, the conversion is performed as follows. When W (0) = 0, R (0) = 0, R (1) = 0, R (2) = 0,... R (5) = 0 When W (0) = 1, R (0) 0) = 1, R (1) = 0, R (2) = 0,..., R (5) = 0 When W (0) = 2, R (0) = 1, R (1) = 1 , R (2) = 0,... R (5) = 0: When W (0) = 6, R (0) = 1, R (1) = 1, R (2) = 1,. R (5) = 1 The above is step 94.

At step 95, the output signals R (6) to R (11) of the output unit 65 of the microcomputer 61
Set. If the input W (1) is W (1) = i, R out of the 6-bit data R (6) to R (11)
(6) -R (i + 5) is 1, R (i + 6) -R (11)
Is set to 0. Specifically, the conversion is performed as follows. When W (1) = 0, R (6) = 0, R (7) = 0, R (8) = 0,... R (11) = 0 When W (1) = 1, R (1) = 1 6) = 1, R (7) = 0, R (8) = 0,... R (11) = 0 When W (1) = 2, R (6) = 1, R (7) = 1 , R (8) = 0,... R (11) = 0: When W (1) = 6, R (6) = 1, R (7) = 1, R (8) = 1,. .. R (11) = 1 The above is step 95.

When step 95 is completed, the process jumps to step 97. In step 97, output signals R (0) to R (11) are output from twelve output terminals of the output unit 65 of the microcomputer 61. Further, the counter d is incremented (d = d + 1) (step 97). Thus, the processing in the case of d = 0 ends.

In step 93, if d ≠ 0 holds (d = 1 to 5), the routine jumps to step 96. In step 96, the output signals R of the twelve output terminals
(0) to R (5) and output signals R (6) to R (11) are rotated as follows. R (0) → R (1) → R (2) → R (3) → R (4) → R (5) → R (0) R (6) → R (7) → R (8) → R (9) → R (10) → R (11) → R (11) (Step 96)

Next, output signals R (0) to R (1) are output from twelve output terminals of the output section 65 of the microcomputer 61.
1) is output (the output signals of each terminal are rotated one by one). Further, the counter d is incremented (d = d + 1) (step 97). This is d ≠
The processing in the case of 0 (d = 1 to 5) ends. By executing the flowchart of FIG. 9 six times (d = 0 to 5),
One oversampling period (1 / 64f) shown in FIG.
The output waveform of s) is obtained. As described above, the second embodiment realizes a digital / analog conversion device and a digital / analog conversion method using software for a part of the processing. The digital filter 12 and the first noise shaper 13 in FIG. 6 can be replaced by processing by hardware to processing by software of the microcomputer 61.

<< Embodiment 3 >> The digital / analog converter of the third embodiment has basically the same configuration as the digital / analog converter of the second embodiment. 12 has a personal computer instead of the microcomputer 61, and has a flowchart of FIG. 12 instead of the flowchart of the data conversion processing of FIG. 8 (the microcomputer 61 may be used as it is). In the third embodiment, the digital filter 12, the first noise shaper 13, the 1-bit D / A converter 33, and the adders 34 and 17 in FIG.
It is arranged on a card inserted into a slot of a personal computer. For example, the personal computer of the third embodiment is equipped with a DVD, and when reproducing a DVD disk on which a digital audio signal is recorded,
A digital / analog conversion process, which is a part of the process of the reproduction signal, is executed by the digital / analog conversion device of the third embodiment. The analog audio signal output from the output terminal 18 is transmitted to a driving device for a built-in speaker of a personal computer, and drives the speaker.

The flowchart of FIG.
To 87 are executed in a short time using the data conversion table. A part of the data conversion table of the digital / analog converter of the third embodiment is described below (illustration). The data conversion table uses the input signal X, the primary delay signal Z1, and the secondary delay signal Z2 as address signals, and the memories specified by these address signals store the addition signals W (0) and W (1). ing. In the equation (8), the input signal X, the primary delay signal Z1, and the
The next delay signal Z2 is substituted to obtain Q (j) (Z1 and Z
2 is incremented to obtain 12 sets of Z1 and Z2,
Q based on the respective Z1 and Z2 and the input signal X
(J) is obtained. ), Q in equations (9) and (10)
W (0) and W (1) are obtained by substituting (j) (steps 82 to 8 in the flowchart of FIG. 8).
7 are the same as W (0) and W (1) obtained by the processing up to 7. ). The added signal W thus obtained
(0) and W (1) are stored in the data conversion table.

[0116]

[Data Conversion Table (Partial)] Address signal: Data signal X = 3 Z1 = 10 Z2 = 0: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 1: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 2: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 3: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 4: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 5: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 6: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 7: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 8: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 9: W (0) = 1 W (1) = 2 X = 3 Z1 = 10 Z2 = 10: W (0) = 1 W (1) = 2 X = 3 Z1 = 1 0 Z2 = 11: W (0) = 1 W (1) = 2 X = 3 Z1 = 11 Z2 = 0: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 1: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 2: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 3: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 4: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 5: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 6: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 7: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 8: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 9: W (0) = 2 W (1) = 1 X = 3 Z1 = 11 Z2 = 11: W (0 ) = 2 W (1) = 1 X = 4 Z1 = 0 Z2 = 0: W ( 0) = 2 W (1) = 2 X = 4 Z1 = 0 Z2 = 1: W (0) = 1 W (1) = 3 X = 4 Z1 = 0 Z2 = 2: W (0) = 2 W ( 1) = 2 X = 4 Z1 = 0 Z2 = 3: W (0) = 1 W (1) = 3 X = 4 Z1 = 0 Z2 = 4: W (0) = 2 W (1) = 2 X = 4 Z1 = 0 Z2 = 5: W (0) = 1 W (1) = 3 X = 4 Z1 = 0 Z2 = 6: W (0) = 2 W (1) = 2 X = 4 Z1 = 0 Z2 = 7: W (0) = 1 W (1) = 3 X = 4 Z1 = 0 Z2 = 8: W (0) = 2 W (1) = 2 X = 4 Z1 = 0 Z2 = 9: W (0) = 1 W (1) = 3 X = 4 Z1 = 0 Z2 = 10: W (0) = 2 W (1) = 2 X = 4 Z1 = 0 Z2 = 11: W (0) = 1 W (1) = 3 X = 4 Z1 = 1 Z2 = 0: W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z = 1: W (0) = 2 W (1) = 2 X = 4 Z1 = 1 Z2 = 2: W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z2 = 3: W (0 ) = 2 W (1) = 2 X = 4 Z1 = 1 Z2 = 4: W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z2 = 5: W (0) = 2 W (1 ) = 2 X = 4 Z1 = 1 Z2 = 6: W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z2 = 7: W (0) = 2 W (1) = 2 X = 4 Z1 = 1 Z2 = 8: W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z2 = 9: W (0) = 2 W (1) = 2 X = 4 Z1 = 1 Z2 = 10 : W (0) = 3 W (1) = 1 X = 4 Z1 = 1 Z2 = 11: W (0) = 2 W (1) = 2 X = 4 Z1 = 2 Z2 = 0: W (0) = 2 W (1) = 2 X = 4 Z1 = 2 Z2 = 1: W (0) = 1 W (1) = 3 X = 4 Z1 = 2 Z2 = 2: W (0) = 2 W (1) = 2 X = 4 Z1 = 2 Z2 = 3: W (0) = 1 W (1) = 3 X = 4 Z1 = 2 Z2 = 4 : W (0) = 2 W (1) = 2 X = 4 Z1 = 2 Z2 = 5: W (0) = 1 W (1) = 3 X = 4 Z1 = 2 Z2 = 6: W (0) = 2 W (1) = 2 X = 4 Z1 = 2 Z2 = 7: W (0) = 1 W (1) = 3 X = 4 Z1 = 2 Z2 = 8: W (0) = 2 W (1) = 2

A flowchart of the data conversion processing of the digital / analog converter and the digital / analog conversion method according to the third embodiment will be described with reference to FIG. 7 and 9 are the same as those in the second embodiment.
First, the input signal X and the primary delay signal Z1 and the secondary delay signal Z2 stored in step 75 are read (step 121). Next, the values of W (0) and W (1) stored at the addresses determined by the values of X, Z1 and Z2 are read (step 122). W (0) and W
The value of (1) is stored in the storage unit 64 (Step 12)
3). Thus, the same processing as in FIG. 8 is completed. Therefore, the second
Compared to the embodiment (FIG. 8), the third embodiment can complete the processing of FIG. 12 in a very short time. As for the size of the data conversion table, for example, when X, Z1, and Z2 each have 12 values, the address space of the data conversion table has a size of 12 × 12 × 12 = 1.7k. This size is very small compared to the size of the RAM of the personal computer. The process in FIG. 12 can be executed by using a general-purpose RAM of a personal computer (without using a dedicated processing device).

A recording medium on which a program for the digital / analog conversion method of the second or third embodiment is recorded may use a clock generator (for example, a built-in clock of a computer) such as an oversampling clock. ) And the D / A converter 33 and the adders 34 and 17
By loading the program into a personal computer having an analog processing circuit such as (for example, a card mounting these circuits in a slot) and executing the program, the second embodiment or The digital / analog conversion method of the third embodiment can be realized. Depending on the processing capacity of the computer, signal processing excluding processing by analog circuits and the like is divided into a part processed by hardware and a remaining part processed by a program (software). How to divide is optional. All of the signal processing except the processing by the analog circuit or the like can be processed by a program (software).

[0119]

According to the present invention, there is obtained an advantageous effect that it is possible to realize a digital / analog converter with a smaller size and higher precision than the conventional one by using a decoder smaller than the conventional one.

According to the present invention, there is obtained an advantageous effect that it is possible to realize a high-precision digital / analog conversion apparatus which is hardly affected by a relative conversion error due to variations in analog elements.

Further, by dividing the output section into a plurality of parts, the operating frequency of the output section can be reduced.
The heat generation of the output unit can be reduced, and the D / A conversion accuracy is improved. In addition, the influence of relative conversion errors due to variations in analog elements on digital / analog conversion accuracy is described in DE.
The conversion accuracy can be improved by reducing the M device.

The digital / analog conversion method of the present invention
For example, the present invention can be applied to a digital-to-analog conversion method using software on a computer or a personal computer. According to the present invention, an advantageous effect of realizing a digital / analog conversion method with a short processing time by software can be obtained. Therefore, for example, a microcomputer can realize digital / analog conversion processing by software which cannot be caught by the conventional method.
Also, by implementing the digital-to-analog conversion method of the present invention on a computer, for example, it is possible to secure a margin of processing capability of the computer as compared with the conventional method. You can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital / analog conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a decoder of the digital / analog conversion device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an output unit configuration of the digital / analog conversion device according to the first embodiment of the present invention.

FIG. 4 is a timing chart of each signal of an output unit of the digital / analog conversion device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a data converter and a pulse converter according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a digital / analog conversion device according to a second embodiment of the present invention.

FIG. 7 is a flowchart of a noise shaper process according to a second embodiment of the present invention.

FIG. 8 is a flowchart of a data conversion process according to the second embodiment of the present invention.

FIG. 9 is a flowchart of a pulse conversion process according to the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional digital / analog converter.

FIG. 11 is a block diagram showing a configuration of a decoder of a conventional digital / analog converter.

FIG. 12 is a flowchart of a data conversion process according to a third embodiment of the present invention.

[Explanation of symbols]

11, 1001 Input terminal 12, 1002 Digital filter 13, 1003 First noise shaper 14, 1004 Decoder 15 First output unit 16 Second output unit 17 Adder 18 Output terminal 21, 1102 Level converter 22, 1103 2 noise shaper 23, 1107 Data converter 201, 51 Adder 202, 52 Quantizer 203, 207, 53 Subtractor 204, 205 Delayer 206, 54 Double multiplier 32 Pulse converter 33, 1005 1 bit Digital / analog converter (DAC) 34, 1004 Adder 1106 Shaping filter 50 Secondary noise shaper calculator 55, 56 Counter with data input terminal 57 12-stage shift register 58, 59 Parallel input / serial input switching 6
Step shift register 61 Microcomputer 62 Input unit 63 Central processing unit 64 Storage unit 65 Output unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J022 AB08 BA01 BA06 CA07 CA10 CB04 CB06 CC03 CD02 CD03 CE01 CE04 CE07 CG01 5J064 AA04 BA00 BA06 BC07 BC08 BC09 BC12 BC16 BD03

Claims (8)

[Claims] 1. A digital filter for low-pass filtering an input digital signal and p times the sampling frequency of the digital signal (p is an integer of 2 or more), and a first filter for quantizing an output signal of the digital filter. A first noise shaper having a first feedback path that outputs a quantized signal and feeds back a first quantization error generated by the quantization; (M is an integer of 2 or more), a decoder that outputs an added signal, a plurality of digital / analog converters that generate a plurality of analog signals based on the m added signals, and adds the plurality of analog signals. An output unit having an adder, and a digital-to-analog conversion device comprising: an output unit that outputs a first feedback signal to the first quantized signal. A second quantizer for quantizing a signal obtained by adding or subtracting the output signal of the path to generate a second quantized signal and a second quantized error, and delaying the second quantized error. A second noise shaper having at least one delay unit for generating a delayed signal in the second feedback path; and a value of the delayed signal based on the first quantized signal and the delayed signal. The same n or (n-1) third quantized signals as the second quantized signals generated by n different (n is an integer of 2 or more) second noise shapers are output. And at least a part of the (n-1) third quantized signals and the second quantized signal or at least a part of the n third quantized signals are added. A device for generating the m added signals. Tal / analog converter. 2. The method according to claim 1, wherein the second noise shaper is k · Q =
X + (Z^-1-1) ²ER (X is the first quantized signal
And Z^-1Represents the first-order delay of the Z transform, and Q represents
2 where k is a quantization threshold and ER
Is an error signal due to quantization. )
2. A shape shaping process is performed.
6. A digital / analog converter according to claim 1. 3. The method according to claim 1, wherein each of the m number of added signals is equal to or more than n / m for every m out of the (n-1) third quantized signals and the second quantized signals. A sum signal obtained by adding the quantized signals, or an added signal obtained by adding n / m or more quantized signals for every m signals among the n third quantized signals, and 3. The digital / analog conversion device according to claim 1, wherein the digital / analog conversion device is an addition signal in which at least a part of the digitized signal is different from each other. 4. When each of the m addition signals (hereinafter referred to as the “addition signal”) has c output gradations of the addition signal (c is an integer of 2 or more) (c− 1) 1-bit output signals, the 1-bit output signals are converted to analog signals by (c-1) 1-bit digital / analog converters, and one sampling period of the addition signal Wherein each of the (c-1) 1-bit output signals is converted at least once into an analog signal by all of the (c-1) 1-bit digital / analog converters. The digital / analog conversion device according to any one of claims 1 to 3, wherein 5. The signal generator according to claim 1, wherein a value of the delayed signal is differently obtained by repeatedly adding or subtracting a fixed number to the delayed signal based on the first quantized signal and the delayed signal. Output the same n or (n-1) third quantized signals as the second quantized signals generated by the n (n is an integer of 2 or more) second noise shapers. The digital-to-analog conversion device according to claim 1, wherein 6. A digital filter step for low-pass filtering the input digital signal and p-times the sampling frequency of the digital signal (p is an integer of 2 or more), and a signal generated in the digital filter step And a first noise shaper having a first feedback step of generating a first quantized signal and feeding back a quantization error generated by the quantization.
And a decoder step of receiving the first quantized signal and generating m (m is an integer of 2 or more) sum signals, and converting the m sum signals into a plurality of digital / analog converters. A digital / analog conversion step of inputting the analog signals to generate a plurality of analog signals; and an output step having an addition step of adding the plurality of analog signals. Is a second quantizer that generates a second quantized signal and a second quantization error by quantizing a signal obtained by adding or subtracting a generated signal of a second feedback step to the first quantized signal. And a second feedback step having at least one delay step of delaying the second quantization error to generate a delayed signal; A second noise shaper step; and n (n is an integer of 2 or more) second noises having different values of the delayed signal based on the first quantized signal and the delayed signal. A signal generating step of outputting the same n or (n-1) third quantized signals as the second quantized signal generated by the shaper step; and (n-1) third quantized signals. Generating at least a part of the quantized signal and at least a part of the second quantized signal or at least a part of the n third quantized signals to generate the m number of added signals. Characteristic digital / analog conversion method. 7. The signal generation step includes the step of repeatedly adding or subtracting a constant number to or from the delayed signal based on the first quantized signal and the delayed signal to thereby change the value of the delayed signal differently. Generate the same n or (n-1) third quantized signals as the second quantized signals generated by the n (where n is an integer of 2 or more) second noise shaper steps The digital / analog conversion method according to claim 6, wherein: 8. A digital filter step for low-pass filtering the input digital signal and p times the sampling frequency of the digital signal (p is an integer of 2 or more), and a signal generated in the digital filter step And a first noise shaper having a first feedback step of generating a first quantized signal and feeding back a quantization error generated by the quantization.
And a decoder step of receiving the first quantized signal and generating m (m is an integer of 2 or more) sum signals, and converting the m sum signals into a plurality of digital / analog converters. A digital / analog conversion step of inputting the analog signals to generate a plurality of analog signals; and an output step having an addition step of adding the plurality of analog signals. Is a second quantizer that generates a second quantized signal and a second quantization error by quantizing a signal obtained by adding or subtracting a generated signal of a second feedback step to the first quantized signal. And a second feedback step having at least one delay step of delaying the second quantization error to generate a delayed signal; Having a second noise shaper step, and a signal generating step of generating the m number of added signals based on a value of a conversion table determined based on the first quantized signal and the delay signal. A digital / analog conversion method characterized by the above-mentioned.