JP2001339694A - Image signal processor and image signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image signal processor which can reduce failure of motion detection that occurs upon IP conversion of high speed scrolling screen, and its method. SOLUTION: The processor has a DSP 11. It executes motion detection, which is executed when creating interpolation data for lines without data upon IP conversion, according to the motion detection result of the data created by interpolating between the data of the current field and the data delayed by 2 fields, and between the data of the current field and the data delayed by 1 field, and the motion detection result of the previous field. It creates interpolation data by means of intra-field interpolation from the data delayed by 1 field, for the moving space. As for the static space, it creates interpolation data by means of inter-field interpolation from the current field. When the resulting value of intra-field interpolation and that of inter-field interpolation exceed the certain threshold, then it regards it to be the moving space, and executes intra-field interpolation. When the result of motion detection for the previous field is static, it makes the threshold value larger, and when it is moving, it makes it smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image signal processing apparatus, and more particularly to an image signal processing apparatus for converting an interlace signal into a progressive signal (IP conversion) and a method thereof.

[0002]

2. Description of the Related Art Many image signals such as television and video are interlaced. In contrast, computer signals are progressive, for example,
In order to simultaneously display a computer image and a television image on the same computer display, the interlaced signal must be converted to progressive. Also, interlaced signals tend to flicker if there are thin horizontal lines in the image due to their characteristics.However, progressive signals do not have such a phenomenon and are clearly displayed. Some machines also internally convert from interlaced to progressive and display progressively.

As shown in FIG. 7, in the IP conversion, an interlace signal forms one frame by two fields having line data of every other line shifted from each other. On the other hand, in the progressive signal, as shown in FIG. 8, all line data are present (blocked) from the beginning. In the case of converting the interlace signal into the progressive data, in the interlace, since only every other line exists, interpolation data is generated and output for a line having no data.

The interpolation data can be created in various ways. In general, as shown in FIG. 9, in general, a motion is detected and divided into a moving area and a stationary area. The interpolation method is used to create interpolation data from the data, and bring the data of the same line in the previous field as it is for the still area. Conventionally, in the motion detection processing when performing the IP conversion, the current field is compared with data delayed by two fields to determine.

[0005]

However, as described above, in the conventional method, when there is an image in which the character telop scrolls at high speed in the original image to be subjected to IP conversion,
The motion detection failed, and the scrolling of the character telop seemed to be trailing.

For example, when two bars scroll at a high speed, the result is as shown in FIG. It should be noted that FIG. 10 is illustrated horizontally for convenience. FIG.
10A shows the first field, FIG. 10B shows the second field, FIG. 10C shows the third field, and FIG.
FIG. 10D shows the result of the motion detection, and FIG.
The result of the conversion is shown. Here, the E line in the second field is interpolated.

In FIG. 10D showing the result of motion detection, * indicates the absolute value of the difference between the first and third fields, and + indicates the expansion of the moving area space. As a result of the IP conversion based on the conventional method, the second field remains unchanged for the O line, the motion area (*, +) is interpolated from the second field for the E line, and the static area ( ) Uses the third field as it is. However, in this case, as shown in FIG. 10E, even if the space expansion of the motion detection is expanded, it cannot be completely avoided and an error occurs.

In the result of the IP conversion based on the conventional method, similarly, in the horizontal direction, when the IP conversion is performed by the LAP, an error is conspicuous on a screen in which the character telop scrolls at high speed.

For example, when the two bars scroll at high speed, the state becomes as shown in FIG. 11A shows the first field, FIG. 11B shows the second field,
FIG. 11C shows the third field, FIG. 11D shows the result of motion detection, and FIG. 11E shows the result of IP conversion. Also in this case, FIG.
In (D), * indicates the absolute value of the difference between the first field and the third field, and + indicates the expansion of the moving region space. And in the result of IP conversion based on the conventional method,
The motion area (*, +) is interpolated from the second field, and the still area () uses the third field as it is. However, also in this case, as shown in FIG. 11E, even if the space expansion of the motion detection is expanded, it cannot be completely avoided and an error occurs.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image signal processing apparatus and method capable of reducing a failure in motion detection that occurs when performing high-speed scrolling screen IP conversion. Is to do.

[0011]

In order to achieve the above object, the present invention performs motion detection on a line where no interlace signal data exists, and creates interpolation data for a line where no interlace signal data exists. An image signal processing device for converting image data from an interlaced signal to a progressive signal based on the interpolation data, wherein the motion detection when converting the image data from an interlaced signal to a progressive signal is performed using a current field and a two-field delay. This is performed for each pixel based on the data created by interpolating from the data and the one-field delay data and the motion detection result of the previous field, and the moving area is interpolated by intra-field interpolation from the one-field delay data. The created and stationary area is Over data or two-field delay data or has a processing means for producing interpolation data from the data of the data and the two-field delay in the current field.

In the present invention, when the result of the intra-field interpolation and the result of the inter-field interpolation exceed a predetermined threshold, the processing means performs the intra-field interpolation assuming that the area is a motion area.

Further, in the present invention, the processing means automatically adjusts the threshold value according to the result of the motion detection in the previous field.

In the present invention, the processing means increases the threshold value if the motion detection result of the previous field is stationary, and decreases the threshold value if the motion is detected.

Further, in the present invention, the processing means has a SIMD control processor in which element processors are one-dimensionally and multi-parallel.

Further, according to the present invention, the SIMD control processor in which the above-mentioned element processors are multi-paralleled one-dimensionally is bit processing.

Further, according to the present invention, motion detection is performed on a line where no interlace signal data exists, interpolation data is created for a line where no interlace signal data exists, and image data is interlaced based on the interpolation data. An image signal processing method for converting a signal into a progressive signal, wherein motion detection when converting image data from an interlaced signal to a progressive signal is performed by interpolating from a current field, data of a two-field delay, and data of a one-field delay. Based on the created data and the motion detection result of the previous field,
The moving area creates interpolation data by intra-field interpolation from the data of one field delay, and the stationary area shows the data of the current field or the data of two fields delay or the data of the current field and the data of two fields delay. Interpolate between data to create interpolated data.

According to the present invention, the motion detection at the time of IP conversion is performed based on the data generated by interpolating the current field, the data of the two-field delay, the data of the one-field delay, and the motion detection result of the previous field. Done. In the moving area, interpolation data is created by performing intra-field interpolation from data delayed by one field. on the other hand,
In the stationary area, interpolated data is created by inter-field interpolation from the data of the current field. If the result of the intra-field interpolation and the result of the inter-field interpolation exceed a predetermined threshold value, the intra-field interpolation is performed assuming that the area is a motion area. If the motion detection of the previous field is stationary, the threshold is adjusted to be large, and if the motion is detected, the threshold is adjusted to be small. Thus, when the stationary state continues, the threshold value gradually increases, and the IP conversion can be performed without flicker.

[0019]

FIG. 1 is a block diagram showing an embodiment of an image signal processing apparatus according to the present invention.

As shown in FIG. 1, the image signal processing apparatus 10 has a digital signal processor (DSP) 11 as processing means and memories 12 and 13 for generating one-field delay as main components. ing.

The DSP 11 converts an image signal from an image source from an interlace signal to a progressive signal based on a parameter from a control system (not shown).
(Interlace / progressive) conversion is performed. DSP
Reference numeral 11 denotes a line without data at the time of IP conversion for converting an interlace signal into a progressive signal.
The motion detection performed when creating the interpolation data is performed based on the data generated by interpolating from the current field, the data of the two-field delay, the data of the one-field delay, and the result of the motion detection of the previous field. Creates interpolated data by performing intra-field interpolation from data delayed by one field, and creates interpolation data by inter-field interpolation from data of the current field in a stationary area.
When the result of the intra-field interpolation and the result of the inter-field interpolation, as described later, exceed a certain threshold, the DSP 11 performs the intra-field interpolation assuming that the area is a motion area. Also, the DSP 11 adjusts the threshold according to the result of the motion detection in the previous field. Specifically, if the motion detection result of the previous field is stationary, the threshold is increased, and if the motion is detected, the threshold is decreased.

The memories 12 (M 1) and 13 (M 2) for generating a delay for one field are arranged at the image data input stage of the DSP 11. An input line for image data is connected to an input terminal of the memory 12 and a first input terminal (I1) of the DSP 11. An output terminal of the memory 12 is connected to an input terminal of the memory 13 and a second input terminal (I2) of the DSP 21. The output terminal of the memory 13 is connected to the third input terminal (I3) of the DSP.

The DSP 11 is a linear array (linear array)
Type DSP, for example, SIMD (Single Instruction Stream Multiple) in which element processors are made one-dimensionally multi-parallel.
Data stream) It is composed of a control type parallel processor.

Hereinafter, the specific configuration of the SIMD control processor and the specific processing contents of the IP conversion processing in the DSP 11 will be described in order with reference to the drawings.

Basic Configuration of SIMD Control Processor Hereinafter, the configuration of the SIMD control processor will be described with reference to FIG. This SIMD control processor 100
As shown in FIG. 2, an input pointer (input skip register) 101, an input SAM (serial access memory) unit (input register) 102, a data memory unit (local memory) 103, and an ALU (Arithmetic and)
Logic Unit) Array unit 104, output SAM
It comprises a unit (output register) 105, an output pointer (output skip register) 106, and a program control unit 107.

Of these components, the input SAM 1
02, data memory unit 103 and output SAM unit 105
Is mainly composed of a memory. Input SAM unit 102,
The data memory unit 103, the ALU array unit 104, and the output SAM unit 105 constitute a plurality of (more than the number of pixels H for one horizontal scanning period of the original image) element processors 110 parallelized in a linear array (linear array) format. I do. Each of the element processors 110 (single element) has an independent processor component, and corresponds to a hatched portion in FIG. The plurality of element processors 110 are arranged in parallel in the horizontal direction in FIG.
Construct an element processor group.

Input pointer (input skip register) 1
Reference numeral 01 denotes a 1-bit shift register. Each time pixel data for one pixel of an original image is input from an external image processing device (not shown) or the like, a 1-bit signal of logical value 1 (H) is input. Pointer signal (SIP)] to designate the element processor 110 that is in charge of the input pixel data of one pixel, and
The pixel data of the corresponding original image is written to the input SAM unit 102 (input SAM cell) of 0.

That is, the input pointer 101 sets the logical value of the input pointer signal to the element processor 110 at the left end of FIG. 2 to 1 at every horizontal scanning period of the original image, and responds to the clock signal synchronized with the pixel data. The pixel data of the first input original image is converted to the SIM data shown in FIG.
The leftmost element processor 100 of the D control processor 100
Then, every time the clock signal changes by one cycle, the input pointer signal of the logical value 1 to the element processor 110 on the right is sequentially shifted rightward, and each of the element processors 110 , The image data of the original image is written one pixel at a time into the input SAM unit 102.

The input SAM unit (input register) 102
As described above, when the input pointer signal input from the input pointer 101 becomes a logical value 1, pixel data (input data) for one pixel input to the input terminal DIN from an external image processing device or the like is stored. I do. That is, the input SAM unit 102 of the element processor 110 stores pixel data for one horizontal scanning period of the original image as a whole for each horizontal scanning period. Further, the input SAM unit 102 stores the pixel data (input data) of the stored original image for one horizontal scanning period in a data memory as needed in the next horizontal scanning retrace period according to the control of the program control unit 107. Transfer to the unit 103.

Data memory section (local memory) 103
Under the control of the program control unit 107, pixel data of the original image input to the input SAM unit 102, data in the middle of calculation, and data corresponding to the logical value of the input pointer signal (SIP) input from the input pointer 101 , Constant data, etc., and output them to the ALU array unit 104.

Under control of the program control unit 107, the ALU array unit 104 performs arithmetic operation processing and logical operation on pixel data of the original image, data in the middle of operation, constant data, and the like input from the data memory unit 103. Processing is performed and stored at a predetermined address in the data memory unit 103. The ALU array unit 104 performs all the arithmetic processing on the pixel data of the original image in bit units,
The arithmetic processing is performed on data of one bit every one cycle.

The output SAM unit (output register) 105
Under the control of the program control unit 107, when the processing assigned to one horizontal scanning period is completed, the processing result is transferred from the data memory unit 103 and stored. The output SAM unit 105 outputs the stored data to the outside according to an output pointer signal (SOP) input from the output pointer 106.

Output pointer (output skip register) 1
Reference numeral 06 denotes a 1-bit shift register that selectively activates an output pointer signal (SOP) to the output SAM unit 105 and controls output of a processing result (output data).

The program control unit 107 includes a program memory, a sequence control circuit for controlling the progress of a program stored in the program memory, the input SAM unit 102, the data memory unit 103, and the output SAM unit 10.
5 is composed of "ROW" address code data (both not shown) for the memory and the like. The program control unit 107 stores a single program by these components, generates various control signals based on the stored single program for each horizontal scanning period of the original image,
All the element processors 1 through the generated various control signals
The image data is processed by interlocking and controlling the image data 10. Controlling a plurality of element processors based on a single program in this manner is referred to as SIMD control.

Each element processor (processor element) 110 is a 1-bit processor, and performs a logical operation process and an arithmetic operation process on pixel data of an original image input from an external image processing device or a preceding circuit. Then, as a whole, the element processor 110 realizes a filtering process in a horizontal direction and a vertical direction using an FIR digital filter. The program control unit 1
07 is performed with the horizontal scanning period as a cycle. Therefore, each element processor 110 divides the program of the maximum number of steps obtained by dividing the horizontal scanning period by the cycle of the instruction cycle of the element processor 110 into each horizontal line. It can be performed every scan period.

The element processor 110 is connected to the adjacent element processor 110 and has a function of performing inter-processor communication with the adjacent element processor 110 as necessary. That is, each element processor 110
According to the SIMD control of the program control unit 107,
For example, the processing can be performed by accessing the data memory unit 103 or the like of the element processor 110 on the right or left side. By repeating the access to the element processor 110 on the right side, the element processors 110 are directly connected. Data unit 1 of the element processor 110 that has not been
03 can be accessed and data can be read. The element processor 110 realizes a horizontal filtering process as a whole by using a communication function between adjacent processors.

Here, for example, when arithmetic processing between pixel data separated by about 10 pixels in the horizontal direction is required, the number of program steps becomes extremely large when communication between processors is performed. The FIR filter processing hardly includes arithmetic processing between pixel data separated by as much as 10 pixels, and mostly includes arithmetic processing on continuous pixel data. Therefore, it is very unlikely that the number of program steps of the FIR filter processing for performing inter-processor communication increases and becomes inefficient.

Each of the element processors 110 always processes the pixel data at the same position in the horizontal scanning direction exclusively. Therefore, the write address of the data memory unit 103 to which the pixel data (input data) of the original image is transferred from the input SAM unit 102 is changed at each initial stage of the horizontal scanning period to retain the input data of the past horizontal scanning period. The element processor 110
Can also filter the pixel data of the original image in the vertical direction.

Note that the input processing (first processing) of writing pixel data (input data) of the original image into the input SAM unit 102 in each of the element processors 110 is stored in the input SAM unit 102 under the control of the program control unit 107. Transfer processing of input data to the data memory unit 103, arithmetic processing by the ALU array unit 104, output SAM
Transfer process (output data) to the processing unit 105 (second
) And the process of outputting output data from the output SAM unit 105 (third process) are executed in a pipeline format with a processing cycle of one horizontal scanning period. Therefore, when focusing on input data, each of the first to third processes for the same input data requires a processing time of one horizontal scanning period. Processing time for a period is required. However, since these three processes are executed in parallel in a pipeline format, on average, processing of input data for one horizontal scanning period requires only a processing time for one horizontal scanning period.

The basic operation of the linear array type SIMD control processor for image processing shown in FIG. 2 will be described below.

In the input pointer 101, in the first horizontal scanning period (first horizontal scanning period), the logical value 1 (H) for each of the element processors 110 according to the clock synchronized with the input pixel data of the original image. Are sequentially shifted, and the element processor 110 that performs arithmetic processing on each pixel data of the original image is designated.

The pixel data of the original image is input to the input SAM unit 102 via the input terminal DIN. In the input SAM unit 102, each element processor 110 stores pixel data of one pixel of the original image according to the logical value of the input pointer signal. In all input SAM units 102 of the element processor 110 corresponding to each pixel included in one horizontal scanning period, pixel data of an original image is stored. When the pixel data for one horizontal scanning period is stored as a whole, the input process (first process) ends.

When the input processing (first processing) is completed, the input SAM section 102, the data memory section 103, the ALU array section 104, and the output SAM section of each element processor 110 according to a single program for each horizontal scanning period. 1
05 is subjected to SIMD control by the program control unit 107 to execute processing on pixel data of the original image.

That is, in the next horizontal scanning flyback period (second horizontal scanning period), each input SAM unit 102
Each pixel data (input data) of the original image stored in the first horizontal scanning period is transferred to the data memory unit 103.

In this data transfer process, the program control unit 107 activates the input SAM read signal (SIR) [to a logical value 1 (H)] and sets a predetermined row (ROW) of the input SAM unit 102 to a predetermined row (ROW). Data is selected and accessed, and further, a memory access signal (SWA) is activated, and the input SA is written so that the accessed data is written to a memory cell (described later) of a predetermined row of the data memory unit 103.
It is realized by controlling the M unit 102 and the data memory unit 103.

Next, during the horizontal scanning period, the program control unit 1
07, each element processor 1 based on the program
10 is controlled, and the data is
Output to the LU array unit 24. In the ALU array unit 104, arithmetic operation processing and logical operation processing are performed, and the processing result is written to a predetermined address of the data memory unit 103. When the arithmetic operation processing and the logical operation processing according to the program are completed, the program control unit 107
Then, the control of the data memory unit 103 is performed, and the processing result is output to the output SAM unit 105 in the next horizontal scanning retrace period.
(This is the second processing). Further, in the next horizontal scanning period (third horizontal scanning period), the output S
The AM unit 105 is controlled, and the processing result (output data) is output to the outside (third processing).

That is, the input data for one horizontal scanning period stored in the input SAM unit 102 is transferred to the data memory unit 103 as necessary in the next horizontal scanning period, stored and stored in the subsequent horizontal scanning period. Used for processing in the period.

Next, specific processing of IP conversion in the DSP 11 having the basic configuration as shown in FIG.
This will be described with reference to FIGS.

As shown in FIGS. 2 and 3, the interlace signal from the image source is input to the memory 12 and also to the first input terminal I1 of the DSP 11 (this data is referred to as DI1). The data stored in the memory 12 is input to the memory 13 and also to the second input terminal I2 of the DSP 11 (this data is referred to as DI2). Further, the data stored in the memory 13 is input to a third input terminal I3 of the DSP 11 (this data is referred to as DI3). And DS
Data DI2 of the data memory section (103 in FIG. 2) of P11
Are stored for two lines. These data are defined as L1 and L2 (ST101, ST102).

The data DI1 and DI3 are compared to determine a first absolute value of the difference (ST103). If the first absolute value is equal to or less than a preset first threshold value (threshold value 1). , The pixel is regarded as a “still area”. On the other hand, the data DI1 and data DI3 are compared, and a first absolute value of the difference is obtained (ST103). If the first absolute value is larger than the set threshold value, the pixel is regarded as a “moving area”. .

If the result of the previous field motion detection is "still", a certain constant is added to the second threshold value (threshold value 2) (ST104), and the result of the previous field motion detection is "motion". , A certain constant is subtracted from the threshold value 2 (ST105). If the threshold value 2 exceeds 255, the threshold value is set to 255 (ST106 to ST108), and 128
When it becomes smaller, it is set to 128 (ST109-
ST111). However, it is the case of 8 bits.

Then, the data DI1 and the data DI3 are compared, and if the data is equal to or smaller than the threshold value 1, as shown in FIG. 4, intra-field interpolation data R1, which is an average value of L1 and L2 data, is created (ST112). ), Data DI1, D
Inter-field interpolation data R2 which is an average value of I3 data
Is created (ST113), and the intra-field interpolation data R1 is created.
Is compared with the inter-field interpolation data R2, and a second absolute value of the difference is obtained (ST114).

If the second absolute value is larger than the threshold value 2, the pixel is regarded as a "moving region", otherwise the pixel is regarded as a "still region". Then, the space of the motion area is expanded (ST115). When the result of the motion detection of the adjacent pixels is “movement”, the result of the motion detection of the own pixel is regarded as the motion.

As a result, the pixel regarded as the “moving area” is the data L stored in the internal memory according to the detection result.
1, L2, and generates interpolation data R1.
1. Output data DI2 (ST116, ST11)
7). On the other hand, the pixel regarded as the “still area” outputs data DI1 and data DI2 (ST118).

As described above, in this embodiment,
When the result of the intra-field interpolation and the result of the inter-field interpolation exceed a predetermined threshold value, it is regarded as a motion area and the intra-field interpolation is performed. As a result, when the processing shown in FIGS. 10A to 10D is performed, FIG.
As shown in (A), no error occurs. Similarly, when the processing shown in FIGS. 11A to 11D is performed, FIG.
As shown in (B), no error occurs.

Further, in the above algorithm, 10
In the case of a still image with N / 1OFF, for example, FIG.
(C), the black squares (■) in the first and third fields are stationary at the same position, but interpolation is performed from the white squares (□) in the second field. If the difference between the white circle (○) and the black square (し た) corresponding to the same position created by Therefore, data interpolated in the second field is output as a result. As a result, the image appears to flicker. Therefore, in the present embodiment, as described above, the threshold is automatically adjusted according to the result of the motion detection in the previous field. If the result of the motion detection in the previous field is stationary, the threshold is increased, and if the result is motion, the threshold is decreased. At this time, the threshold value does not fall out of a certain range.
As a result, when the stationary state continues, the threshold value gradually increases, and the IP conversion can be performed without flickering even in the above case.

As described above, according to the present embodiment, the motion detection performed when creating the interpolation data for the line without data at the time of the IP conversion for converting the interlace signal into the progressive signal is performed based on the current field and the current field. It is performed based on the data created by interpolating from the two-field delay data and the one-field delay data and the motion detection result of the previous field, and the moving area is interpolated by inter-field interpolation from the one-field delay data. Is created, and in the stationary area, interpolated data is created by inter-field interpolation from the data of the current field.If the result of intra-field interpolation and the result of inter-field interpolation exceed a certain threshold, Assuming that it is a motion area, perform intra-field interpolation, and increase the threshold if the motion detection result of the previous field is static. , Is provided with the DSP11 to reduce the threshold if the motion, the screen of the fast scrolling I
It is possible to reduce the failure of motion detection that occurs when performing P conversion, and to perform IP conversion with high accuracy.

[0058]

According to the present invention, even when IP conversion is performed on an image accompanied by high-speed scrolling, there is an advantage that motion detection can be performed with few failures and IP conversion can be performed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image signal processing device according to the present invention.

FIG. 2 is a block diagram showing a basic configuration of a SIMD control processor constituting a DSP according to the present invention.

FIG. 3 is a flowchart for explaining the operation of the image signal processing device according to the present invention.

FIG. 4 is a flowchart for explaining the operation of the image signal processing device according to the present invention.

FIG. 5 shows an image signal processing apparatus according to the present invention;
FIG. 12 is a diagram illustrating a result of the IP conversion in a case where the processes of (A) to (D) and FIGS. 11A to 11D are performed.

FIG. 6 is a diagram for explaining an effect of automatically adjusting the threshold value based on a result of motion detection in a previous field.

FIG. 7 is an explanatory diagram of an interlace signal.

FIG. 8 is an explanatory diagram of a progressive signal.

FIG. 9 is an explanatory diagram of IP conversion.

FIG. 10 is a diagram for explaining a problem of conventional IP conversion.

FIG. 11 is a diagram for explaining a problem of the conventional IP conversion.

[Explanation of symbols]

10 image signal processing device, 11 DSP, 12, 13 ...
Memory 100 SIMD control processor 101 input pointer (input skip register) 102 input S
AM unit (input register), 103: data memory unit (local memory), 104: ALU array unit, 105: output SAM unit (output register), 106: output pointer (output skip register).

Claims (16)

[Claims] 1. A motion detection is performed on a line having no interlace signal data, interpolation data is created for a line having no interlace signal data, and image data is converted from an interlace signal to a progressive signal based on the interpolation data. An image signal processing device for converting, when converting image data from an interlaced signal to a progressive signal, a motion detection, which is performed by interpolating between a current field, data of a two-field delay and data of a one-field delay, and Performed for each pixel based on the motion detection result of the field, a moving area creates interpolation data by performing intra-field interpolation from data delayed by one field, and a stationary area uses data of the current field or 2-field delay data or current fee Image signal processing apparatus having a processing means for producing interpolation data from the de-data and two-field delayed data. 2. The image signal according to claim 1, wherein said processing means performs intra-field interpolation assuming that the result of intra-field interpolation and inter-field interpolation exceeds a predetermined threshold value as a motion area. Processing equipment. 3. The image signal processing apparatus according to claim 2, wherein said processing means automatically adjusts said threshold value in accordance with a result of motion detection of a previous field. 4. The image signal processing apparatus according to claim 3, wherein said processing means increases the threshold value if the motion detection result of the previous field is stationary, and decreases the threshold value if the motion detection result indicates motion. 5. The image signal processing apparatus according to claim 1, wherein said processing means includes a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 6. The image signal processing apparatus according to claim 2, wherein said processing means has a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 7. The image signal processing apparatus according to claim 3, wherein said processing means has a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 8. The image signal processing apparatus according to claim 4, wherein said processing means includes a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 9. The image signal processing apparatus according to claim 5, wherein the SIMD control processor in which the element processors are one-dimensionally and multi-parallel is bit processing. 10. The image signal processing device according to claim 6, wherein the SIMD control processor in which the element processors are one-dimensionally multi-parallel is bit processing. 11. The image signal processing apparatus according to claim 7, wherein the SIMD control processor in which the element processors are one-dimensionally and multi-parallel is bit processing. 12. The image signal processing device according to claim 8, wherein the SIMD control processor in which the element processors are one-dimensionally and multi-parallel is bit processing. 13. A motion detection is performed on a line where no data of the interlace signal is present, interpolation data is created for a line where no data of the interlace signal is present, and the image data is converted from the interlace signal to a progressive signal based on the interpolation data. An image signal processing method for converting, in which motion detection when converting image data from an interlaced signal to a progressive signal is performed by interpolating between a current field, two-field delayed data, and one-field delayed data. Based on the result of the field motion detection, the moving area is interpolated in the field from the data of one field delay to create interpolation data,
An image signal processing method in which a stationary area is subjected to inter-field interpolation from data of a current field, data of a two-field delay, or data of a current field and data of a two-field delay to create interpolation data. 14. The image signal processing method according to claim 13, wherein when a result of the intra-field interpolation and a result of the inter-field interpolation exceed a predetermined threshold value, the intra-field interpolation is regarded as a motion area. 15. The image signal processing method according to claim 14, wherein the threshold value is adjusted according to a result of motion detection in a previous field. 16. The image signal processing method according to claim 15, wherein the threshold value is increased if the motion detection result of the previous field is still, and the threshold value is decreased if the motion is detected.