JP2001308810A - Multi-carrier frame synchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain frame information for performing inter-multi-carrier frame synchronization in a multi-carrier communication method using the syndrome operation of an error correction code. SOLUTION: A transmitting part 1 converts a transmission signal S1 into the parallel signal of an (a) string and subsequently performs error correction coding in each parallel signal. An error correction coded signal is modulated by a modulator 13 and transmitted by a multi-carrier signal. A receiving part 2 respectively demodulates each multi-carrier signal with a demodulator 14 and subsequently corrects errors in a demodulated signal with an error correction decoder 18. The decoder 18 decides a bit, at which the syndrome operation of the demodulated signal is zero as the point of separation of a code block and defines the zero bit of the syndrome operation as a frame signal. Since there is a phase difference between multi-carriers, a frame control circuit 19 performs timing adjustment of the phase difference of the frame information and adjusts the information signal phase of a multi-carrier read from a FIFO circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-carrier frame synchronization circuit for establishing frame synchronization between carriers in multi-carrier communication (system).

[0002]

2. Description of the Related Art In a multi-carrier communication system, which is one of digital radio communication systems, a transmission signal transmitted at a frequency in a radio band is divided into a plurality of carriers having a small frequency bandwidth and transmitted. In general, multicarrier communication is used to prevent deterioration of channel quality due to fading that occurs in a propagation path. For example, when a transmission signal in one column is divided into a plurality of carriers in column a having a small frequency bandwidth,
The fading tolerance is improved by LOG10 (a) [dB]. One example of such multi-carrier communication is disclosed in Japanese Patent No.
No. 637172 (title of the invention: error correction method). Although the disclosed gazette mainly describes a technique relating to error correction, it is needless to say that it is necessary to establish frame synchronization between carriers.

FIG. 8 is a configuration diagram showing an example of a conventional multi-carrier communication system which also describes a configuration for achieving frame synchronization between carriers. FIG. 9 is a diagram showing a configuration of main signals in the configuration of FIG.

Referring to FIG. 8 and FIG. 9, the conventional multi-carrier communication system includes a transmitting unit 1A and a receiving unit 1B with a propagation path 3 interposed therebetween. This transmission unit 1A
In order to reduce the circuit scale, error correction coding is performed in a common unit (error correction encoder 10A) before dividing transmission signal S1 into parallel signal S11a for each carrier.

[0005] The transmission section 1A has a transmission rate (speed) fL
The (bit / sec) transmission signal S1 is input to the error correction encoder 10A. Here, it is assumed that the transmission signal S1 is an information signal of information sequence length k × multicarrier number a (k and a are positive integers of 2 or more). Error correction encoder 10A
Adds an n × a (n is a positive integer) error correction code to the end of the transmission signal S1 to the transmission signal S1, and sets a code rate fH (bi
t / sec) of the transmission signal S10 to the serial / parallel conversion circuit 1.
1A. A BCH code or the like, which is a block code, is used as the error correction code.

The serial / parallel conversion circuit 11A converts the serial transmission signal S10 into a series of parallel signals S11a1 to S11aa of columns (1), (2),... Each of the parallel signals S11a1 to S11aa has a code rate fHx / a (bit) of a signal obtained by adding a blank for a 1-bit frame signal to the information sequence length (k + n × a).
/ Sec). Serial / parallel conversion circuit 11A
Is a clock S11a synchronized with the timing of each frame signal position of each of the parallel signals S11a1 to S11aa.
Output c. Each of the parallel signals S11a1 to S11aa and the clock S11ac are supplied to the frame insertion circuit 12.
(1) to 12 (a).

The frame insertion circuits 12 (1) to 12 (a)
Is a predetermined frame signal (FRAME)
At the beginning (frame signal position) of the parallel signals (DATA) S11a1 to S11aa,
12a, and generates the modulated signals S121 to S1.
2a (see FIG. 9) is sent to each of the modulators 13 (1) to 13 (a). Here, the total information amount of the modulated signals S121 to S12a is obtained by adding a redundant signal n × a for error correction and a frame signal of 1 bit to each frame to the original information sequence length k × multicarrier number a. Note that F ″ (= a) is added, and the amount of information transmitted to an information signal of (k + n + 1) × multicarrier number a is finally expanded.

Each of the modulators 13 (1) to 13 (a) modulates the modulated signals S121 to S12a with a different carrier (carrier), and generates transmission signals S131 to S13a. As a modulation method, four-phase PSK modulation or the like is used. It should be noted that a well-known transmission circuit such as a power amplifier is often connected to the subsequent stage of each of the modulators 13 (1) to (a). Each of the transmission signals S131 to S13a is transmitted to the propagation path 3 via an antenna (not shown).

[0009] The receiving section 2B transmits the transmission signals S131a to S13aa transmitted from the transmission section 1A to the antennas (shown in FIG. 1) through the propagation path 3 which may cause quality deterioration such as fading. Zu). Each of the received signals S131a to S13aa generally passes through a receiving circuit (not shown) such as a low-noise amplifier, and is then demodulated for each carrier by demodulators 14 (1) to 14 (a) to generate a baseband signal. The signals S141 to S14a are generated. The baseband signals S141 to S14a are sent to the frame reproduction circuits 15 (1) to 15 (a), respectively.

Frame reproducing circuits 15 (1) to 15 (a)
Respectively reproduce frame signals S151f to S15af from baseband signals S141 to S14a,
In addition, the parallel signals S151 to S15a for each carrier obtained by separating the frame signals S151f to S15af are reproduced. The frame signals S151f to S15af are respectively sent to the frame control circuit 19A, and the parallel signals S151f to S15af are sent to the frame control circuit 19A.
S15a is FIFO (First-In First)
-Out) are sent to and stored in the circuits 16 (1) to 16 (a), respectively. To reproduce the frame signal “F”, the frame signals S151f to S15af inserted into the parallel signals S11a to S11aa by the frame insertion circuits 12 (1) to 12 (a) of the transmission unit 1A are used (FIG. 9). 9).

[0011] The frame control circuit 19A receives the parallel signal S1.
The delay information such that the frame timing of each of 51 to S15a becomes the same is transmitted to the frame signals S151f to S15a.
f and the read timing signals S191 to S19a generated from the delay information
(1) to (a). Therefore, FI
From each of the FO circuits 16 (1) to 16 (a), parallel signals S161 to S16a having the same signal timing are read.

The parallel signals S161 to S16a read from each of the FIFO circuits 16 (1) to 16 (a) are converted by a parallel / serial conversion circuit 17A into a serial transmission signal S1.
7a. The transmission signal S17a is error-corrected and decoded by an error-correction decoder 17A such as a BCH decoding circuit,
Transmission speed fL (bit / sec) input to the transmission unit 1
A transmission signal S18 having the same information as that of the transmission signal S1 is reproduced.

[0013]

In the multicarrier communication system shown in FIG. 8, it is necessary to insert a frame signal for each carrier in the receiving section in order to establish frame synchronization between the carriers (parallel signals). However, there is a disadvantage that the amount of information that can be transmitted is reduced by the amount of the frame signal.

Therefore, one of the objects of the present invention is to provide a multicarrier frame synchronization circuit with high information transmission efficiency in a multicarrier communication system.

Another object of the present invention is to provide a multicarrier frame synchronization circuit capable of shortening the time required for frame synchronization between multicarriers.

[0016]

A multicarrier frame synchronization circuit according to the present invention converts a serial transmission signal into a plurality of parallel signals subjected to error correction coding, and modulates each parallel signal. A transmitting unit for transmitting the obtained multicarrier signal to a propagation path, and after demodulating each of the multicarrier signals into a baseband signal, performing error correction decoding of the baseband signal and establishing frame synchronization between the baseband signals. To generate a decoded signal, and a receiving unit that reproduces the serial transmission signal from the plurality of decoded signals, wherein the receiving unit performs frame synchronization between the decoded signals. It is established based on code synchronization information obtained by the error correction decoding.

[0017] One of the multicarrier frame synchronization circuits may be configured such that the code synchronization information is a bit indicating zero of a syndrome operation in the error correction decoding of the baseband signal.

The multi-carrier frame synchronization circuit may have a configuration in which the parallel signal is a block code.

Another one of the multi-carrier frame synchronization circuits is that the transmission unit converts the transmission signal into a plurality of parallel signals by a serial / parallel conversion circuit, and an error correction code for each of the parallel signals. It is possible to adopt a configuration including an error correction encoder that generates a modulated signal by performing modulation, and a modulator that modulates a different carrier in each of the modulated signals.

Still another one of the multi-carrier frame synchronization circuits is that the receiving section demodulates each of the multi-carrier signals into a base band signal, and outputs an error to each of the base band signals. Correction decoding,
An error correction decoder that respectively generates the decoded signal and the code synchronization information; a frame control circuit that generates a readout signal corresponding to the code synchronization information by adjusting the phase of the code synchronization information; and temporarily stores the decoded signal. With
A configuration including a FIFO circuit for reading out the stored decoded signal by the corresponding readout signal and a parallel / serial conversion circuit for converting each of the read out decoded signals into a serial transmission signal. Can be.

The multi-carrier frame synchronization circuit may have a configuration in which one of the FIFO circuits is replaced with a delay circuit having a fixed delay amount.

[Operation] The multi-carrier frame synchronization circuit according to the present invention divides a transmission signal of digital radio communication into a plurality of carriers having a small frequency bandwidth and transmits the divided signals as frame information between the carriers. The use of the code synchronization information of the error correction code has a feature that the frame synchronization between the multicarriers can be established without adding a multicarrier frame signal to the transmission signal in the transmission unit.

[0023]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a multicarrier frame synchronization circuit according to the present invention. FIGS. 2 to 6 are diagrams showing the configuration of main signals in the embodiment of FIG. Note that the information sequence length of the error correction code is k, the error correction code length is n, and the number of multicarriers in this multicarrier communication system is a.

Referring to FIG. 1 to FIG. 6, the transmitting unit 1
Input, transmission rate (speed) fL (bit / sec)
A transmission signal (DATA) S1 having an information signal of
It is supplied to the serial / parallel conversion circuit 11. The transmission signal S1 shown in FIG. 2 has an information sequence length k × the number of multicarriers a.
Represents the reference time width (one frame) composed of the number of bits of The serial / parallel conversion circuit 11 converts the serial transmission signal S1 into a parallel transmission signal (a) of columns (1), (2),..., (A) of transmission speed fH / a (bit / sec). (Parallel signal: DATA) S111 to S11a are converted. It should be noted that the serial / parallel conversion circuit 11 matches the timing of the transmission signals S111 to S11a when converting the transmission signal S1 into the transmission signals S111 to S11a in column a.

Here, the transmission rate fH / a (bit / sec) of each of the transmission signals S111 to S11a is n bits added by the error correction encoders 10 (1) to 10 (a) at the subsequent stage. In consideration of the redundant signal (error correction code), the transmission rate is increased from fL / a (bit / sec). That is, in the serial / parallel conversion circuit 11, the transmission signal S
The speed conversion of n / k times 1 and the serial / parallel conversion to column a are performed simultaneously, and the total number of bits of the transmission signals S111 to S11a is increased by the error correction code length n × multicarrier number a. Have been. The magnified signal is usually
Simple blank data is stored. Transmission signal S111
To S11a are error correction encoders 10 (1) to 10 (1) to 10
(A). Serial / parallel conversion circuit 11
Sends the code synchronization information (equivalent to a frame signal: FREME) S111f to S11af at the same timing as the transmission signals S111 to S11a to the error correction encoders 10 (1) to 10 (a), respectively (FIG. 2).

The error correction encoders 10 (1) to 10 (a)
Of the transmission signals S111 to S11a are error-correction-coded by replacing the blank data continuous for each block with an error-correction code, and an error-correction code (modulated signal) S10
1 to S10a are generated. The error correction code includes BC
A code word of a block code such as an H code is used. Further, each of the error correction encoders 10 (1) to 10 (a) receives the code synchronization information S111f to S11af at the same timing from the serial / parallel conversion circuit 11, and converts the codeword of the error correction code of each carrier. Make the same phase. The configuration examples and operations of the error correction encoders 10 (1) to 10 (a) are described in “Code Theory, written by Hideki Imai, edited by the Institute of Electronics, Information and Communication Engineers, for example, pp10
5-134, published in March 1990 ".
The error correcting codes S101 to S10a are
(1) to (a).

Each of the modulators 13 (1) to 13 (a) modulates a different carrier (carrier) with a modulation signal S101 to S10a, respectively, and transmits transmission signals S131 to S13a,.
That is, a multicarrier signal is generated. As a modulation method, four-phase PSK modulation or 256 QAM that preserves the symmetry of the modulation signals (codewords of the transmission signal S1) S101 to S10a is used. It should be noted that a known transmission circuit (not shown) such as a power amplifier is often connected to each subsequent stage of the modulators 13 (1) to 13 (a). Each of the transmission signals S131 to S13a, which are multicarrier signals, is an antenna (not shown).
Is transmitted to the propagation path 3 via the.

Since the transmitter 1 does not insert a frame signal by the frame insertion circuit, the transmitter 1 has a feature that more information for the frame signal can be transmitted than the transmitter 1A shown in FIG. 8 in the same transmission time. That is, when transmitting the same information signal, the code rate f of the transmitter 1 is
H / a (bit / sec) is the code rate fH of the transmitter 1A.
It may be delayed by x / a (bit / sec) by a frame signal.

The receiving unit 2 can cause each of the transmission signals S131 to S13a having a transmission rate of fH / a (bit / sec), which has been converted into a multicarrier by the transmitting unit 1, to cause quality deterioration or phase change due to fading or the like. Received from the antenna (not shown) are received signals S131a to S13aa that have passed through the propagating propagation path 3. Received signals S131a-S
Each of 13aa generally passes through a receiving circuit such as a low noise amplifier, and is then demodulated for each carrier (each of the received signals S131a to S13aa) by demodulators 14 (1) to 14 (a) to obtain a baseband signal. (DATA) S141 to S14a
Is generated. The baseband signals S141 to S shown in FIG.
14a undergoes a different phase (delay time) change for each carrier due to the propagation path 3 having fading or the like. The baseband signals S141 to S14a are sent to error correction decoders 18 (1) to 18 (a), respectively.

The error correction decoders 18 (1) to 18 (a)
Of the baseband signals S141 to S14a are error-corrected and decoded, and the decoded signals (DATA) S181 to S1 are decoded.
8a (see FIG. 4). Note that an error correction decoder 18 (1) that corrects an error in a block code such as a BCH code.
18 (a) show the well-known BM method and B
A CH decoding circuit is appropriate (coding theory, Hideki Imai, edited by the Institute of Electronics, Information and Communication Engineers, for example, pp 151-190, Heisei 2
Published March 2003). The decoded signals S181 to S18a are FIFO
The signals are supplied to the circuits 16 (1) to 16 (a) and temporarily stored (stored).

The error correction decoders 18 (1) to 18 (a)
Has a function of generating frame signals S181f to S18af, which are frame information of the decoded signals S181 to S18a. Error correction decoders 18 (1) -1
8 (a), the baseband signals S141 to S1
A syndrome operation is performed for each of 4a, and a code position (code synchronization information) where the syndrome becomes zero is detected.
Then, the baseband signal S14 is obtained from the code synchronization information.
Judgments of codewords 1 to 14a, that is, frame division positions are determined, and frame signals (FREME) S181f to S18af are created at bit positions next to the divisions (see FIG. 4). Each of the frame signals S181f to S18af is sent to the frame control circuit 19. At this point, the frame signals S181f to S18af are not yet synchronized with each other, and have different input phases.

Here, the frame signals S181f-S18
The process of creating af will be briefly described. Each of the error correction encoders 10 (1) to 10 (a) of the transmission unit 1 divides a generator polynomial for each of the transmission signals S111 to S11a, which are information sequences, and divides the remainder into transmission signals S111 to S111. Error correction codes S101 to S10a, which are codewords added to each of S11a and error-corrected, are generated. On the other hand, the error correction decoders 18 (1) to 18 (1)
8 (a), the error correction codes S101 to S10
a corresponding to baseband signals S141 to S1
4a is divided by a generator polynomial to find the remainder. If there are no errors in the baseband signals S141 to S14a, the remainders are zero. Also,
If there is a remainder, the corresponding baseband signal S1
Since there is a signal error in 41 to S14a, a signal error position is estimated for each of the baseband signals S141 to S14a from the value, and error correction is performed.

In the embodiment shown in FIG. 1, since the transmitting section 1 does not insert a frame signal, each of the baseband signals S141 to S14a in the receiving section 2 is a continuum of the above codeword. A method of correctly finding a break of the continuum of the code word, that is, a method of achieving frame synchronization between multicarriers in column a according to the present embodiment, wherein the break of the code (word) is determined by the frame signals S181f to S18a
f or the generation position of each frame pulse.

Error correction decoders 18 (1) to 18 (a)
Perform a syndrome operation (remainder operation) with a 1-bit shift on each of the baseband signals S141 to S14a, respectively.
The syndrome calculation result becomes zero only when the corresponding signal in 14a has no error and the syndrome calculation is performed from the beginning of the codeword. Even when there is a signal error in the baseband signals S141 to S14a, each of the error-correction decoders 18 (1) to 18 (a) can perform the baseband signal by performing appropriate forward protection and backward protection. From each of the signals S141 to S14a, the correct frame signal S
181f to S18af can be respectively generated.

The frame control circuit 19 controls one of the frame signals S181f to S18af so that the timings of the frame signals S181f to S18af supplied from the error correction decoders 18 (1) to 18 (a) coincide. Timing adjustment is performed such that the delay is adjusted for some or all of the units. This adjustment is desirably based on the frame signal with the most delayed phase, that is, the frame signal S182f in the example of FIG.

The frame signal S19 whose timing has been adjusted
Each of 1 to S19a is a FIFO circuit 16 (1) to 16
(A) and temporarily stored decoded signal S
Parallel signals (DATA) S161 to S1 in which frames 181 to S18a are frame-synchronized (having the same phase) between the carriers.
The data is read out to the parallel / serial conversion circuit 17 as 6a (see FIG. 5). It is to be noted that since it is more advantageous to perform the speed conversion of the information signal in the common unit as much as possible in terms of circuit scale and the like, the parallel signal S161 from which the error correction code has been omitted in the frame control circuit 19 which is the common unit of each carrier is generally used. The speed conversion (that is, the clock frequency conversion) control of S16a is also performed.
That is, the FIFO circuits 16 (1) to 16 (a) also perform the speed conversion of the baseband signals S141 to S14a, respectively.

The parallel-to-serial conversion circuit 17 converts the parallel signals S161 to S16a in the parallel format into the serial format and converts the parallel signals S161 to S16a into the serial format, and transmits the same transmission speed fL (bit / sec) as the transmission signal S1 supplied to the transmission unit 1. The transmission signal S18, which is the information signal of, is reproduced (see FIG. 6).

As described above, in the multi-carrier frame synchronization circuit of the multi-carrier communication system shown in FIG. 1, even if the transmitting unit 1 does not transmit a frame signal, the error correction decoders 18 (1) to 18 of the receiving unit 2 There is a feature that frame synchronization between multicarriers can be established by the syndrome calculation by each of (a).

Further, in the frame synchronization circuit, since it is not necessary to provide a frame reproduction circuit in series with the error correction decoder in order to extract the frame information, it is possible to shorten the time required for frame synchronization between multicarriers. There is.

Further, in this frame synchronization circuit, some of the received signals S131a to S13aa received by the receiving unit 2, for example, a severe reception failure occurs in the received signal S131a, and the error correction decoder 18 (1) operates normally. Also, when the normal frame signal S181f cannot be output, the normal frame signal S18 (y) f is output from the sequence of the other normal received signals (the y sequence: S13y). S18yf) is saved. Therefore,
From the received signal of the S13y sequence, a correct decoded signal S18y is obtained.
Is obtained. However, information signals such as a decoded signal S181 of a sequence that cannot output a normal frame signal are lost.

FIG. 7 is a block diagram showing another embodiment of the multicarrier frame synchronization circuit according to the present invention.

In the embodiment of the multicarrier frame synchronization circuit shown in FIG. 7, the FIFO 16 (1) of the receiving section 2 in the embodiment of FIG. 1 is replaced with a delay circuit 20 having a fixed delay amount. In the receiving unit 2A of FIG. 7, the parallel signal S201 output from the (1) column delay circuit 20 is used as a timing reference for the other parallel signals S162 to S16a. Then, the delay amount of the delay circuit 20 to which the decoded signal S181 is supplied is set to be larger than the maximum value of the delay amount that may cause other decoded signals S182 (2) to S18a. Then, the frame control circuit 19 outputs the decoded signals S182 to S1.
8a, the FIFOs 16 (2) to 20
(A) Parallel signals S162 to S16a which are signals passing through
Of the parallel signal S2 which is the output of the delay circuit 20
01 can be easily adjusted to the same timing.
The reference decoded signal (S18) is (1) to (1).
Any column in (a) may be used. This embodiment is characterized in that an inexpensive line or logic circuit can be used in place of the expensive FIFO circuit 16 (1).

[0044]

As described above, the frame synchronization circuit according to the present invention uses the result of the syndrome calculation by the error correction decoder as frame information in order to synchronize the frames between multicarriers in the receiving unit. There is an effect that there is no need to insert a frame signal and the transmission speed of a transmission signal is not reduced.

Further, the frame synchronization circuit according to the present invention
Since it is not necessary to provide a frame reproducing circuit in series with the error correction decoder in order to extract the frame information, there is an effect that the time required for frame synchronization between multiple carriers can be reduced.

Further, since the frame synchronization circuit according to the present invention performs error correction independently for each carrier (received signal), for example, when a severe line degradation occurs in one carrier and frame synchronization cannot be achieved. This also has the effect that normal signal reception is performed in other normal carrier sequences.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a multicarrier frame synchronization circuit according to the present invention.

FIG. 2 is a first diagram showing a configuration of a main signal in the embodiment of FIG. 1;

FIG. 3 is a second diagram showing a configuration of a main signal in the embodiment of FIG. 1;

FIG. 4 is a third diagram showing a configuration of a main signal in the embodiment of FIG. 1;

FIG. 5 is a fourth diagram showing a configuration of a main signal in the embodiment of FIG. 1;

FIG. 6 is a fifth diagram showing a configuration of a main signal in the embodiment of FIG. 1;

FIG. 7 is a configuration diagram showing another embodiment of the multicarrier frame synchronization circuit according to the present invention.

FIG. 8 is a configuration diagram showing an example of a conventional multi-carrier communication system that also describes a configuration for achieving frame synchronization between carriers.

FIG. 9 is a diagram showing a configuration of a main signal in the configuration of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Transmission part 2, 2A reception part 3 Propagation path 10 (1), 10 (2), 10 (a) Error correction encoder 11 Serial / parallel conversion circuit 13 (1), 13 (2), 13 (a) Modulator 14 (1), 14 (2), 14 (a) Demodulator 16 (1), 16 (2), 16 (a) FIFO (F
IFO) circuit 17 Parallel / serial conversion circuit 18 (1), 18 (2), 18 (a) Error correction decoder 19 Frame control circuit 20 Delay circuit

Claims (6)

[Claims] A transmitting unit for converting a serial transmission signal into a plurality of parallel signals subjected to error correction coding and transmitting a multicarrier signal modulated for each of the parallel signals to a propagation path; After demodulating each of the multicarrier signals into a baseband signal, an error correction decoding of the baseband signal and a frame synchronization between the baseband signals are performed to generate a decoded signal. A multi-carrier frame synchronization circuit comprising: a reception unit that reproduces the serial transmission signal, wherein the reception unit performs frame synchronization between the decoded signals based on code synchronization information obtained by the error correction decoding. A multi-carrier frame synchronization circuit characterized by establishing. 2. The apparatus according to claim 1, wherein the code synchronization information is a bit indicating zero of a syndrome operation in the error correction decoding of the baseband signal.
A multicarrier frame synchronization circuit as described. 3. The multi-carrier frame synchronization circuit according to claim 2, wherein said parallel signal is a block code. 4. A serial / parallel conversion circuit for converting the transmission signal into a plurality of parallel signals, and an error correction encoder for generating a modulated signal by performing error correction coding on each of the parallel signals. 2. The multi-carrier frame synchronization circuit according to claim 1, further comprising: a modulator for modulating different carriers in each of the modulation signals. 5. The receiver according to claim 1, wherein the receiver demodulates each of the multicarrier signals into a baseband signal, and performs error correction decoding on each of the baseband signals.
An error correction decoder that respectively generates the decoded signal and the code synchronization information; a frame control circuit that generates a readout signal corresponding to the code synchronization information by adjusting the phase of the code synchronization information; and temporarily stores the decoded signal. With
A FIFO circuit for reading the stored decoded signal by the corresponding read signal; and a parallel / serial conversion circuit for converting each of the read decoded signals into a serial transmission signal. The multi-carrier frame synchronization circuit according to claim 1. 6. The multicarrier frame synchronization circuit according to claim 5, wherein one of said FIFO circuits is replaced by a delay circuit having a fixed delay amount.