JP2001306411A - Information processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of performing sure parity check even when a general memory having a bit width less than the bit width for the parity bits of capacity matching with a system scale is used. SOLUTION: A memory control part 30 accesses a memory 20 twice by one writing cycle of a CPU 10, writing data from the CPU 10 are written in a 1st address and parity bits are generated simultaneously with the writing operation at the first time and the generated parity bits are written in a 2nd address at the 2nd time. The memory is read out twice by one reading cycle of the CPU 10, the 2nd address is generated and read data are latched at the 1st time, the 1st address is generated at the 2nd time and the read data and the latched data are combined to perform parity check. When there is an abnormality, the CPU 10 is allowed to generate an interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and an information processing method for exchanging data via a bus having a predetermined data bit width, for example, information having no parity bit in data bits constituting the bus. With respect to the processing device and the information processing method, the parity and the
The present invention relates to an information processing apparatus and an information processing method in which a check system is implemented by a general-purpose memory without using a dedicated memory with a parity bit.

[0002]

2. Description of the Related Art Conventionally, in an information processing system including a microprocessor system, a method called parity check has been performed in order to monitor the authenticity of data on a data bus.

For example, when the processing data width is n bits, a data bus or the like is composed of (n + 1) bits, one of which is reserved as a parity bit, and the parity bit is set according to the content of the processing data. It is determined whether the parity bit is correctly set on the side that has received the (n + 1) -bit data. If the parity bit is not set correctly, the data is erroneous data. I was handling it.

For example, if the processing data (true data) is 8 bits, the data of the ninth parity bit is added so that the sum of each bit value of "1" becomes an odd number or an even number. Was determined to be true or false.

For this reason, in the conventional system, if the bit width (true data portion) of the data portion to be processed is 8 bits, a memory having a parity bit width of 9 bits in total is used to store the data. It had to perform access control and exchange data.

In order to adopt the above-described conventional data access method, in an information processing apparatus having a data processing bit width of 8 bits, it is necessary to use a memory whose access unit is 9 bits.

[0007]

However, a memory having a 9-bit access unit used in an apparatus having a data processing unit of 8 bits has been discontinued due to the circumstances of the memory maker, and the availability of the memory has been determined. This is expected to be impossible, and when searching for a substitute, only expensive large-capacity products can be selected.

[0008] In this case, only a small part of the memory is used, and there is a problem that a large area is wasted (unused area) and the cost is increased.

[0009]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems. For example, it is possible to ensure the reliability of transmitted / received data, and at the same time, to use a general-purpose capacity suitable for a system scale. An object is to provide an information processing apparatus and an information processing method that can use a memory.

As one means for achieving the above object, for example, the following arrangement is provided.

That is, the memory can be accessed twice in response to one memory access request from the data processing side,
An information processing apparatus for exchanging data via a bus having a predetermined data bit width, wherein in response to a data write request to the memory, write request data is written to a first address of the memory in a first access. Data write means for writing parity check bits from write request data and writing the generated parity check bits to a second address of the memory in a second access; and Second
Check bit read means for reading a parity check bit from an address of the memory; data read means for reading the write request data from the first address in a second access in response to a data read request to the memory; And notifying means for notifying a check result of performing a parity check using the write request data read by the reading means and the check bit read by the check bit reading means.
Is generated from one address data from the processing side of the data.

Alternatively, the memory can be accessed twice in response to one memory access request from the data processing side,
An information processing apparatus for transmitting and receiving data via a bus having a predetermined data bit width, wherein the first and second addresses are generated from one address data from a processing side of the data, and the first and second addresses are transmitted to the memory. For a data write request,
Write request data is stored in the first memory in the first access.
At the same time, a parity check bit is generated from the write request data, and the generated parity check bit is written to the second address of the memory in the second access, and the data read request to the memory is In the first access, a parity check bit is read from the second address, and in the second access, the write request data is read from the first address, and the parity check bit is read using the read write request data and the parity check bit. It is characterized by comprising means for performing a check and notifying a check error to the data processing side when a parity check error occurs.

[0013]

With the above arrangement, there is provided an information processing apparatus and an information processing method capable of securing the reliability of transmitted / received data and using a general-purpose memory having a capacity suitable for a system scale.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a memory access control unit in an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 10 denotes a CPU for controlling the entire information processing apparatus according to the present embodiment, which can be constituted by, for example, a single microprocessor IC chip. The CPU 10 also controls access to the memory 20. The data bit width of the processing data in the CPU 10 (the data bit width at which the memory can be accessed at one time at the time of memory access) has a configuration of 8 bits.

Reference numeral 20 denotes a general-purpose memory that can be used in this embodiment and that can access data in 8-bit units. Reference numeral 30 denotes a memory control unit that controls access to the memory 20 when controlling memory access between the CPU 10 and the memory 20. This embodiment is characterized by the memory access control unit 30.

Reference numeral 40 denotes a host, which is composed of, for example, a large-sized computer system, and is connected to the system of this embodiment via an external bus. The data bus with the host 40 is a parallel bus having a bit width of 9 bits (D0 to D8) having a parity bit, and is configured to be able to directly access the memory 20 without passing through the CPU 10.

More specifically, when the CPU 10
(A) / Read (RD) / Write (W)
R) are controlled.

At this time, the interface according to the present embodiment is configured to handle 9-bit data including parity bits even if the data bus width is a parallel 8-bit data bus.

That is, in this embodiment, the access area of the memory 20 is configured to be divided into two types of areas, and the first access area is used to secure the reliability of the access data. Parity for
The storage area for the data to be checked and the second area are the storage areas for the data for which no parity check is performed on the access data.

At the time of memory access to a data storage area where parity check is not performed on access data, the memory control unit 30 supplies the address data from the CPU 10 and the memory control signals / RD and / WR to the memory 20 as they are. Area for normal memory access.

At the time of memory access (including the time of DMA) to a data storage area (parity bit effective area) for performing parity check on access data, memory control unit 30 transmits a memory access control signal from CPU 10. The address signal A0 to the memory 20 is switched to "H / L" (second address / first address) during one memory access cycle by / RD, that is, (RD-) and / WR, that is, (WR-). In accordance with the timing, in the case of a read cycle, / RDM, that is, (RDM-) is output twice to the memory 20 in response to one assertion of / RD, and the memory 20 is accessed twice. In response to the assertion, / WDM, that is, (WDM-) is output to the memory 20 twice and accessed twice.

The address bits of the address bus of this embodiment used by the CPU 10 are A0 to AX.
Address bits A0 to A on the address bus
X is connected to address terminals A1 to A (X + 1) of the memory 20, and an address bit from the memory control unit 30 is connected to the address terminal A0 of the memory 20. CPU1
The data bits of the data bus used at 0 are 8 of D0 to D7.
The 8-bit data bus is connected to the memory control unit 30, and 7 bits D1 to D7 are stored in the memory 20.
, D1 to D7, and D0 / D8 from the memory control unit 30 to D0 of the memory 20.

The memory control unit 30 is connected to a data bus and an address bus, and receives memory access control signals / RD and / WR from the CPU 10. From the memory control unit 30 of the present embodiment, the data bit for memory and the address bit A0 of the memory 20 are connected, and the control signals / RDM and / W of the memory 20 are further connected.
DM is supplied.

The memory 20 is directly connected to an external bus from the host, and is configured to enable access to data having a parity bit D8.

Next, the detailed configuration of the memory control unit 30 is shown in FIG.
Shown in

In FIG. 2, reference numeral 301 denotes address data decoded on the address bus to determine whether or not the CPU 10 has performed memory access to a data storage area (parity bit valid area) for performing parity check on access data. This is an address decoder for detection.
Reference numeral 302 denotes a memory address generator that controls the address bit A0 in accordance with the detection result of the address decoder 301.

303 is a memory timing generator,
At the time of memory access to the parity bit effective area in accordance with the detection result of the address decoder 301, the CPU 10
The access control signals / RDM and / WRM to the memory 20 are asserted twice from the memory access control signals / RD and / WR to access the memory 20 twice.
Memory access control signals / RD and / WR from U10
Access control signal / R to memory 20 at the same timing as
Outputs DM and / WRM.

Reference numeral 304 denotes a second memory access at the time of memory access to the parity bit effective area;
This is a parity bit generation unit that generates a parity bit D8 to be written to 0 (hereinafter also referred to as “write”).
Numeral 305 compares the data read in the second access (hereinafter also referred to as "read") with the parity bit D8 read in the first access at the time of memory read access to the parity bit effective area. A parity check unit that performs a parity check, issues an interrupt request to the CPU 10 if the parity check error occurs, and reports the parity check error.

Reference numeral 306 denotes a D0 / D8 synthesizing unit,
The D8 synthesizing unit 306 switches between the true data D0 and the generated parity bit D8 in accordance with the timing of the / WRM output generated by the memory timing generating unit 303 at the time of write access to the parity bit effective area. To the output signal of D0.

Reference numeral 307 denotes a parity bit discriminating unit;
08 is a parity bit separation unit, 309, 310, 311
Is a gate. Memory timing generator 30 described above
3 controls the parity bit discrimination unit 307, the parity bit separation unit 308, and the gates 309, 310, and 311 also control the memory timing generation unit 303.

The parity bit determination unit 307 determines whether the current access is a write or read to the memory of the CPU 10 or an external (for example, from the host) write or read to the memory. Select D8 to be checked and select parity bit separation unit 3
Send to 08.

The parity bit separation unit 308 latches (temporarily holds) data read in the first access at the time of memory read access to the parity bit effective area, and separates the data into parity bits and true data. Then, the true data is sent to the gate 309 that controls the output of D0 of the data bus, and the parity bit D8 is sent to the parity bit discriminating unit 307.

In the present embodiment, the above configuration is provided. For example, at the time of memory writing to the parity bit effective area, the data bus from the CPU 10 is used at the memory writing timing at the time of the first / WRM output in the first half. The valid data to be written to the memory 20 output above is passed through the D0 / D8 synthesizing unit 306 and the gate 310 and the address bus A0 of the memory 20 is set to A1 of “0” as it is.
Write to the memory address specified by Ax.

At the same time, the parity bit generation section 304 generates a parity bit corresponding to the data content from the data on the data bus, and supplies the parity bit to the parity bit determination section 307. In the parity bit determining unit 307, the supplied parity bit is used as the parity check unit 30.
5 is sent to the D0 / D8 synthesizing unit 306, and is passed through the gate 310 at the memory write timing at the time of the second / WRM output in the second half. A1 is supplied to the memory 20, and the address bus A0 of the memory 20 is "1" A1
Write to the memory address specified by Ax.

As a result, within one memory write cycle period of the CPU 10, write control is performed on two consecutive addresses, true data (actual processing data) is written for the first time, and D0 / D8 is written for the second time. Synthesizing unit 3
06 stops the supply of the true data to the memory 20, and the parity bit generated from the true data can be written.

With this control, in the write cycle, the true data is written to the even address which is the first address by the first assertion, the parity bit is generated at the same time, and the second address is generated at the second assertion. The generated parity bit can be written to an odd address. This parity bit is, for example, D0
Bit or D7 bit. However, any bit of the data bus may be assigned.

In a read cycle, an odd address is generated at the first assertion and the read data at this time is latched, and an even address is generated at the second assertion and latched with the read data at this time. The parity check is performed together with the stored data, and an interrupt can be generated in the CPU 10 if there is an abnormality.

As described above, according to the present invention, the memory control unit 30 accesses the memory 20 twice in one write cycle of the CPU 10, writes the write data from the CPU 10 to the even address at the first time, and simultaneously A bit can be generated and the generated parity bit can be written to an odd address a second time.

In one read cycle of the CPU 10, two
The memory is read twice, an odd address is generated first time, the read data at this time is latched, and an even address is generated second time, and the read data at this time is combined with the latched data. A parity check is performed, and if there is an abnormality, an interrupt can be generated in the CPU 10.

For this reason, even if a general-purpose memory having no bit width corresponding to the parity bit having a capacity corresponding to the system scale is used, the reliability of data transmitted and received can be ensured, and a reliable parity check can be performed. It is possible to provide an information processing device that can perform the information processing.

In the above description, the case where the memory is controlled by the CPU 10 and the host 40 has been described. However, the same memory control is performed for the memory access from various I / O devices that process data. It is needless to say that the parity check can be performed in the same manner. Further, in the above description, the first address is an even address and the second address is an odd address. However, the present invention is limited to the above example. However, for example, D0 to D3 may be set as the first address, and D4 to D7 may be set as the second address, and the present invention can be applied to an information processing apparatus that performs all kinds of memory access.

[0043]

As described above, according to the present invention, a reliable parity check can be performed even when a general-purpose memory having no bit width for a parity bit having a capacity suitable for the system scale is used. An information processing device can be provided.

Therefore, it is possible to use a general-purpose memory which is expected to be stably supplied at a low price, and to assemble a system which maintains the same security as before.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a CPU and a memory access control unit according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a detailed configuration of a memory control unit according to the embodiment.

[Explanation of symbols]

 Reference Signs List 10 CPU 20 Memory 30 Memory control unit 301 Address decoder 302 Memory address generation unit 303 Memory timing generation unit 304 Parity bit generation unit 305 Parity check unit 306 D0 / D8 synthesis unit 307 Parity bit determination unit 308 Parity bit separation unit 309, 310 , 311 gate

Claims (2)

[Claims] 1. An information processing apparatus which enables a memory to be accessed twice in response to one memory access request from a data processing side, and transmits and receives data via a bus having a predetermined data bit width. In response to a data write request to the memory, data write means for writing write request data to a first address of the memory in a first access and generating a parity check bit from the write request data; Check bit writing means for writing the generated parity check bit to a second address of the memory; check bit reading means for reading the parity check bit from the second address in a first access; and a data read request to the memory. On the other hand, in the second access, the Data reading means for reading only the request data, and notifying means for notifying a check result of performing a parity check using the write request data read by the data reading means and the check bit read by the check bit reading means. An information processing apparatus, wherein the first and second addresses are generated from one address data from the data processing side. 2. An information processing method in an information processing apparatus which enables a memory to be accessed twice in response to one memory access request from a data processing side and transmits and receives data via a bus having a predetermined data bit width. Wherein the first and second addresses are generated from one piece of address data from the data processing side, and in response to a data write request to the memory, write request data is written to the memory by a first access. A parity check bit is generated from the write request data while writing to the first address, and the generated parity check bit is written to the second address of the memory in the second access, and the data read request to the memory is Reading the parity check bit from the second address in the first access, Reading the write request data from the first address by access, performing a parity check using the read write request data and a parity check bit, and notifying a check error to the data processing side when a parity check error occurs. An information processing method characterized by the following.