JPH05120211A - Data bus width controller - Google Patents

Abstract

PURPOSE:To provide the data width controller which inputs and outputs data by controlling the bus width of a central processing unit by specifying an address only once when the bus width of the central processing unit is an integral multiple of the bus width of a storage device. CONSTITUTION:In a write cycle, the output data of the central processing unit 1 are arrayed and temporarily stored in write registers 19-22 and while the address of the storage device 2 is controlled by an address sequencer 18 and an address counter control circuit 17, a WR sequencer 15 outputs the data in the write registers 19-22 to the data bus 28 of the storage device 2. In a read cycle, while the address of the storage device 2 is controlled by the address counter 18 and address counter control circuit 17, the data are arrayed in read registers 23-26 and temporarily stored, and the data are read by the central processing unit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention intervenes between a central processing unit having a data bus having a plurality of bits and a storage device having a data bus having a smaller number of bits than the data bus. The present invention relates to a data bus width control device for converting width and inputting / outputting data.

[0002]

2. Description of the Related Art In recent years, as semiconductor manufacturing technology has advanced, there has been a remarkable increase in the degree of integration and capacity of semiconductor memories. In addition, the development of microcomputers has rapidly become more sophisticated and multi-bit with the progress of semiconductor technology, and 32-bit central processing units (hereinafter referred to as "microprocessors") have been developed by various companies and have relatively low prices. Can be used in. Many systems have been developed in which a microprocessor having such a multi-bit data bus and a plurality of semiconductor memories (hereinafter referred to as "memory") are combined. However, the memory used in such a system is generally Since the bus width is 1, 4 or 8 bits, when connecting to a 32-bit microprocessor, a plurality of memories are used or a special memory configuration is used to match the data bus width.

FIG. 5 is a block diagram showing the configuration of a conventional bus width control device. In the figure, 1 is a microprocessor,
Reference numeral 2 is a storage device which is accessed by the microprocessor 1 and is composed of a semiconductor memory. 3 is a decoder which decodes the address space of the microprocessor 1. 6 is an address bus of the microprocessor 1; 7 is a data bus of the microprocessor 1; Is an address strobe signal indicating that the address of the microprocessor 1 has been determined, and is used as a basic signal for one cycle of the microprocessor 1. Reference numeral 9 is a read / write signal that indicates a read cycle or a write cycle, 10 is an acknowledge signal that notifies the microprocessor 1 of the completion of access, 11 is a write signal that is input to the storage device 2, and 12
Is an output enable signal for reading data from the storage device 2, 4 is a WE control circuit for generating the write signal 11 to the storage device 2, and 5 is an OE control circuit for generating the output enable signal. is there.

The mutual relationship and operation of the above components will be described below. In the system shown in FIG. 5, the data bus 7 of the microprocessor 1 is 32 bits and the data bus of the storage device 2 is 8 bits. A general semiconductor memory storage device has a 1-, 4-, or 8-bit data bus, and the most commonly used storage device has a data bus width of 8 bits. Of the 32 bits of the data bus 7 of the microprocessor 1, 8 bits (D24-3
1) is connected to the data bus of the storage device 2 and the remaining 24
Bits (D0-23) are not connected.

FIG. 6 is a timing chart showing an access operation in a conventional data bus control device. In the figure, when the microprocessor 1 starts a read cycle or a write cycle with respect to the memory device 2, an address signal is first output to the address bus 6 and an address strobe signal 8 for notifying that the address has been determined is given.
Is activated. Further, the read / write signal 9 designating a read cycle or a write cycle is also activated. Here, the chip select signal 13 is generated by the decoder 3 to which the upper bits of the address bus 6 are connected, for the storage device 2 assigned to a predetermined address. In the read cycle, the OE control circuit 5 generates the output enable signal 12, and in the write cycle, the WE control circuit 4 generates the write signal 11. By the above control signals, reading and writing can be performed on the storage device 2.

The positional relationship of the data read or written as described above on the memory map will be described. FIG. 7 is a schematic diagram showing the relationship between the address space of the microprocessor 1 and the memory address of the storage device 2. Here, the start address of the memory address of the storage device 2 will be described as address 0. As shown in FIG. 5, the memory address of the memory device 2 is connected to the address of the microprocessor 1 from A2. This is because the 8-bit unit of data corresponds to one address, so that the 32-bit microprocessor 1 accesses four addresses in one access. Further, since the lower bits (D0 to D23) of the data bus 7 are not connected to the storage device 2, when the microprocessor 1 accesses the storage device 2, the address on the microprocessor side is 0,
4, 8, C, ...

By such access, the addresses on the storage device 2 side can be continuously accessed as 0, 1, 2, 3, .... Further, although not shown in the figure, even when the data is stored in a register inside the microprocessor 1, since the register is usually 32 bits, only 8 bits out of 32 bits are valid.

[0008]

In such a conventional data bus width control device, when reading 32-bit data from the memory device, the microprocessor requires four consecutive accesses to the memory device. Further, a large number of operations are required in order to arrange 8-bit data into 32-bit data inside the microprocessor. Therefore, there is a problem that it takes a lot of time to process the data and the processing capability is lowered.

The present invention solves the above-described problems, and a bus width control that enables data of the bus width of a microprocessor to be accessed in one access to a storage device having a bus width smaller than that of the microprocessor. The purpose is to provide a device.

[0010]

In order to achieve the above-mentioned object, the present invention is interposed between a central processing unit and a storage device, and the bus width of a data bus of the central processing unit is the data of the storage device. In a data bus width control device for controlling the bus width and inputting / outputting the data of the central processing unit, which is an integral multiple of the bus width of the bus, to / from the storage device, the data output from the microprocessor is temporarily stored in a write cycle. A first storage means, a second storage means for temporarily storing data output from the storage device during a read cycle, and a temporary storage in the first storage means based on size data designating a bus width of the storage device. First sequencer means for dividing the stored data into the bus width of the storage device and sequentially controlling output to the data bus of the storage device; and the storage device based on the size data. Second sequencer means for controlling input of data output from the storage device to the second storage means until the bus width of the central processing unit is reached, and an address of the storage device corresponding to address data of the central processing unit. An address control unit for controlling, and in a write cycle, the data output from the central processing unit is temporarily stored in the first storage unit, and then the data stored in the first storage unit is stored in the first sequencer. The data is divided into the data buses of the storage device by the means and output, and the addresses to be stored are sequentially output from the address control means,
In the read cycle, the data of the storage device is sequentially read by the second sequencer means from the address designated by the address control means until the bus width of the central processing unit is reached and temporarily stored in the second storage means, The data bus width control device outputs the data to the data bus of the central processing unit.

[0011]

According to the present invention, in the above structure, in the write cycle, the data output from the central processing unit is temporarily stored in the first storage unit, and then the data stored in the first storage unit is stored by the first sequencer unit. The data is divided into the data bus of the device and output, and the addresses to be stored are sequentially output from the address control means, and in the read cycle, the data of the storage device is read from the address designated by the address control means by the second sequencer means. Then, the data is sequentially read out until the bus width becomes equal to, and temporarily stored in the second storage means, and then the data is output to the data bus of the central processing unit. Therefore, a single access of the microprocessor causes the storage device to perform a plurality of read or write operations.

[0012]

【Example】

(Embodiment 1) A data bus width control device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data bus width control device according to an embodiment of the present invention. In the figure, 1 is a microprocessor, 2 is a memory device, 3 is a decoder that decodes an address of an address bus 6 of the microprocessor 1 and outputs a chip select signal, 7 is a data bus of the microprocessor 1, and 8 is an address bus. An address strobe signal indicating the confirmation, 9 is a read / write signal indicating whether the microprocessor 1 is in the read operation or the write operation, 10 is an acknowledge signal notifying that the access is completed, and 11 is to the storage device 2. A write signal, 12 is an output enable signal for reading data from the storage device 2, and 13 is a storage device 2
A WR sequencer that generates each reference signal, 16 an RD sequencer that generates a predetermined timing during a read cycle, 18 an address counter that generates an address of the storage device 2, and 17 an address counter 18 An address counter control circuit for supplying a load signal 34 and a count signal 35 to
Reference numerals 19, 20, 21, and 22 denote first, second, third, and fourth write registers for latching data on the data bus 7 of the microprocessor 1 in a write cycle, and reference numerals 23, 24, 25, and 26 denote a read cycle, respectively. First, second, third and fourth read registers that sometimes latch data on the memory data bus 28, 27 is a memory address bus supplied to the memory device 2, and 29 is a CPU clock which is a reference signal of the microprocessor 1. Three
0 is the address counter clock which is the reference signal of the address counter control circuit 17, 31 and 32 are the first size signal and the second size signal which respectively indicate the access bit size of the microprocessor 1, 33 is the read register 23-26. First to fourth clock signals
, 36 is a first to fourth register enable signal which is an output enable signal for the write registers 19 to 22, and 37 is a write clock for latching the data bus of the microprocessor 1 in the write registers 19 to 22.

FIG. 4 is a schematic diagram showing the relationship between the data of the microprocessor and the data of the storage device when the data bus width control device of the present invention is used.

The mutual relationship and operation of the above components will be described below. First, the operation when the microprocessor 1 reads 32-bit data from the storage device 2 will be described. FIG. 2 is a timing chart showing the operation of reading 32-bit data from the storage device using the data bus width control device according to the embodiment of the present invention. At this time, the bus width of the memory data bus 28 of the storage device 2 is 8 bits, and the bus width of the data bus 7 of the microprocessor 1 is 32 bits.

When the microprocessor 1 executes a 32-bit data read cycle, first, an address signal is output to the address bus 6, the address strobe signal 8 indicating that the address has been determined is activated, and read / write is performed. The write signal 9 and the first and second size signals indicating the access size are activated. This size signal determines the access size by the combination of two signals. The combination is (first size signal, second size signal) = 32 bits when (0,0), (1,0)
Indicates 16 bits, and (0, 1) indicates 8 bits. The address output from the microprocessor 1 is loaded into the address counter 18. The loaded address is transferred to the storage device 2 via the memory address bus 27.
Is supplied to. The chip select signal 13 is also activated. Here, the RD sequencer 16 uses the read / write signal 9, the first and second size signals and the address A0,
The output enable signal 12 is activated with reference to A1. By this operation, the first byte of data is output from the storage device 2, and the first read register 23 stores the RD
The read clock 33 is supplied from the sequencer and the data of the first byte is latched.

Next, the count signal 35 is supplied from the address counter control circuit 17 to the address counter 18, and the address of the storage device 2 is incremented by 1. Therefore, the second byte of data is output from the storage device 2, and the read clock 3 of the RD sequencer is output.
3 is latched in the second read register 24. By repeating this operation 4 times, 4 bytes (32 bits)
Data is latched in the read register. When the 32-bit data is complete, the acknowledge signal 10 indicating the completion of the access is supplied to the microprocessor 1, and the microprocessor 1 reads the data from the read register and completes the access. FIG. 4 is a block diagram showing the data arrangement at this time.

Although the above description has been made by taking the case of 32-bit access as an example, the same operation is performed in the case of 16-bit or 8-bit. However, when 16 bits are used, 2 bytes and when 8 bits are used, 1 byte of data is latched in the read register and the acknowledge signal 10
Is generated, the microprocessor 1 is notified of the completion of the cycle, and the read cycle is completed. Therefore, 1
The time required for the cycle becomes shorter in the order of 32 bits, 16 bits, and 8 bits. Therefore, the cycle time depends on the access size of the microprocessor 1, and no unnecessary time is required.

Next, the operation when the microprocessor 1 writes 32-bit data to the storage device 2 will be described. FIG. 3 is a timing chart showing the operation of writing 32-bit data to the storage device 2 using the data bus width control device of the present invention.

Similar to the read cycle, first, the address bus 6 of the microprocessor 1 is output, and the address strobe signal 8 notifying that it has been determined is activated. At the same time, the read / write signal 9 and the first and second size signals indicating the access size are activated. The microprocessor 1 also outputs write data on the data bus 7, and the WR sequencer outputs a write clock 37 to latch this write data in the write registers 19, 20, 21 and 22. A register enable signal 36 of the first write register is supplied from the WR sequencer to output the first byte of the latched data to the memory data bus 28. The 8-bit data output on the memory data bus 28 is written in the storage device 2 by the write signal 11 output from the WR sequencer. Similar to the read operation, the address counter counts up by 1 and supplies the next 8-bit address to the storage device 2. Then, the register enable signal of the second write register is generated from the WR sequencer, and the data of the second byte is stored in the memory data bus 2.
8 are supplied. Then, similarly to the above, the write signal 11 is activated and the data of the second byte is written in the storage device 2. By repeating such operation 4 times, 3
2-bit data can be written to the storage device 2. At the same time when the writing of four times is completed, the WR sequencer supplies an acknowledge signal 10 to the microprocessor 1 to notify the completion of the access. In this way, one write cycle is completed. Similar to the description of the read cycle, writing of 32-bit data has been described here, but the same operation is performed for 16-bit or 8-bit data. However, when data of 2 bytes in the case of 16 bits and 1 byte in the case of 8 bits are written in the memory device 2, an acknowledge signal 10 is generated immediately to notify the microprocessor 1 of the completion of the cycle, and the write cycle is completed. finish. Therefore, it is possible to realize the access time according to the designated number of bits even in the write cycle.

[0021]

As is apparent from the above embodiments, the present invention is interposed between the central processing unit and the storage device, and the bus width of the data bus of the central processing unit is the bus of the data bus of the storage device. A data bus width control device for inputting / outputting data of the central processing unit, which is an integral multiple of the width, to / from the storage device by controlling the bus width. The data bus width control device temporarily stores data output from the microprocessor during a write cycle. Storage means, second storage means for temporarily storing data output from the storage device during a read cycle, and data temporarily stored in the first storage means based on size data designating a bus width of the storage device. Is divided into the bus width of the storage device and sequentially controlled to output to the data bus of the storage device, and the output of the storage device is performed based on the size data. Second sequencer means for controlling input of data to the second storage means until the bus width of the central processing unit is reached, and address control for controlling the address of the storage apparatus corresponding to the address data of the central processing unit Means for temporarily storing the data output from the central processing unit in the first storage device in a write cycle, and then storing the data stored in the first storage device by the first sequencer device. The data is divided into the data bus of the device and output, and the address to be stored is sequentially output from the address control means, and in the read cycle, the data of the storage device is changed from the address specified by the address control means by the second sequencer means. The data was sequentially read until the bus width of the central processing unit was reached and temporarily stored in the second storage means. Chi, by a data bus width control device to output the data to the data bus of the central processing unit can input and output data of the data bus width of the microprocessor in a single access of the microprocessor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data bus width control device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a read cycle in the data bus width control device according to the embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of a write cycle in the data bus width control device according to the embodiment of the present invention.

FIG. 4 is a schematic diagram showing a relationship between a data bus of a microprocessor and a memory address in a data bus width control device according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional data bus width control device.

FIG. 6 is a timing chart showing an access operation in a conventional data bus width control device.

FIG. 7 is a conceptual diagram showing a relationship between a conventional microprocessor address space and a memory address.

[Explanation of symbols]

1 Microprocessor (Central Processing Unit) 2 Storage Device 3 Decoder (Address Control Means) 4 WE Control Circuit 5 OE Control Circuit 6 Address Bus of Central Processing Unit 7 Data Bus of Central Processing Unit 8 Address Strobe Signal 15 WR Sequencer (First 16 sequencer means) 16 RD sequencer (second sequencer means) 17 address counter control circuit (address control means) 18 address counter (address control means) 19-22 first to fourth write registers (first storage means) 23 to 26 1st to 4th read registers (second storage means) 27 address bus of storage device 28 data bus of storage device SIZE1 size data SIZE2 size data

Claims (1)

[Claims] 1. The data of the central processing unit, which is interposed between the central processing unit and the storage unit, wherein the bus width of the data bus of the central processing unit is an integral multiple of the bus width of the data bus of the storage unit. In a data bus width control device for controlling the bus width to and from the storage device, the first storage means for temporarily storing data output from the microprocessor during a write cycle, and the output from the storage device during a read cycle. Second storage means for temporarily storing data, and based on size data designating a bus width of the storage device, the data temporarily stored in the first storage means is divided into bus widths of the storage device and sequentially described above. First sequencer means for controlling output to the data bus of the storage device, and the data output from the storage device based on the size data becomes the bus width of the central processing unit. A second sequencer means for controlling the input to the second storage means and an address control means for controlling the address of the storage device in correspondence with the address data of the central processing unit. The data output from the processing device is temporarily stored in the first storage device, and then the data stored in the first storage device is divided into the data bus of the storage device by the first sequencer device and output. , Sequentially outputting addresses to be stored from the address control means,
In the read cycle, the data of the storage device is sequentially read by the second sequencer means from the address designated by the address control means until the bus width of the central processing unit is reached and temporarily stored in the second storage means, A data bus width control device adapted to output the data to the data bus of the central processing unit.