JP2001297594A - Method for providing capability of reprogramming memory redundancy in field - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and a method in which a memory can be tested and restored in a field by a user. SOLUTION: A memory device (142) having a redundant memory block (143) is evaluated by a processing mechanism (110) deciding whether the memory device (142) includes a defective memory or not. A restoring mechanism (130) is used for restoring the memory device (142) when the memory has a defective memory and the redundant memory block (143) can be used for restoration. A method for providing capability reprogramming memory redundancy in a field is summarized in the following steps. First. it is decided whether or not the memory device has a defect (103) and the redundant memory block (143) can be used for restoring the memory device, Next, when the memory (142) has a defect and the redundant memory block (143) can be used for restoration, the memory is restored in the field (106).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to memories, and more particularly, to systems and methods that provide the ability to reprogram memory redundancy in the field.

[0002]

2. Description of the Related Art There are currently several prior art solutions for replacing faulty memory. One conventional solution is to replace certain parts of the memory hardware (ie, memory chips or memory boards). This first conventional solution causes downtime for any device that utilizes memory. This downtime is not only expensive, but can also reduce customer satisfaction. This decrease in customer satisfaction is caused by a delay in the time from when the memory problem is detected to when the service engineer goes to the site and replaces the faulty memory. This service call can increase both user cost and vendor cost.

[0003] Another conventional solution uses error correction hardware to detect and correct data corrupted by a memory failure during operation at the customer. A disadvantage of this alternative solution is that the device that detects and corrects data corrupted by a memory failure degrades the performance of the memory, and the device cannot handle all failures.

[0004]

Accordingly, there is a need in the art for a method that addresses the above shortcomings and deficiencies.

[0005]

SUMMARY OF THE INVENTION The present invention is generally directed to a system and method for testing and repairing memory in the field. Briefly, in an architecture, a memory test and repair system can be implemented as follows. Memory devices having redundant memory blocks are evaluated by a processing mechanism that determines whether the memory device has defective memory. If the memory has defective memory and a redundant memory block is available for repair, a memory repair mechanism is used to repair the memory device.

The present invention can also be viewed as providing a method for testing and repairing a memory in the field. In this regard, methods that provide the ability to reprogram memory redundancy in the field can be broadly summarized in the following steps. First, it is determined whether the memory device has failed and whether a redundant memory block is available for repairing the memory device. Next, if the memory is faulty and a redundant memory block is available for repair, the memory is repaired in the field.

[0007] Other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following drawings and detailed description. In this specification,
All such additional features and advantages are intended to be included within the scope of the present invention.

[0008]

Next, the present invention will be described in detail with reference to the drawings. While the present invention will be described in conjunction with these drawings, there is no intention to limit the invention to the embodiments disclosed herein, and all alternatives, modifications, and variations included within the scope of the invention as defined in the appended claims. And the like.

FIG. 1 shows a computer system 12 employing a memory test and repair system 100 of the present invention.
Is shown. Computer system 12 uses processor 21, storage 22, and memory 31, including operating system 32, to identify, access, and process resources desired by the user. Processor 2
1 accepts data from memory 31 via local interface 23, for example, one or more buses. For example, mouse 24 and / or keyboard 2
5, one or more input devices may be used to send instructions from the user. The input data and the output data can be displayed on the display terminal 26.

FIG. 1 also shows a device system 50 located in the memory 31 of the user computer system 12.
, A memory test and repair system 100 is also shown. The device system 50 will be further described below with reference to FIG. Memory test and repair system 10
0 is described further below in connection with FIGS.

FIG. 2 is a block diagram illustrating the memory test and repair system 100 of the present invention located in the memory circuit 41. The memory circuit 41 shown in FIG. 2 includes a memory area 42 and a memory control logic 43. The memory control logic 43 further includes a device system 50 and the memory test and repair system 100 of the present invention. The device system 50 is defined in more detail herein with respect to FIG. 3, and the memory test and repair system 100 is further defined herein with reference to FIGS. I do. The memory circuit 41 in FIG. 2 is, for example, a memory of the following type, that is, a random access memory (RA).
M), read-only memory (ROM), erasable programmable ROM (EPROM or flash memory), and portable compact disc ROM (C
D-ROM), but is not limited thereto.

FIG. 3 shows an example of the architecture and functions of the device system 50. Device system 5
A zero operation involves the use of the memory test and repair system 100 of the present invention. Use of the memory test and repair system 100 is included in the initialization of the device system 50.

In step 51, the device system 50 is connected to the computer system 12 or the memory circuit 4.
Initialized at 1. In step 52, the device system 50 executes the memory test and repair system 100 of the present invention. The memory test and repair system 100 is further defined herein in connection with FIGS. After the memory test and repair system 100 has been executed in step 52 of FIG.
To determine if a significant memory failure (ie, irreparable) has been detected. If a serious memory failure is detected in step 53, the device system 5
0 displays a critical memory fault message to the user in step 57, followed by terminating operation of device system 50 in step 59.

If no failure is detected in step 53, the device system 50 proceeds to step 54 and performs a normal operation. In step 54, the device system 50 performs normal operation, and periodically determines in step 55 whether a reset or reboot command has been input. If a reset or reboot command has been received in step 55, device system 50 returns to step 51, reinitializes the device, and repeats steps 51-59.

If the command received in step 55 is not a reset or reboot command,
In step 56, the device system 50 determines whether the command is a command for ending the normal operation of the device. If it is determined in step 56 that the termination command has not been received, the device system 50 returns and repeats steps 54 to 56. If it is determined in step 56 that the device has received the termination command, the device proceeds to step 59.
To end the device operation.

FIG. 4 illustrates an example of the architecture and functions of a memory test and repair system 100 that operates within the memory 31 of the computer system 12. In step 101, the memory repair system 100 is initialized.

In step 102, memory test and repair system 100 performs a memory test.
This step of testing the memory can be performed in a number of ways, depending on the nature of the redundancy scheme implemented on the memory. One method uses built-in self-test hardware (BIST) for memory testing. A description of the special purpose built-in test hardware can be found in A Flexible and Programmable BIST Engine for On-c, filed October 30, 1998.
co-pending US patent application Ser. No. 09 / 183,536, assigned to the common assignee, entitled “hip Memory Array Testing and Characterization” (attorney docket number 10981644-
It is described in detail in 1) and is incorporated herein by reference.

After completion of the memory test performed on the dedicated memory, the memory test and repair system 100
Determines in step 103 whether a failure has been detected during the memory test. If no fault is detected, the memory test and repair system 100 marks the state of the memory as good memory at step 107. In step 109, the memory test and repair system 100 ends.

However, if the memory test and repair system 100 detects a failure in step 103, the memory test and repair system 100 identifies a defective memory section in step 104. At step 106, the memory test and repair system 100 determines whether a redundant memory block is available. Redundant memory blocks can be used to repair sections of memory. These repairable sections of memory may include columns, rows, or other blocks of memory, depending on how the memory implementation divides the memory into sections.

The example described herein in connection with FIGS. 7 and 8 is a column-based HP PA8500 cache memory. In the PA8500 embodiment, a defective row of cache memory can be replaced during testing of the memory at the manufacturing site prior to packaging (ie, encapsulating the integrated circuit in a plastic or ceramic material). On-site replacement requires an integrated circuit tester to perform function replacement before packaging. In the PA8500 example, if a defective column of the cache memory is found during manufacturing test, the entire column of the cache memory will be unused and a spare (ie,
A redundant column of a cache memory) is used. Defective memory locations found during manufacturing test are stored in non-volatile memory fuses. Further explanation of this process can be found in the November 1997 IEEE INTERNA
Jeff Brauch and Jay Fle, co-inventors, in TIONAL TEST CONFERENCE, Paper 12.2, pp. 286-293.
`` Design of cache test hardware on t '' by ischman
he HP PA8500 ", which is incorporated herein by reference.

If it is determined in step 105 that the redundant memory block is not available, the memory test and repair system 100 proceeds to step 108 and marks the memory state as having a severe failure. The memory test and repair system 100 proceeds to step 109
Ends at

If it is determined in step 105 that a redundant memory block is available, the memory repair system 100 attempts to repair the memory in step 106. The architecture of the device for repairing memory is described herein in FIGS. 6, 7, and 8.
More details will be defined in relation to. Step 10 in FIG.
At 6, after attempting to repair the memory, the memory test and repair system 100 returns and repeats steps 102-107. This retest operation is performed on the newly configured memory to ensure that there is no defect in the new (redundant) section of memory or in the hardware that controls the switching of the new (redundant) section of memory. Done. Some applications that use more complex redundancy schemes require multiple paths to complete the repair operation.

FIG. 5 shows an example of the architecture and functions of the memory test process 110 of the present invention. In step 111, the memory test process 110 is initialized and the memory is marked as good. Step 11
At 2, a first memory address is received. At step 113, the received memory address is decoded. This decoding determines the memory array and location indicated by the received memory address. Having determined the correct memory array and location, at step 114, data is written to the memory array at the location indicated by the received memory address. After writing the data to the appropriate memory array, a read function is performed at step 115 to instruct the appropriate memory array to output the data at the received memory address.

At step 116, a comparison is made between the data from the appropriate memory address in the appropriate memory array and the input data value. In step 117, it is determined whether a failure is detected. A fault is detected if the data result written from the appropriate memory array is not equal to the data entered into the appropriate memory array at the address specified by the memory address. If a fault is detected, the memory test process 110 marks the memory as faulty at step 118, records the location of the fault, and continues the test operation at step 121.

If no fault is detected, the memory test process 110 determines in step 121 whether there are more memory addresses to check.
If there are more memory addresses to check, the memory test process 110 returns and repeats steps 112-121. If it is determined that there are no more memory addresses to check, then at step 129, the memory test process 110 ends. If no fault was recorded in step 118, the memory is considered good.

FIG. 6 shows a memory repair process 1 of the present invention.
1 illustrates an example of ten architectures and functions. In step 131, the memory repair process 130 is initialized.

In step 132, memory repair process 130 receives the failed memory location. Once the failed memory location is known, the memory repair process 130 decodes the memory location at step 133. At step 134, the memory repair process 130 applies the redundant memory to replace the failed memory at the indicated memory location.
As mentioned above, there are many different ways to apply redundant memory, depending on the memory architecture. At step 135, the memory repair process 130 detects the faulty memory location by a fault detect register (fault detect).
ed register), and in step 139,
End the memory repair process. The detected fault register is any non-fuse type logic circuit that stores at least one bit indicating the fault memory location. The detected fault register is further defined herein in connection with FIGS. 7 and 8.

FIG. 7 is a schematic block diagram showing an example of the device of the memory test and repair system 100 of the present invention. Illustrated is an exemplary memory circuit 41
The memory 42 in FIG. 2 and the memory test and repair system 100 logic. In the memory 42,
Decoder 141 and memory arrays 142A and 142
B. Also shown are spare memory arrays 143A and 143B.

The decoder 141 has an address register 15
1 receives the address. Decoder 141 decodes the received address to determine the specified memory array and location. Upon determining the correct memory array and location, the decoder 141 commands the appropriate memory array 142A or 142B to write data to the location indicated by the memory address. Data values are obtained from the data 0 register 152 or the data 1 register 153. After writing the data to the appropriate memory array 142A or 142B, the decoder 141
A read function to instruct 42B to output data to the comparator 154 is performed. The comparator 154
Compare the data from the appropriate memory location in the appropriate memory array 142A or 142B with the input data value from either the Data 0 register 152 or the Data 1 register 153.

Comparator 154 determines whether the data result written from the appropriate memory array 142A or 142B is equal to the data input to the appropriate memory array at the address specified by address register 151. If the comparator 151 determines that a fault has been detected, the comparator 154 sends a signal to the detected fault register 155. The detected fault register 155 generates a detected fault warning signal 156. Read and write operations can be performed systematically at different addresses to perform a march test. A description of the March Test can be found in Nov. 1997, co-inventors Jeff Brauch and Jay Fleischman, supra,
ign of cache test hardware on the HP PA8500 ", which is fully described and incorporated herein by reference.

FIG. 8 is a schematic block diagram showing an example of the operation of the redundant memory switching circuit using the memory test and repair system 100 of the present invention. In the operation of the memory circuit 41 (FIG. 2), the memory address register 151 in FIG. Memory address decoder 141 determines the appropriate location in memory array 142 that corresponds to the address from memory address register 151. During a read operation, the memory array 142
Inputs the result to the data selector 161. Spare memory array 143 also inputs the result of the spare column to data selector 161. This causes the detected fault register 155 to indicate which column of the memory array 142 (if any) is to be replaced with the spare memory array 143.
It can be shown in the data selector 161. Then, the data result is output on the data bus 162.

In the write operation of the memory circuit 41 (FIG. 2), the memory address register 151 inputs an address to the memory address decoder 141 of FIG. The memory address decoder 141 includes a memory array 142 corresponding to an address from the memory address register 151.
Determine the appropriate location within Memory array 14
2 writes the data from the data selector 161 into the corresponding memory array 142. When the address input from the memory address register 151 indicates an area in the memory array 142 using the spare memory array 143, the data selector 161
Move data away from the failed memory location in memory array 142 to spare memory array 143. The detected fault register 156 indicates when the spare memory array 143 is used during a write operation.

As mentioned above, the flowcharts of FIGS. 1-8 illustrate the architecture, functionality, and operation of a possible implementation of the software for testing and repairing system memory. In this regard, each block represents a module, segment, or portion of code that contains one or more executable instructions for performing the specified logical function. Also, note that in some alternative implementations, the functions noted in the block may occur out of the order noted in the flowcharts. For example, as described herein above, depending on the functions involved, blocks shown in succession may actually be executed substantially simultaneously, or blocks may be executed in reverse order. There is also.

[0034] The memory test and repair system 100, including an ordered list of executable instructions for performing the logic functions, may be used to retrieve instructions from a computer-based system, a processor-containing system, or an instruction execution system, apparatus, or device. It can be implemented in any computer-readable medium for use by or in conjunction with an instruction execution system, apparatus, or device, such as another system capable of fetching and executing the instructions. . In the context of this specification, "computer-readable medium" includes, stores, communicates, propagates, or conveys a program used by or for use with an instruction execution system, apparatus, or device. Can be any means that can be used. The computer-readable medium can be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (not an exhaustive list) of computer readable media include: Electrical connections (electronics) with one or more wires, portable computer diskettes, random access memory (RAM),
Read-only memory (ROM), erasable programmable ROM (EPROM or flash memory),
And portable compact disk ROM (CD-R
OM). Note that, for example, the program may be optically scanned on paper or other media on which the program is printed, and the program may be captured electronically and then compiled and interpreted or, if necessary, processed in an appropriate manner. Note that the computer readable medium may be paper or any other suitable medium on which the program is printed, as it may be stored in computer memory from Microsoft.

The foregoing description has been presented for purposes of illustration and description. This is not exhaustive and is not intended to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments discussed best illustrate the principles of the present invention and its practical application, whereby a person of ordinary skill in the art would be able to read the specification in various embodiments and with various modifications suitable for the particular intended use. It has been selected and described in order to make the description available.

All such modifications and variations are within the scope of the present invention.

The present invention includes the following embodiments as examples.

(1) A method for providing the ability to reprogram memory redundancy in a field, comprising: determining whether the memory (142) is faulty (103); and a redundant memory block (143). Determining Whether Is Available for Repair (105)
And repairing the memory (142) in the field if the memory (142) has failed and the redundant memory block (143) is available for repair (106). .

(2) The step of determining whether the memory (142) has a fault includes the step of generating a memory address (113), the step of writing data to the memory address (114), and the step of Reading the data at the address (115)
And the data written to the memory address,
Comparing the data read from the memory address with the data (116).

(3) Identifying a defective memory portion in the memory which is the cause of the failure (117)
The method according to the above (1), further comprising:

(4) The method according to (3), wherein the step (117) of identifying the defective memory portion further comprises a step (133) of decoding a memory address for the defective memory portion.

(5) The step of repairing the memory in the field (106) includes switching to the redundant memory block (143) available for repair and replacing the defective memory portion (134); Storing the memory address of the defective memory portion in a defective memory index location (135);
The method according to the above (4), further comprising:

(6) A system that provides the ability to reprogram memory redundancy in a field, wherein the memory (142) has a redundant memory block (143).
A processing mechanism (110) for determining whether the memory (142) is a defective memory; and the memory (142).
Are defective and the redundant memory block (143)
A memory repair mechanism (130) for repairing the memory device in the field if it is available for repair
And a system comprising:

(7) The processing mechanism includes a data writing mechanism (159) for writing data to the memory (142) at a memory address, and a data reading mechanism (159) for reading the data from the memory (142) at the memory address. The system according to (6), further comprising: and a comparing unit (154) for comparing data written to the memory address with data read from the memory address.

(8) The memory repair mechanism (130)
The system according to (7), further comprising a defective memory specifying mechanism (151) for specifying a memory address of the defective memory.

(9) The memory repair mechanism (130)
The system according to (8), further comprising a memory switching mechanism (161) for replacing the defective memory with the redundant memory block.

(10) The memory repair mechanism (130)
The system according to (8), further comprising a memory storage mechanism (155) for storing the memory address of the defective memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a memory test and repair system of the present invention located in a computer readable medium, such as in a user computer system.

FIG. 2 is a block diagram illustrating a memory test and repair system of the present invention located within a stand-alone device having a memory circuit.

FIG. 3 is an exemplary flowchart showing a device process for performing the memory test and repair system of the present invention in the apparatus having the memory circuit shown in FIGS. 1 and 2;

FIG. 4 is an exemplary flow chart illustrating an example of the field memory test and repair system of the present invention shown in FIG.

FIG. 5 is an exemplary flowchart showing an example of the memory test process of the present invention shown in FIG.

FIG. 6 is an exemplary flowchart illustrating an example of the memory repair process of the present invention shown in FIG.

FIG. 7 is a block diagram showing an example of a memory fault detection circuit used by the memory test and repair system of the present invention shown in FIGS. 1, 2 and 4;

FIG. 8 is a block diagram illustrating an example of a memory replacement architecture utilized by the memory test and repair system of the present invention.

[Description of Signs] 142 Memory 143 Redundant Memory Block 151 Defective Memory Identifying Mechanism 154 Comparison Mechanism 155 Memory Saving Mechanism 159 Data Reading Mechanism 161 Memory Exchange Mechanism

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Jay Michael Hill United States 80526 Ford Collins, Colorado, Idledale Drive 4420 (72) Inventor Jay Fleischman, United States 80526 Fort Collins, Colorado, Bronson・ Coat 2100 (72) Inventor James I. Brookhauser, West Bourne Circle 6537, Fort Collins, Colorado, 80525 USA

Claims (1)

[Claims] 1. A method for providing the ability to reprogram memory redundancy in a field, the method comprising: determining whether the memory has a fault; and determining whether a redundant memory block is available for repair. And repairing the memory in the field if the memory has failed and the redundant memory block is available for repair.