JP2001307497A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that as wiring or the like are physically processed after manufacturing in memory-repair technology of a fuse system in which a defective part of a memory cell section is replaced by a redundant part by physically separating a fuse, the cost is increased, and further, the manufacturing cost owing to a test itself of an incorporated large scale memory is increased. SOLUTION: This device is provided with a memory cell means having a normal port in which normal read/write operation is performed and a test port for test only, a data latch means for temporarily holding write-data written in the memory cell means from a normal port, a comparing means for reading out data written by the normal port in the memory cell means from the test port and comparing read-data with write-data held in the data latch means, a redundant means for holding write-data instead of the memory cell means, and an address holding means for holding information about an address indicating a place of the memory cell means in which write-data is written when noncoincidence occurs in coincidence-comparison by the comparing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a large-scale memory circuit mounted in a circuit device.

[0002]

2. Description of the Related Art In accordance with recent advances in semiconductor processing technology, large-scale memory cell units have been mounted on semiconductor integrated circuit devices. The memory cell portion is a portion where the integration density is higher than that of the logic and a manufacturing defect is likely to occur. Conventionally, as a remedy method for a defect of the memory cell in the memory cell portion at the time of manufacturing, a redundant area (redundant portion) is secured in advance, and a word, a bit, or the like in which the memory cell becomes defective in a test performed after manufacturing. To
There is a repair technique for replacing a redundant part prepared in advance. As this repair technique, for example, there is a fuse type memory repair technique in which a fuse is physically cut by a laser to separate a failed portion of a memory cell portion and replace it with a redundant portion. Japanese Patent Application Laid-Open No. 4-372 discloses a document which discloses another example of remedy for a memory cell defect in a conventional semiconductor integrated circuit device.
798 publication.

[0003]

Since the conventional semiconductor integrated circuit device is configured as described above, a fuse type memory repair for replacing a faulty portion of a memory cell portion and a redundant portion by physically disconnecting a fuse. In the technology, wiring and the like are physically processed after manufacturing, so that the cost is increased, and further, there is a problem that the manufacturing cost of the test of the built-in large-scale memory itself is also increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor integrated circuit device capable of relieving a defect in a memory cell portion without increasing cost. And

[0005]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention includes a memory cell means having a normal port for performing a normal read / write operation, a test port dedicated to a test, and a memory cell from the normal port. Data latch means for temporarily holding write data written to the means, and data written to the memory cell means from its normal port are read from the test port, and the read data matches the write data held in the data latch means. A comparing means for performing comparison; a redundant means for holding write data in place of the memory cell means when the comparison by the comparing means results in a mismatch; Address holding information on an address indicating the location of the memory cell means in which is written It is intended and means.

In the semiconductor integrated circuit device according to the present invention, the data latch means has a plurality of data latches each of which temporarily holds write data to be written from the normal port to the memory cell means. During the first read operation to the address of the changed memory cell means, the data held in the corresponding data latch of the data latch means is output, and thereafter, in the write / read operation to that address, the matching by the comparison means is performed. This is to directly access the redundant means holding the write data corresponding to the address held in the address holding means without performing the comparison.

In the semiconductor integrated circuit device according to the present invention, the data latch means has one data latch for temporarily holding write data written to the memory cell means from the normal port, and writes the write data to the memory cell means. In operation, the comparing means performs a match comparison, and in the case of a mismatch, the redundancy means holds the write data, the address holding means holds an address indicating the location of the memory cell means in which the write data has been written, and If a match is found in the subsequent match comparison, the address held in the address holding means is cleared or the address becomes overwritable, and the write data held in the redundant means is cleared. Alternatively, the write data is in a state where overwriting can be performed.

In the semiconductor integrated circuit device according to the present invention, the data latch means has one data latch for temporarily holding write data written to the memory cell means from the normal port, and writes the write data to the memory cell means. In operation, the redundancy means holds the write data, the address holding means holds an address indicating the location of the memory cell means in which the write data has been written, the comparison means performs a match comparison, and in the case of a mismatch, the redundancy means Holds the write data as it is, and the address holding means holds the address as it is. If the addresses match, the address held in the address holding means is cleared or the address becomes overwritable, and the redundant means The write data held in the And it serves as a site ready.

A semiconductor integrated circuit device according to the present invention decodes an input address when performing a read / write operation, and activates a first word line for activating a word line of a redundant means.
And a second decoder for activating the word line of the memory cell means. The address holding means determines whether or not the same address as the address is held. If the same address is held, the first decoder activates the corresponding word line of the redundancy means; otherwise, the second decoder activates the corresponding word line of the memory cell means. It becomes something.

The semiconductor integrated circuit device according to the present invention asserts a full flag signal when there is no space necessary for the redundancy means to replace the memory cell means.

The semiconductor integrated circuit device according to the present invention asserts an overflow signal when there is no space necessary for the redundancy means to substitute for the memory cell means, and when the comparison means makes a mismatch, the overflow signal is asserted. Things.

A semiconductor integrated circuit device according to the present invention has a memory cell means having a normal port for performing a normal read / write operation, a test port dedicated for testing, and write data written from the normal port of the memory cell means. A data latch means for temporarily holding data, and a comparison in which data written to the memory cell means from the normal port is read out from the test port, and the read data is compared with the write data held in the data latch for each bit. An address indicating the location of the memory cell means to which the write data has been written, and an address / bit information holding means for holding information on the mismatch detection bit, when the match is not made by the comparison by the comparing means; In the subsequent read operation for the address where For bets, in which and means for inverting data read from the memory cell.

The semiconductor integrated circuit device according to the present invention has three or more odd numbers having different structures, each having an individual address decoder and writing the same write data so as to have the same contents at the time of a write operation. When the same address is input to a plurality of memory cell sections and a plurality of address decoders in which a read operation is performed, a majority operation of an odd number of data read from a location of the plurality of memory cell sections specified by the address is performed. And majority decision means for judging the presence or absence of a defect in the memory cell means and outputting the result of majority decision as read data.

A semiconductor integrated circuit device according to the present invention has a memory cell means having at least three odd-numbered memory cells into which respective bits of write data are written so as to have the same contents at the time of a write operation, and a memory cell means. If a read operation is performed on the write data written to
Performs a majority operation on odd-numbered bit data corresponding to each bit of data read from the plurality of memory cells of the memory cell unit, determines whether there is a defect in the plurality of memory cells of the memory cell unit, and reads the result of the majority decision Majority selection means for outputting as data.

According to the semiconductor integrated circuit device of the present invention, a plurality of memory cell portions to which the same write data is written so as to have the same contents at the time of a write operation, and a case where the write data is written to a plurality of memory cell portions And a parity bit holding means for obtaining and holding a parity bit of the write data, and performing a match comparison of a plurality of data read from a plurality of memory cell parts during a read operation, and holding a parity bit when the data does not match. Comparing means for checking the parity bit stored in the means and selecting and outputting the correct data.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device provided with at least one memory block, comprising self-test pattern generation means for generating a set of address and data as a test pattern. A memory cell means, a data latch means for temporarily holding write data written to the memory cell means, a comparison means for reading data written to the memory cell means and comparing read data and write data for coincidence; When a mismatch is detected, the redundancy means for holding the data instead of the memory cell means, the address holding means for holding the address information specifying the location of the memory cell means where the write data is written, Select the address from the self test pattern generation means An input selector for sending to the memory cell unit, during testing of the memory cell means, and selects the data from the self-test pattern generating means, in which and a data input selector to be transmitted to the memory cell unit.

A semiconductor integrated circuit device according to the present invention includes a plurality of memory blocks each including a memory cell unit, a comparing unit, a redundant unit, an address holding unit, an address input selector, and a data input selector. When testing the memory blocks of the self-test pattern, the self-test pattern generation means sends a set of address and data to a plurality of memory blocks as a test pattern, and each memory block needs the redundant means to replace the memory cell means. When there is no free space, a full flag signal is output, and the device further includes an OR circuit for calculating the logical sum of the full flag signals from a plurality of memory blocks.

A semiconductor integrated circuit device according to the present invention includes a plurality of memory blocks each including a memory cell unit, a comparing unit, a redundancy unit, an address holding unit, an address input selector, and a data input selector. When testing the memory blocks of the self-test pattern, the self-test pattern generation means sends a set of address and data to a plurality of memory blocks as a test pattern, and each memory block needs the redundant means to replace the memory cell means. If there is no free space and the comparison means makes a mismatch, the overflow signal is output. The device further includes an OR circuit for calculating the logical sum of the overflow signals from the plurality of memory blocks.

According to the semiconductor integrated circuit device of the present invention, there is provided a memory cell means, a data latch means for temporarily holding write data written to the memory cell means, and reading data written to the memory cell means to read data. Comparing means for comparing the write data held in the data latch means for coincidence; redundancy means for holding the write data in place of the memory cell means when the comparison results in a mismatch; An address holding buffer memory for holding information about an address indicating a location of a memory cell means to which write data has been written when a match is found by the comparing means, and both a read / write operation. When disabled, the address input from the address holding buffer memory is disabled. Read the less, when has an address input selector to be sent to the memory cell unit is disabled for both read / write, comparison means is intended to be enabled.

A semiconductor integrated circuit device according to the present invention comprises a memory cell means, a data string holding means having a smaller capacity than the memory cell means for holding a frequently used data string or a data string requiring a long processing time, It holds the address where the data string of the column holding means is held, and when a frequently used data string or a data string that requires processing time is accessed, the address where the data string is held is stored. Address information holding means for sending to the data string holding means.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a memory cell portion of a RAM in which a required number of memory cells are originally arranged, and a read / write port (normal port) used for a normal read / write operation and a read / write port used only for a test. There are two ports (test ports). Reference numeral 2 denotes a redundant unit provided to supplement the function of the defective part when a part of the memory cell in the memory cell unit 1 has a defect. The read / write unit 2 is used for a normal read / write operation. Light port (normal port),
It has two ports, a read port (test port) for use exclusively for testing. 3 is a memory cell unit 1
And the address decoder for the normal port of the redundant unit 2, 4
Reference numeral denotes an address decoder for a test port, and reference numeral 5 denotes an address latch for temporarily holding an address to the test address decoder 4.

Reference numeral 6 denotes a data latch for temporarily holding data input from the data input terminal DI. Reference numeral 7 denotes write data held in the data latch 6 and a test port of the memory cell unit 1 after one cycle. This is a comparison circuit that performs a comparison with the read data. 8 is the comparison circuit 7
Is a defective memory cell address holding unit that holds the input address applied to the address decoder 3 one cycle before when a mismatch is detected. If not, an OVF signal is generated. 9
Is a selector for selecting one of the data read from the normal port of the memory cell unit 1 and the data held in the data latch 6 and outputting it from the data output terminal DO. The redundant section 2 has a plurality of memory cells (not shown), the data latch 6 has a plurality of latches (not shown), and the defective memory cell address holding section 8 has a plurality of defective memory cell address holding sections. It has a register (not shown).

Next, the operation will be described. In operation, the address is directly input to the address decoder 3 for the normal port, and also to the address latch 5 disposed before the address decoder 4 for the test port. At the time of a write operation, the address latch 5 temporarily holds an address input in response to a write signal applied from outside the memory block. Therefore, at the test port of the memory cell unit 1, data is read in the next cycle of the write access of the normal port. As described above, the read from the test port is performed in the next cycle of the write access of the normal port. Therefore, the address decoding for the test port by the address decoder 4 may be performed only after the write operation of the normal port. 5 may be held only in the next cycle of the normal port write access.

At the time of a write operation, data input from the data input terminal DI is temporarily held in the data latch 6, and is also input to the normal port of the memory cell unit 1,
The data is written to the memory cell specified by the input address.
The data held in the data latch 6 is compared with the data read from the test port of the memory cell unit 1 after one cycle by the comparison circuit 7 to determine the match / mismatch. When the two match, the write / read to the corresponding address of the memory cell unit 1 has been performed normally, and thereafter, the access to the address is performed using the corresponding address of the memory cell unit 1. On the other hand, if they do not match, it means that a defective memory cell exists at that address portion of the memory cell unit 1, so that the address is held in the defective memory cell address holding unit 8 as a defective memory cell address. The access to the address is performed using the redundant unit 2.

When the write / read operation is performed, the defective memory cell address holding unit 8 determines whether or not a defective memory cell address equal to the address input to the address decoder 3 for the normal port is held. If the address is a defective memory cell address, the defective memory cell address holding unit 8 sends a hit signal to the address decoder 3 so that the address decoder 3 performs a write / read operation not on the address of the memory cell unit 1 but on the redundant unit 2. Is performed.
Since the data written first to the corresponding address is also held in the data latch 6, the data held in the data latch 6 is output from the data output terminal DO in the first read access.

As described above, the redundant unit 2, the data latch 6, and the defective memory cell address holding unit 8 are each provided with a plurality of data to deal with a plurality of defective memory cells that may be present in the memory cell unit 1. It has a holding element. Further, when a write operation is performed on an address using the redundant unit 2, it is known that the address of the memory cell unit 1 is a region where a defective portion exists, so that data coincidence comparison is performed. It is also possible to control it not to be. When the memory cell unit 1 has many defects and the address (that is, the address register) prepared by the defective memory cell address storage unit 8 cannot handle the defect, the defective memory cell address storage unit 8 outputs an OVF signal, and Notify the circuit device that a memory operation error has occurred.

FIG. 2 is an explanatory diagram for explaining the operation of the memory block according to the first embodiment for each cycle.
In FIG. 2, for the sake of simplicity, redundant section 2 has two memory cells, data latch 6 has two latches, and defective memory cell address holding section 8 has two address registers. Assume that Hereinafter, the operation will be described in detail with reference to FIG. First, in the first cycle, write data (write data) for the address A is input to the normal port of the memory cell unit 1. Next, in the second cycle, the write data for the address A input to the normal port in the previous cycle (first cycle) is held in one latch (1) of the data latch 6, and the memory read from the test port is read. The read data (read data) at the address A of the cell section 1 is compared with the read data (compared by the comparator 7). If the match comparison finds a mismatch,
The address A is held in one address register (1) of the defective memory cell address holding unit 8. On the other hand, this 2
In the cycle, write data for the address B is also input to the normal port.

Next, in the third cycle, the write data for the address B input to the normal port in the previous cycle (second cycle) is held in the data latch 6. In this case, since the first write data for the address A held in the defective memory cell address register (1) is held in the first latch (1), the write data for the address B is replaced with the data latch 6 instead. Is held in the other latch (2). The write data for the address B held in the second latch (2) is compared with the read data of the address B of the memory cell unit 1 read from the test port by the comparison circuit 7 for comparison. If the result of the match comparison is a match, the data written to the address B of the memory cell unit 1 has been normally read, and thus the data read from the memory cell unit 1 is used. That is, the address B is the defective memory cell address holding unit 8
, And the data related to the address B is not stored in the redundant unit 2. Also, the second latch (2) has the address B
Since there is no need to hold data on the related data, overwriting can be performed with other data in the next cycle. on the other hand,
In the third cycle, input of write data for address C is also performed to the normal port.

Next, in the fourth cycle, write data for the address C input to the normal port in the previous cycle (third cycle) is held in the data latch 6. In this case, the first latch (1) holds the first write data for the address A held in the defective memory cell address register (1), and the second latch (2) can be overwritten. Therefore, the write data for the address C is held in the second latch (2). The write data for the address C held in the latch (2) is compared with the read data of the address C of the memory cell unit 1 read from the test port by the comparison circuit 7 for comparison. If the result of the match comparison is a mismatch, the address C
Is stored in the second address register (2) of the defective memory cell address storage unit 8. On the other hand, the normal port of the memory cell unit 1 performs the read operation for the address A in the fourth cycle. Since this address A matches the address held in the defective memory cell address register (1) and is a read access to the first write data, the selector 9 sets the data held in the first latch (1). Is output from the data output terminal DO as read data for the address A.

Next, in the fifth cycle, a second write operation for address A is performed for the normal port.
Here, since the address A is held as a defective memory cell address in the first defective memory cell address register (1), this write access is not performed at the corresponding address of the memory cell section 1 but at one memory of the redundant section 2. Performed on cell (1). Since the write data for the address A has been written to the first memory cell (1) of the redundant unit 2, the previous write data for the address A held in the first latch (1) is cleared. Next, in the sixth cycle, write data for the address D is input to the normal port.

Next, in the seventh cycle, the write data for the address D input to the normal port in the previous cycle (the sixth cycle) is held in the first latch (1). This write data is compared with the read data at the address D of the memory cell unit 1 read from the test port by the comparison circuit 7. If the result of the match comparison is a match, the data written in the address D of the memory cell unit 1 has been normally read, so that the data read from the memory cell unit 1 is used. That is, the address D is not held in the defective memory cell address holding unit 8, and data related to the address D is not held in the redundant unit 2. Therefore, the first latch (1) has the address D
Since there is no need to hold data on the related data, overwriting can be performed with other data in the next cycle. on the other hand,
In the seventh cycle, a read operation for the address B is performed via the normal port. Since the address B is not held in the defective memory cell address holding unit 8 as a defective memory cell address, a normal read operation using the memory cell unit 1 is performed.

Next, in the eighth cycle, a read operation for the address C is performed for the normal port. This address C is stored in the second defective memory cell address register (2).
The selector 9 reads the data held in the second latch (2) from the read data corresponding to the address C because the read access to the write data that matches the address held in Is output from the data output terminal DO. Next, in the ninth cycle, the read operation for the address A is performed for the normal port. Since the address A is held in the first defective memory cell address register (1), the first operation of the redundant unit 2 is performed. The write data for the address A held in the memory cell (1) is output from the data output terminal DO via the selector 9. Next, in the tenth cycle, a second write operation for the address C is performed for the normal port. Since the address C matches the address held as the defective memory cell address in the second defective memory cell address register (2), the write data is written to the second memory cell (2) of the redundant unit 2. It is.

FIG. 3 is a flowchart showing the procedure of a write operation in the memory block shown in FIG.
Hereinafter, this will be described in detail with reference to FIG. When the write operation is performed, first, in step ST1, it is confirmed whether or not the address at which the write access is performed corresponds to the defective memory cell address held in the defective memory cell address holding unit 8. As a result, if not applicable, in step ST2, the write data is held in the data latch 6, and the write data is written to the normal port of the memory cell unit 1 in step ST3 and from the test port in step ST4. Lead. Next, in step ST5,
The comparison circuit 7 compares the data held in the data latch 6 with the data read from the test port, and determines the match / mismatch in step ST6. If the result of the determination is that they do not match, the flow branches to step ST7,
After the write target address is held in the defective memory cell address holding unit 8 as the defective memory cell address, and if the addresses match, the write operation is terminated.

On the other hand, if it is confirmed in step ST1 that the address to be subjected to the write access corresponds to the defective memory cell address held in the defective memory cell address holding section 8, the process proceeds to step ST8. . In step ST8, the write data is written to the redundant section 2 without performing the comparison by the comparison circuit 7, and the write operation is completed.

According to the first embodiment, when the address at which the write access is performed corresponds to the defective memory cell address held in the defective memory cell address holding unit 8, the data is sent to the redundant unit 2 Since the write / read operation is performed, the power consumption can be reduced by stopping the write / read operation to the memory cell unit 1, and the data match comparison operation by the comparison circuit 7 is not performed. As a result, power consumption can be further reduced.

As described above, according to the first embodiment, even if there is a defective portion in the memory cell portion 1, the function can be replaced by the redundant portion 2, so that the semiconductor which is normally defective due to the defect is obtained. The integrated circuit device can be rescued, the yield can be improved, and a test port, a comparison circuit 7 and a defective memory cell address holding unit 8 are provided, so that a test can be performed during operation and software It is possible to identify defective parts in pre-shipment tests, which are usually performed when repairing semiconductor integrated circuit devices with defective memory cells, or change to hard-wired by laser trimming etc. This eliminates the need for the process of performing the test, and provides effects such as a reduction in test cost.

Since the failure is detected by comparing the write data with the read data, the determination as to whether or not a failure depends on the held data. That is, depending on the held data, the defective part also operates normally in a pseudo manner. For example, when "0" is written at the location of the "0" fixed failure, replacement is unnecessary. Therefore, such data does not need to be held in the redundant unit 2, and the storage capacity of the redundant unit 2 can be reduced correspondingly, and the chip cost can be reduced. In addition, it is not necessary to replace unused addresses with the redundant unit 2, and only the addresses (areas) that are actually used need to be repaired, so that chip cost can be reduced. Furthermore, once a mismatch is detected, there is no need to perform a match comparison on the corresponding address thereafter, so that the processing time can be shortened, and the operation rate of the comparison circuit 7 is reduced to reduce power consumption. When the defective memory cell address holding unit 8 and the redundant unit 2 cannot cope with a large number of defective memory cells, the defective memory cell address holding unit 8 outputs an OVF signal. Error processing and the like can be performed by distributing the data to the like, so that malfunction of the system can be avoided.

Embodiment 2 FIG. 4 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a second embodiment of the present invention. The same or corresponding parts as those in the first embodiment of FIG. The description is omitted here. The data latch 6 according to the second embodiment is different from that of the first embodiment shown in FIG. 1 in that the data latch 6 is constituted by only one latch.

Here, the basic operation is the same as that of the first embodiment, and the duplicate description will be omitted. During a write operation, write data input from the data input terminal DI is temporarily held in the data latch 6 and also input to the normal port of the memory cell unit 1. The data held in the data latch 6 and the data read from the test port of the memory cell unit 1 after one cycle are compared by a comparator circuit 7. If the data does not match, the comparator circuit 7 outputs a hit signal indicating the mismatch. Then, the address is held in the defective memory cell address holding unit 8 and the data held in the data latch 6 is written in the redundant unit 2.

FIG. 5 is an explanatory diagram for explaining the operation of the memory block according to the second embodiment for each cycle.
In FIG. 5, for the sake of simplicity, it is assumed that redundant unit 2 has two memory cells and defective memory cell address holding unit 8 has two address registers. Hereinafter, the operation will be described in detail with reference to FIG. First, in the first cycle, write data for the address A is input to the normal port of the memory cell unit 1. Next, in the second cycle, the write data for the address A input to the normal port in the previous cycle (first cycle) is held in the data latch 6, and the address A of the memory cell unit 1 read from the test port is read. The read data is compared with the comparison data by the comparison circuit 7. When a mismatch is detected as a result of the match comparison, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the first defective memory cell address register (1) holds the address A, and the first memory cell (1) of the redundant unit 2 holds the write data for the address A once held in the data latch 6. . On the other hand, in the second cycle, write data for address B is also input to the normal port.

Next, in the third cycle, the write data for the address B input to the normal port in the previous cycle (second cycle) is held in the data latch 6. The write data for the address B held by the data latch 6 is:
The read data at the address B of the memory cell unit 1 read from the test port is compared with the read data at the comparison circuit 7. If the result of the match comparison is a match, the data written to the address B of the memory cell unit 1 has been normally read, and thus the data read from the memory cell unit 1 is used. That is, the address B is not held in the defective memory cell address holding unit 8, and data relating to the address B is not held in the redundant unit 2. On the other hand, in the third cycle, input of write data for the address C is also performed to the normal port.

Next, in the fourth cycle, write data for the address C input to the normal port in the previous cycle (third cycle) is held in the data latch 6. The write data for the address C held by the data latch 6 is:
The read data at the address C of the memory cell section 1 read from the test port is compared with the read data at the comparator 7. If the result of the match comparison is a mismatch, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the second defective memory cell address register (2)
Holds the address C, and the second memory cell (2) of the redundant unit 2 holds the write data for the address C held in the data latch 6. On the other hand, the memory cell unit 1
The normal port performs a read operation on the address A in the fourth cycle. Since this address A matches the address held in the first defective memory cell address register (1), the data held in the first memory cell (1) of the redundant unit 2 is transferred to the address A. The data is output from the data output terminal DO as read data.

Next, in the fifth cycle, a second write operation for address A is performed for the normal port.
Here, the address A is held in the first defective memory cell address register (1), and the first defective memory cell address is written by a write operation to the address held in the first defective memory cell address register (1). The data held in the cell address register (1) and the first memory cell (1) of the redundant unit 2 are cleared once, or the first defective memory cell address register (1) and the first memory of the redundant unit 2 Cell (1) is set to a state where new data can be overwritten.

Next, in the sixth cycle, the write data corresponding to the address A input to the normal port in the previous cycle (fifth cycle) is held in the data latch 6, and the write data of the memory cell unit 1 read from the test port is read. The read data at the address A is compared with the comparison data by the comparison circuit 7. As a result of the match comparison,
If a match is detected, the data written to the address A of the memory cell unit 1 has been normally read. Therefore, this data is read using the data of the memory cell unit 1 and the address A is defective. Neither is held in the memory cell address holding unit 8, nor is data related to the address A held in the redundant unit 2. On the other hand, in the sixth cycle, write data for the address D is also input to the normal port.

Next, in the seventh cycle, the write data for the address D input to the normal port in the previous cycle (the sixth cycle) is held in the data latch 6. The write data for the address D held by the data latch 6 is
The read data at the address D of the memory cell unit 1 read from the test port is compared with the read data at the comparator 7. If the result of the match comparison is a mismatch, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the first defective memory cell address register (1)
Holds the address D, and the first memory cell (1) of the redundant unit 2 holds the write data for the address D held in the data latch 6. On the other hand, the memory cell unit 1
The normal port performs a read operation on the address B in the seventh cycle. Since this address B is not held in the defective memory cell address holding section 8, a normal read operation using the memory cell section 1 is performed, and the data held in the address B of the memory cell section 1 is read data. Is output from the data output terminal DO.

Next, in the eighth cycle, a read operation for address C is performed for the normal port. This address C is stored in the second defective memory cell address register (2).
, The write data held in the second memory cell (2) of the redundant unit 2 is output from the data output terminal DO as read data. Next, in the ninth cycle, the read operation for the address A is performed for the normal port. However, since the address A is not held in the defective memory cell address holding unit 8, the address A of the memory cell unit 1 is read. Is held at the data output terminal D as read data.
Output from O.

Next, in the tenth cycle, a second write operation for address C is performed for the normal port. Since this address C matches the address held in the second defective memory cell address register (2), the second defective memory cell address register (2) and the second memory cell (2) of the redundant unit 2 Is temporarily cleared or after the second defective memory cell address register (2) and the second memory cell (2) of the redundant unit 2 are overwritable, the next cycle (eleventh cycle) In ()), a comparison is made with the read data from the test port.

FIG. 6 is a flowchart showing the procedure of the write operation in the memory block shown in FIG.
Hereinafter, this will be described in detail with reference to FIG. When a write operation is performed, first, in step ST11, write data is held in the data latch 6, and the write data is written to the normal port of the memory cell unit 1 in step ST12, and in step ST1.
3 is read from the test port. Next, in step ST14, the comparison circuit 7 compares the data held in the data latch 6 with the data read from the test port, and in step ST15, determines whether the data matches / mismatches. If the result of the determination is that there is a mismatch and a hit signal is output to the defective memory cell address holding unit 8 and the redundant unit 2, the process branches to step ST16, and the address to be written is held in the defective memory cell address holding unit 8 as the defective memory cell address. Then, the write data is held in the redundant section 2 and the write operation is completed.
If they match, the process branches to step ST17. If one address register of the defective memory cell address holding unit 8 holds the address of the write data,
The contents of the address register holding the address register are cleared, or the address register is set in an overwritable state. Further, if the redundant section 2 holds the corresponding write data, this is cleared or the corresponding memory cell of the redundant section 2 is set in a state where overwriting is possible. Then, the write operation ends.

As described above, according to the second embodiment, a defective semiconductor integrated circuit device can be rescued, and the yield can be improved. Can reduce the test cost, reduce the redundant unit 2, eliminate the need to replace unused addresses, reduce the chip cost, and avoid the malfunction of the system by error processing based on the OVF signal. An effect similar to that of the first embodiment, such as being possible, is obtained.

Further, each time a write operation is performed, the comparison circuit 7 determines match / mismatch, and in the case of a mismatch, the data held in the data latch 6 is transferred to the redundant unit 2. There is no need to prepare a plurality of sets, the circuit scale can be reduced, and the chip cost can be reduced. Also, for the address that once becomes unmatched, if it is determined that the data written next is not pseudo-bad, the redundant portion 2 can be temporarily released, and the redundant portion 2 as a whole can be released. Since many defective parts can be relieved, the effect of reducing the chip cost can be obtained.

Embodiment 3 FIG. FIG. 7 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a third embodiment of the present invention. In FIG. 7, the same or corresponding parts as those in the second embodiment shown in FIG. And the description is omitted. The memory block according to the third embodiment has a data input terminal DI during a write operation.
4 is different from that of the second embodiment shown in FIG. 4 in that the input write data is simultaneously written into the redundant unit 2 together with the data latch 6.

Here, the basic operation is the same as that of the first embodiment, and a duplicate description will be omitted. During a write operation, write data input from the data input terminal DI is temporarily held in the data latch 6 and also input to the normal port of the memory cell unit 1 and the redundant unit 2. The input address is held in the defective memory cell address holding unit 8 as a defective memory cell address. The data held in the data latch 6 and the data read from the test port of the memory cell unit 1 after one cycle are compared by a comparison circuit 7. The address is already sent to the defective memory cell address holding unit 8 and the data already written in the redundant unit 2 is also held as it is.

FIG. 8 is an explanatory diagram for explaining the operation of the memory block according to the third embodiment for each cycle.
In FIG. 8, for the sake of simplicity, it is assumed that redundant unit 2 has two memory cells and defective memory cell address holding unit 8 has two address registers. Hereinafter, the operation will be described in detail with reference to FIG. First, in the first cycle, write data for the address A is input to the normal port of the memory cell unit 1. Next, in the second cycle, the write data for the address A input to the normal port in the previous cycle (first cycle) is held in the data latch 6 and the first memory cell (1) of the redundant unit 2, and The address A is held in the first defective memory cell address register (1). The write data held in the data latch 6 is compared with read data of the address A of the memory cell unit 1 read from the test port by the comparison circuit 7. As a result of the match comparison,
When a mismatch is detected, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the write data written in the first memory cell (1) of the redundant unit 2 is held as it is, and the address A is also held in the first defective memory cell address register (1). . On the other hand, in the second cycle, write data for address B is also input to the normal port.

Next, in the third cycle, write data for the address B input to the normal port in the previous cycle (second cycle) is held in the data latch 6 and the second memory cell (2) of the redundant unit 2. You. The address B is held in the second defective memory cell address register (2).
The write data for the address B held by the data latch 6 is compared with the read data of the address B of the memory cell unit 1 read from the test port by the comparison circuit 7. If the result of the coincidence comparison is a match, the data written to the address B of the memory cell unit 1 has been read normally, and this data is read out from the memory cell unit 1.
Is used. Therefore, the write data relating to the address B is cleared from the second memory cell (2) of the redundant unit 2, or the second memory cell (2) of the redundant unit 2 is set in a state where overwriting is possible. Similarly, the address B is cleared from the second defective memory cell address register (2) or the second defective memory cell address register (2) is set in a state in which overwriting is possible. On the other hand, in the third cycle, input of write data for the address C is also performed to the normal port.

Next, in the fourth cycle, write data for the address C input to the normal port in the previous cycle (third cycle) is held in the data latch 6 and the second memory cell (2) of the redundant unit 2. You. Further, the address C is held in the second defective memory cell address register (2).
The write data for the address C held in the data latch 6 is compared with read data of the address C of the memory cell unit 1 read from the test port by the comparison circuit 7. If the result of the match comparison is a mismatch, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the write data written in the second memory cell (2) of the redundant section 2 is held as it is, and the address C is also held in the second defective memory cell address register (2). .
On the other hand, the normal port of the memory cell unit 1 performs the read operation for the address A in the fourth cycle. This address A is the first defective memory cell address register (1)
Therefore, the data held in the first memory cell (1) of the redundant unit 2 is output from the data output terminal DO as read data for the address A.

Next, in the fifth cycle, a second write operation for address A is performed for the normal port.
Here, the address A is held in the first defective memory cell address register (1), and the first defective memory cell is written by the write operation to the address held in the first defective memory cell address register (1). The data held in the cell address register (1) and the first memory cell (1) of the redundant unit 2 is temporarily cleared or
Of the defective memory cell address register (1) and the first memory cell (1) of the redundant unit 2 are made overwritable.

Next, in the sixth cycle, write data for the address A input to the normal port in the previous cycle (fifth cycle) is held in the data latch 6 and the first memory cell (1) of the redundant unit 2. Address A is the first
In the defective memory cell address register (1). The write data held in the data latch 6 is compared with read data of the address A of the memory cell unit 1 read from the test port by the comparison circuit 7. As a result of the match comparison, if a match is detected, the data written to the address A of the memory cell unit 1 has been read normally, and the data read from the memory cell unit 1 is used. You. Therefore, the write data relating to the address A is cleared from the first memory cell (1) of the redundant unit 2 or the first memory cell (1) of the redundant unit 2 is set in a state where overwriting is possible. Similarly, the address A is cleared from the first defective memory cell address register (1), or the first defective memory cell address register (1) is set to a state in which overwriting is possible. On the other hand, in the sixth cycle, write data for the address D is also input to the normal port.

Next, in the seventh cycle, the write data for the address D input to the normal port in the previous cycle (the sixth cycle) is held in the data latch 6 and the first memory cell (1) of the redundant unit 2. You. Further, the address D is held in the first defective memory cell address register (1).
The write data for the address D held by the data latch 6 is compared with read data of the address D of the memory cell unit 1 read from the test port by the comparator 7. If the result of the match comparison is a mismatch, a hit signal is sent to the defective memory cell address holding unit 8 and the redundant unit 2. As a result, the first memory cell (1) of the redundant unit 2
Is held as it is, and the address D is also held in the first defective memory cell address register (1). On the other hand, the normal port of the memory cell unit 1 performs the read operation for the address B in the seventh cycle. Since this address B is not held in the defective memory cell address holding section 8, a normal read operation using the memory cell section 1 is performed, and the data held in the address B of the memory cell section 1 is read data. Is output from the data output terminal DO.

Next, in the eighth cycle, the read operation for the address C is performed for the normal port. This address C is stored in the second defective memory cell address register (2).
Is output as read data from the data output terminal DO. Next, in the ninth cycle, the read operation for the address A is performed for the normal port. However, since the address A is not held in the defective memory cell address holding unit 8, the address A of the memory cell unit 1 is read. Is output from the data output terminal DO as read data.

Next, in the tenth cycle, a second write operation for address C is performed for the normal port. Since this address C matches the address held in the second defective memory cell address register (2), the second defective memory cell address register (2) and the second memory cell (2) of the redundant unit 2 After once clearing the data or setting the second defective memory cell address register (2) and the second memory cell (2) of the redundant unit 2 to be overwritable, the next cycle (eleventh cycle)
, A match comparison with read data from the test port is performed.

FIG. 9 is a flowchart showing the procedure of a write operation in the memory block shown in FIG.
Hereinafter, this will be described in detail with reference to FIG. When a write operation is performed, first, in step ST61, write data is held in the data latch 6 and the redundant unit 2, and an input address is held in the defective memory cell address holding unit 8 as a defective memory cell address. The write data is written to the normal port of the memory cell unit 1 in step ST62, and
Reading from the test port by 63 is performed. Next, in step ST64, the comparison circuit 7 compares the data held in the data latch 6 with the data read from the test port, and in step ST65, determines the match / mismatch. If the result of the determination is a mismatch, the process branches to step ST66, where the defective memory cell address already held in the defective memory cell address holding unit 8 is still held, and the write data is stored in the redundant unit 2
, The write operation is terminated.
If they match, the process branches to step ST67 to clear the write data held in the redundant unit 2 or to make the portion holding the write data overwritable. Similarly, the defective memory cell address held in the defective memory cell address holding unit 8 is cleared, or the portion holding the address becomes overwritable. Then, the write operation ends.

As described above, according to the third embodiment, a defective semiconductor integrated circuit device can be rescued, and the yield can be improved. Can reduce the test cost, reduce the redundant unit 2, eliminate the need to replace unused addresses, reduce the chip cost, and avoid the malfunction of the system by error processing based on the OVF signal. An effect similar to that of the first embodiment, such as being possible, is obtained.

Further, since the write data is transferred to the redundant unit 2 every time a write operation is performed, the data latch 6
It is not necessary to prepare a plurality of sets, the circuit scale can be reduced, and the chip cost can be reduced. Also, with respect to the address that once becomes unmatched, when it is determined that the data written next is not pseudo-failure, the redundant unit 2 can be released once,
Since a large number of defective parts can be relieved with a small number of redundant parts 2 as a whole, the effect of reducing the chip cost can be obtained.

Embodiment 4 FIG. 10 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 4 of the present invention. In the figure, 1
Reference numeral 0 denotes a RAM memory cell unit having a plurality of ports, one of which is a read port serving as a test port. In the illustrated example, the memory cell unit includes two ports, an A port and a B port. A normal port used for normal read / write operations is used, and a B port is used as a test port for exclusive use for testing. Reference numeral 11 denotes an address decoder for port A of the memory cell unit 10, reference numeral 12 denotes an address decoder for port B, and reference numeral 13 denotes an address latch for temporarily holding an address to the address decoder 12 for port B.

Reference numeral 14 denotes a data latch for temporarily holding data input from the data input terminal DI. Reference numeral 15 denotes write data held in the data latch 14 and 1
B port (test port) of the memory cell unit 10 after the cycle
This is a comparison circuit that compares the data read from the data. 16 holds the address at that time when a mismatch is detected by the comparison circuit 15 and information on the bit at which the mismatch was detected. A defective memory cell address / bit information holding unit that generates an output data control signal based on the output data control signal generates an OVF signal when the memory cell unit 10 has many defects and cannot respond. Reference numeral 17 denotes the data read from the A port (normal port) of the memory cell unit 10 as it is, or inverts the defective bit according to the output data control signal generated by the defective memory cell address / bit information holding unit 16. This is a selector for correcting and outputting from the data output terminal DO.

Next, the operation will be described. In operation, an address is directly input to the address decoder 11 and is also input to an address latch 13 disposed before the address decoder 12 to be temporarily held. As described above, in the fourth embodiment as well, in the test port of the memory cell unit 10, data is read in the next cycle of the write access of the normal port. Therefore, the address decoding for the test port by the address decoder 12 may be performed only after the write operation of the normal port, and the address holding in the address latch 13 is performed by the write operation of the normal port. It may be performed only in the next cycle of the operation.

Data input from the data input terminal DI is held in the data latch 14 as in the first embodiment, and is also input to the normal port of the memory cell unit 10 as write data. Data latch 14
The data held in the comparator circuit 15 and the data read from the test port of the memory cell unit 10 after one cycle.
And a match / mismatch determination is made. If the two match, the write / read operation for the corresponding address of the memory cell unit 10 has been performed normally, so that the read data from the corresponding address of the memory cell unit 10 remains unchanged during the read operation for that address. The data is output from the data output terminal DO via the selector 17.

On the other hand, if they do not match, there is a defective memory cell at that address in the memory cell section 10, so that the address and the information on the mismatch detection bit are stored in the defective memory cell address / It is held in the bit information holding unit 16. Thereafter, in a read operation for that address, the defective memory cell address /
In response to the output data control signal generated by the bit information holding unit 16 based on the held information, the selector 17 inverts and inverts the data of the mismatch detection bit and outputs it from the data output terminal DO.

Here, if the memory cell unit 10 has many defects and the address register prepared by the defective memory cell address / bit information holding unit 16 cannot handle the defect, the defective memory cell address / bit information holding unit 1
6 outputs an OVF signal to notify the system, that is, the semiconductor integrated circuit device, that a memory operation abnormality has occurred.

Next, the operation of generating an output data control signal by defective memory cell address / bit information holding unit 16 will be described. Here, FIG. 11 is a block diagram showing an internal configuration of the defective memory cell address / bit information holding unit 16. In the figure, reference numeral 20 denotes a plurality of defective memory cell address registers for storing a B port address when a mismatch is detected by the comparison circuit 15, and reference numeral 21 denotes a defective memory cell address register 20 for storing mismatched bit information. And the same number of bit information registers. Reference numeral 22 denotes the same number of correction flags as the number of defective memory cell address registers 20, which are set when a mismatch is detected. 2
Reference numeral 3 denotes an address comparison circuit for comparing the A port address with the address stored in the defective memory cell address register 20 during the read operation of the memory cell section 10, and the same number of address comparison circuits as the defective memory cell address register 20; The selector selects one of the bit information registers 21 based on a comparison result of the comparison circuit 23 and generates an output data control signal based on information held by the bit information register 21. An OR circuit 25 performs a logical OR operation on a signal indicating a match to a mismatch with respect to all bits of the write data from the comparison circuit circuit and outputs the result to the correction flag 22.
Is an AND circuit that performs a logical product operation on the outputs of all correction flags 22 and outputs the result as an OVF signal.

As described above, the write data input to the normal port (A port) of the memory cell unit 10 is temporarily held in the data latch 14 and read from the test port (B port) in the next cycle of the write operation. The comparison data 15 is compared with the output data. As a result, when a mismatch is detected in any one of the bits, the correction flag 22 is set in the defective memory cell address / bit information holding unit 16 and the correction flag 22 stores the A in the corresponding defective memory cell address register 20. The address in the cycle before the port address, that is, the B port address temporarily held in the address latch 13 is stored as the defective memory cell address. Further, the bit information in which the mismatch is detected by the comparison of the comparison circuit 15 is stored in the corresponding bit information register 21.

Thereafter, when a read operation is performed on the address stored in the defective memory cell address register 20 from the normal port, the address comparing circuit 23 causes the defective memory cell stored in the defective memory cell address register 20 to be read. A match between the address and the A port address is compared. If there is a defective memory cell address register 20 storing a defective memory cell address that matches the A port address, the address comparison circuit 23 controls the selector 24 to store the defective memory cell address in the bit information register 21 corresponding to the defective memory cell address register 20. The stored correction data is output as an output data control signal.

FIG. 12 is a flowchart showing the operation procedure of such a defective memory cell address / bit information holding unit 16. When the process starts, first, in step ST
At 21, it is determined whether the operation of the A port, which is a normal port, is a write operation or a read operation. If the operation of the A port is a write operation, step ST
22, the defective memory cell address register 20 in which the correction flag 22 is clear and the data latch 14
Fetch the current address and data of the A port. Next, in step ST23, the comparison circuit 15 reads the data of the immediately preceding address from the test port B, and compares the read data with the data held in the data latch 14 in step ST24. As a result, if the read data matches the data held in the data latch 14 in all the bits, no correction is necessary. Therefore, in step ST25, the correction flag 22 is cleared, and the process ends. Further, if even one bit does not match, correction is necessary.
Is set, the bit information of the mismatched data is taken into the bit information register 21, and the process is terminated.

On the other hand, if the operation of the A port is a read operation, the process branches to step ST27. In this step ST27, if the read-accessed address is the same as the defective memory cell address stored in the defective memory cell address register 20 in which the correction flag 22 is set, the address is stored in the bit information register 21. An output data control signal for inverting and outputting the corresponding bit is generated based on the bit information. The output data control signal is sent to the selector 17, and the selector 17 inverts the data of the mismatch bit of the data read from the memory cell unit 10, corrects the data, and outputs the data from the data output terminal DO as read data.

As described above, according to the fourth embodiment, the yield of the semiconductor integrated circuit device can be improved, the test cost and the chip cost can be reduced, and the malfunction of the system can be avoided. In addition to the same effects as in the first embodiment, the redundant portion is not required, and only the bits that need to be corrected are corrected without replacing the memory cells of a plurality of bits including the defective portion. The effect that the cost can be further reduced is also obtained.

Embodiment 5 FIG. 13 is a block diagram showing a configuration of an address decoder in a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In the figure, FIG.
The same reference numerals denote the same components as in the first embodiment, and a description thereof will be omitted below. In the address decoder 3, reference numeral 30 denotes a first decoder for activating the word line of the redundant unit 2, and reference numeral 31 denotes a second decoder for activating the word line of the memory cell unit 1. As described above, in the fifth embodiment, the address decoder 3 is divided into the first decoder 30 and the second decoder 31.

FIG. 14 is a flowchart showing the procedure of the operation in the fifth embodiment. When the read or write operation of the memory cell unit 1 is started, first, in step ST31, it is checked whether the input address matches the address held in the defective memory cell address holding unit 8. . As a result, if they match, the corresponding address of the memory cell unit 1 has a defective bit. Therefore, the address is sent from the defective memory cell address holding unit 8 to the first decoder 30 in step ST32. Then, the word line of the corresponding address of the redundant unit 2 is activated, and the read / write of the redundant unit 2 is performed. At that time, the defective memory cell address holding unit 8
The word line of the memory cell unit 1 is not activated by clearing the non-coincidence signal from the second decoder 31 to the second decoder 31.

On the other hand, if the input address does not match the address held in the defective memory cell address holding section 8, there is no defective bit in the corresponding address of the memory cell section 1, so that in step ST33, A mismatch signal from the defective memory cell address holding unit 8 to the second decoder 31 is set. As a result, the second decoder 31 activates the word line of the corresponding address of the memory cell unit 1 and performs the read / write operation of the memory cell unit 1. At this time, since no address is sent from the defective memory cell address holding unit 8 to the first decoder 30, the word line of the redundant unit 2 is not activated.

As described above, according to the fifth embodiment, in addition to the same effect as in the first embodiment, the word line of the memory cell unit 1 or the redundant unit 2 is compared with the defective memory cell address. Since only one of the word lines is activated, the size of the address decode circuit of the memory cell unit 1 can be reduced. In addition, when the redundant unit 2 is used, the memory cell unit 1 does not operate, so that consumption is reduced. Effects such as reduction of power can be obtained.

Embodiment 6 FIG. FIG. 15 is a block diagram showing a main part of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. In the figure, reference numerals 40 and 41 denote FIGS.
Alternatively, it is a memory block equivalent to that shown in FIG. 10, and here, parts other than the defective memory cell address holding unit 8 are not shown. Although FIG. 15 shows the defective memory cell address holding unit 8,
The same applies to the defective memory cell address / bit information holding unit 16. Also, the case where two sets of memory blocks 40 and 41 are illustrated, but three or more sets may be used. Reference numeral 42 denotes a data processing unit that controls the memory blocks 40 and 41.

In the memory blocks 40 and 41, 8
Is a defective memory cell address holding unit shown by the same reference numeral in FIG.
43, its memory block 40 or 41
A plurality of redundant memory cells (not shown)
And a defective memory cell address register 44 for storing a defective memory cell address when a mismatch is detected. Reference numeral 44 denotes a defective memory cell address register provided for each of the defective memory cell address registers 43. Is a use flag that is set when is detected. 4
An AND circuit 5 generates the full flag signal to the data processing unit 42 by taking the AND logic of each of the use flags 44.

Next, the operation will be described. In the operation, when it is detected that the result of the match comparison by the comparison circuit (not shown) does not match, that is, when it is detected that the memory cell to be written has a defect, one of the defective memory cell address registers 43 of the defective memory cell address holding unit 8 is reset. Finally, the address of the defective memory cell is held as the defective memory cell address, and the use flag 44 corresponding to the defective memory cell address register 43 is set to "1".
Is set. When "1" is set to all of the use flags 44, an AND circuit 45 taking the AND logic thereof
Causes the full flag signal to be asserted. The full flag signal from the memory block 40 is sent to the data processing unit 42, and when the full flag signal is asserted, the data processing unit 42 switches to another memory block 41 and executes a write operation.

FIG. 16 is a flowchart showing the procedure of such a transfer write operation to the memory block 41. In step ST41, it is determined whether or not all the use flags 44 are set to "1" as a result of the operation of setting the use flag 44 to "1". As a result, when all the use flags 44 are set to “1”, the AND circuit 45 asserts the full flag signal in step ST42 and sends it to the data processing unit 42. Upon detecting that the full flag signal has been asserted, the data processing unit 42 determines in step ST43 whether the next access is other than a write operation such as a write operation or a read operation. The process ends. On the other hand, if the next access is a write operation, since all of the defective memory cell address registers 43 of the defective memory cell address holding unit 8 are used, there is a possibility that the write operation may not be performed normally. The processing unit 42 changes the operation to the data write operation to the memory block 41 in step ST44, and ends a series of flag processing.

As described above, according to the sixth embodiment, in addition to the same effects as in the first embodiment, the previously prepared defective memory cell address holding unit 8 (defective memory cell address / bit information Holding section 16) and redundant section 2
Since the full flag signal is asserted and output to the data processing unit 42 when it is no longer possible to respond, the system can be warned by the assertion of the full flag signal and the data can be distributed to other memory blocks. This has the effect that the system can be prevented from being in an error state.

Embodiment 7 FIG. In the sixth embodiment described above, when the previously prepared redundant portion is used up, the full flag signal is asserted to warn the system to switch and hold another buffer. However, the OVF signal may be asserted when the redundant portion prepared in advance is used up and further when the mismatch processing is detected.

FIG. 17 is a block diagram showing a main part of such a semiconductor integrated circuit device according to the seventh embodiment of the present invention. The same reference numerals as in FIG. 15 denote the respective parts, and a description thereof will be omitted. I do. In the seventh embodiment, the AND circuit 45 sets all the use flags 44 to “1”.
Further, when the occurrence of mismatch processing is detected by a comparison circuit (not shown), the OVF signal to the data processing unit 42 is asserted from the AND logic result.

Next, the operation will be described. In the operation, as in the case of the sixth embodiment, if a memory cell to be written has a defect and a mismatch is detected by a comparison comparison (not shown) of a comparison circuit (not shown), one of the defective memory cell address registers 43 is detected. Then, the address of the defective memory cell is held as the defective memory cell address, and the use flag 44 corresponding to the defective memory cell address register 43 is set to "1". Use flag 4
After "1" is set to all of the counters 4, the comparison circuit 7
When an inconsistency is detected by the AND circuit 45, the OVF signal is asserted by the AND circuit 45 which takes the AND logic. The OVF signal from the memory block 40 is sent to the data processing unit 42, and when the OVF signal is asserted, the data processing unit 42 switches to another memory block 41 and executes a write operation.

FIG. 18 is a flowchart showing the procedure of such a transfer write operation to the memory block 41. After all the use flags 44 are set to "1" by the operation of setting the use flag 44 to "1", in the comparison circuit 7, it is determined whether or not further mismatch is detected in step ST51. As a result, all the use flags 44 are set to "1", and if a mismatch is detected, the AND circuit 45 asserts the OVF signal in step ST52 and sends it to the data processing unit 42. When detecting that the OVF signal has been asserted, the data processing unit 42 determines in step ST53 whether the next access is a write operation or a read operation.

As a result of the determination, if the next access is a read operation, the data processing section 42 ends this flag processing as it is. On the other hand, if the next access is a write operation,
The data processing unit 42 determines that the write operation to the memory block 40 has not been performed normally, and executes an error process such as a write operation to the memory block 41 with the same data in step ST54 to execute a series of operations. The flag processing ends. The error processing is
The processing may be such that the data processing unit 42 stops the operation of the system and notifies the outside of the system that a failure has occurred in the memory block 40.

As described above, according to the seventh embodiment, the defective memory cell address holding unit 8 (defective memory cell address / bit information holding unit 16) and the redundant unit 2 which have been prepared in advance can cope with. If not, the OVF signal is asserted and output to the data processing unit 42, so that the assertion of the OVF signal makes it possible to perform error processing such as rewriting the write data to another memory block 41. Therefore, malfunction of the system can be avoided, and the use flags 44 are all "1".
Even after being set to, the memory block 40 can be used for the subsequent write operation until data mismatch occurs, so that the frequency of exception processing using the memory block 41 executed by the data processing unit 42 is reduced. It is possible to obtain effects such as suppression of system performance degradation.

Embodiment 8 FIG. The memory block of each of the above embodiments has only one memory cell unit that simply stores a plurality of data. On the other hand, the memory block according to the eighth embodiment has an odd number of memory cell sections, and the same data is stored and read in each of the memory cells during a write operation so that these memory cell sections have the same contents. This is to detect a defective portion of a memory cell by majority operation of read data.

FIG. 19 is a block diagram showing a main part of such a semiconductor integrated circuit device according to the eighth embodiment of the present invention. In the figure, three 50, 51, 52 are prepared,
These are memory cell sections having different structures. Although the case where three of the memory cell units 50 to 52 are prepared is illustrated here, an odd number of three or more is sufficient. Reference numerals 53, 54 and 55 denote memory cell units 50 to 5 respectively.
2 are address decoders individually prepared for the respective address decoders. Reference numeral 56 denotes a majority selection circuit that performs a majority operation on data read from the same address of each of the memory cell units 50 to 52.

When performing a write operation, first, write data is applied to each of the memory cell units 50 to 52 from the data input terminal DI, and the address decoders 53 to 5 are applied from the address input terminal A.
5 is input with a write address. In the memory cell unit 50, the input write data is stored at the address decoded by the corresponding address decoder 53. Similarly, the memory cell unit 51 stores the input write data at the address decoded by the corresponding address decoder 54, and the memory cell unit 52 stores the input write data at the address decoded by the corresponding address decoder 55.
The data written in each of the memory cell units 50 to 52 is the same data.

Next, the aforementioned address is input to the address input terminal A to perform a read operation. Each memory cell unit 50-5
In 2, the data is read from the addresses decoded by the corresponding address decoders 53 to 55, respectively.
The read data is input to the majority selection circuit 56 and a majority operation is performed. As a result, if all the read data match, it is determined that the corresponding address of each of the memory cell units 50 to 52 has no defect. If the two read data match and the other read data is different, it is determined that the corresponding address of the memory cell portion from which a small number (one) of the read data has been read has a defect. .

As described above, according to the eighth embodiment, the majority is selected based on the read data from the three memory cell units 50 to 52, so that the memory cell units 50 to 5 are selected.
2 can be easily detected even if there is a defective portion, so that the yield can be improved, and the dynamic comparison is performed by the majority decision selection circuit 56, so that it is not necessary to specify a defective portion by performing a test in advance. Costs can be reduced. Since the configuration is such that data selected by majority logic is output, change processing by H / W such as laser trimming is not required, so that costs can be reduced and not only the odd-numbered memory cell sections 50 to 52 having different structures. , It is possible to detect a defect caused by the structure of the memory cell units 50 to 52, and furthermore, the address decoder 53
To 55 are prepared for each of the memory cell units 50 to 52, so that not only the failure of each of the memory cell units 50 to 52 but also the failure of the address decoders 53 to 55 can be repaired. Can be

Embodiment 9 FIG. Also, instead of an odd number of memory cell sections storing the same data at the time of a write operation so as to have the same contents and a majority selection circuit for detecting a defective portion of the memory cell section by majority operation of read data, A semiconductor integrated circuit device according to a ninth embodiment of the present invention provides a memory cell unit having an odd number of memory cells in which the same data is stored during a write operation so as to have the same contents for each address, and the respective memory cells And a majority selection circuit for performing a majority operation on read data read from the memory cell and detecting a defective portion of the memory cell. That is, the memory cell section has three times as many memory cells as necessary.

FIG. 20 is a block diagram showing a main part of a semiconductor integrated circuit device according to a ninth embodiment of the present invention. In the figure, reference numeral 60 denotes a memory cell unit, and reference numeral 61 denotes its address decoder. Reference numerals 62, 63, and 64 denote memory cells in the memory cell unit 60.
3 for each bit of the write data for each address of
One 1-bit memory cell is provided,
One memory cell 62 to 64 holds the same data. 65, 66, and 67 represent these memory cells 62 to
A bit line for reading the data held in 64 is a majority selection circuit for performing a majority operation on the data read from these bit lines 65 to 67.

When performing a write operation, first, write data is input from the data input terminal DI to the memory cell unit 60, and a write address is input from the address input terminal A to the address decoder 61. In the memory cell unit 60, each bit of the input write data is stored in each set of three memory cells of the address decoded by the address decoder 61. Here, each address of the memory cell unit 60 has three memory cells for each bit. For example, each bit of the same write data input from the data input terminal DI is stored in the adjacent one-bit memory cells 62 to 64.

Next, the aforementioned address is input to the address input terminal A to perform a read operation. In the memory cell section 60, data is read based on the address decoded by the address decoder 61, and the same written data is read from the adjacent 3-bit memory cells 62 to 64. In this way, the data read from the adjacent 3-bit memory cells 62 to 64 are input to the majority selection circuit 68 via the respective bit lines 65 to 67, and the majority operation is performed. As a result, if the read data of the three bits match, it is determined that the corresponding bit has no defect. If the two read data match and the other read data is different, it is determined that the bit from which a small number (one) of the read data is read has a defect.

In the above description, the memory cell unit 60 in which each address has three times the required number of memory cells is shown. However, it is sufficient if the address is an odd multiple of three or more. In the circuit 68, the adjacent bit line 65
Although the majority operation of the read data from .about.67 is performed, the adjacent bit lines need not necessarily be adjacent.

As described above, according to the ninth embodiment, even if there is a defective portion in the memory cell portion 60, the yield can be improved because it can be easily detected by majority decision, and the defective portion can be tested in advance by dynamic comparison. Since there is no need to specify a location, test costs can be reduced. Since the data selected by the majority logic is output, change processing by H / W such as laser trimming is not required, cost can be reduced, and the bit lines 65 to 65 to be compared by majority decision.
Since the 67 can be present in the vicinity (adjacent), effects such as shortening of wiring, reduction in power consumption, and improvement in performance such as high speed can be obtained.

Embodiment 10 FIG. An odd-numbered memory cell part or a memory cell having an odd-numbered memory cell into which the same data is written at the time of writing so as to have the same contents, and a majority decision by detecting a defective part of the memory cell part by majority operation of read data. Instead of the majority selection circuit that outputs the result of (1), the semiconductor integrated circuit device according to the tenth embodiment of the present invention includes two memory cell units storing the same data during a write operation so as to have the same contents, When the data read from these memory cell units do not match, a comparator circuit is provided for checking the parity bit and outputting the correct data.

FIG. 21 is a block diagram showing a main portion of such a semiconductor integrated circuit device according to the tenth embodiment of the present invention. In the figure, 70 and 71 are memory cell units having the same address, and 72 is an address decoder for decoding the addresses of these two memory cell units 70 and 71. Reference numeral 73 denotes a parity bit holding unit that holds parity of write data obtained at the time of a write operation for each address of the memory cell units 70 and 71, and 74 denotes a comparison of coincidence of read data from the two memory cell units 70 and 71. And a comparator circuit for checking the parity bit holding unit 73 and outputting the correct data when a mismatch is detected.

When the write operation is performed, the write data input from the data input terminal DI is stored in the memory cell unit 70.
And 71 are written to the addresses decoded by the address decoder 72, respectively. Therefore, the same data is stored in the same address of these memory cell units 70 and 71. At that time, the parity bit holding unit 73
The parity of the write data is calculated and held in a portion corresponding to the address. Next, the address decoder 72
According to the address input to the memory cell unit 7,
From 0 and 71, data reading of the corresponding address is performed. This read data is input to the comparison circuit 74 and is compared for coincidence. As a result, the memory cell portion 7 on those two surfaces
If the read data of 0 and 71 do not match, the comparison circuit 74 checks the corresponding parity bit holding unit 73 and outputs the correct data from the data output terminal DO.

As described above, according to the tenth embodiment, even if there is a defective portion in the memory cell, the read data and the parity bit holding portion 7 of the plurality of memory cell portions 70 and 71 are provided.
3, the yield can be improved, and since the comparison is made dynamically, there is no need to specify a defective portion by performing a test in advance, and the test cost can be reduced. Since the correction is performed using the plurality of memory cell units 70 and 71 and the parity bit holding unit 73, a change process by H / W such as laser trimming is not required, and cost can be reduced. Memory cell section 7
Since it is sufficient to compare the read data of 0 and 71, the number of memory cell portions can be reduced as compared with the case of performing majority selection.
This has the effect of reducing the chip area and chip cost.

Embodiment 11 FIG. FIG. 22 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 11 of the present invention. In the figure, 1 is a memory cell unit, 2 is a redundant unit, 3 is an address decoder, 6 is a data latch, 7 is a comparison circuit, 8 is a defective memory cell address holding unit, and 9 is a selector, which are the same as those in FIG. These are the same as those in Embodiment 1 indicated by the reference numerals. Reference numeral 80 denotes a self-test pattern generation unit that generates a set of test pattern addresses and data based on a trigger signal. Reference numeral 81 denotes an address input selector that selects one of the address of the test pattern generated by the self-test pattern generation unit 80 and the address input from the address input terminal A and uses the selected address as the address of the memory cell unit 1. 82 selects one of the data of the test pattern generated by the self test pattern generation unit 80 and the data input from the data input terminal DI,
This is a data input selector to be input to the memory cell unit 1.
The eleventh embodiment differs from the second embodiment in that the address decoder 4 and the address latch 5 are eliminated, and a self-test pattern generator 80, an address input selector 81, and a data input selector 82 are provided. ing.

Next, the operation will be described. In operation, when there is an input such as power ON, test mode, or reset, the self-test pattern generation unit 80 starts the self-test operation using the input as a trigger signal, and generates an address and data set of an arbitrary test pattern. When the self test mode is reached by the assertion of the trigger signal, the address input selector 81 and the data input selector 82 select the address or data of the test pattern output from the self test pattern generation unit 80 until the self test is completed. I do. While the address / data set of the test pattern generated by the self-test pattern generation unit 80 is being input to the memory cell unit 1, the memory block continuously performs the write operation.

As described above, when the test pattern data is input to the memory cell unit 1, the data read from the memory cell unit 1 and the written test data are written in the same manner as in the write operation in the first embodiment. A match comparison with the pattern data is performed. If a mismatch is detected, it is determined that the memory cell unit 1 has a defect, and the address to be processed by the redundant unit 2 is stored in the defective memory cell address holding unit 8 as a defective memory cell address. Thereafter, when a read access is made to the defective portion of the memory cell unit 1, data is read from the memory cell of the redundant unit 2 specified by the defective memory cell address stored in the defective memory cell address holding unit 8.

If such a test operation is carried out at the time of power-on or reset, or by executing a specially provided test mode, the defective memory cell address holding unit 8, which has prepared many defects in the memory cell unit 1, And redundant part 2
Can be confirmed prior to normal operation by observing the OVF signal, and it can be used as a GO / NG test before shipment. In that period, only the setting of the test mode by the assertion of the trigger signal and the observation of the OVF signal need be performed.

In the above description, the previously defined march (MARC) is used as the address / data set of the test pattern generated by the self-test
H) and an algorithmic checker (CHECKER) pattern are used. However, in the present invention, it is unnecessary to generate the expected value of the test pattern and to compare the expected value with the test pattern. As the pattern, an address / data set generated as a random number can be used.

In the above description, the case where the OVF signal is output from the defective memory cell address holding unit 8 has been described. However, it goes without saying that the full flag signal described in the sixth embodiment may be output. Absent.

As described above, according to the eleventh embodiment, the yield is improved by replacement with redundant portion 2,
It is not necessary to identify defective parts in advance, thereby reducing test costs, reducing redundant parts 2 and reducing chip costs, eliminating the need to replace unused addresses, and eliminating H / W change processing such as laser trimming. As a result, the same effects as those of the first embodiment can be achieved. For example, it is possible to reduce the cost, and it is possible to avoid the malfunction of the system by distributing the data holding to another memory or the like and performing error processing. is there.

Further, if this test operation is performed at the time of power-on or reset, or by executing a specially provided test mode, the observation of the OVF signal allows the defective memory cell address holding unit 8 and the redundant unit prepared in advance. 2 can be checked prior to normal operation, and a test before shipment can be performed. During that time, a test mode is set by assertion of a trigger signal, and an OVF signal / full flag signal is Since only observations need to be made, the test cost can be further reduced. Also, since the match comparison is performed using write / read data instead of the expected value prepared in advance, the circuit for self-test is simple and has a small area. Also, the effect that can be realized by is obtained.

Embodiment 12 FIG. Embodiment 1 of the present invention
The semiconductor integrated circuit device according to No. 2 includes a self-test pattern generation unit 80 shared by a plurality of memory blocks and arranged outside these memory blocks. FIG. 23 is a block diagram showing a main part of a semiconductor integrated circuit device according to the twelfth embodiment. In the figure, 90, 91, 92, 93
Is a memory block equivalent to that according to the eleventh embodiment shown in FIG.
In that it does not have an individual 94
Is a self-test-pattern generating unit that is commonly used in these memory blocks 90 to 93 and supplies test pattern addresses / data sets to them. An OR 95 performs an OR operation on the OVF signals output from the memory blocks 90 to 93 and outputs the OR operation to the outside of the chip.
Circuit.

Each of the memory blocks 90 to 93 is
It receives the address / data set of the test pattern generated by the commonly used self test pattern generation unit 94. Each of the memory blocks 90 to 93 operates similarly to the memory block of the eleventh embodiment. That is, each of the memory blocks 90 to 93 holds the information on the detected defective portion in the defective memory cell address holding section 8, and thereafter, based on the information held in the defective memory cell address holding section 8, The memory cells of the redundant unit 2 are used in replacement. When a shortage occurs in the redundant section 2 in a certain memory block, the defective memory cell address holding section 8 generates an OVF signal and outputs the OVF signal to the outside of the chip via the OR circuit 95. Since the test pattern can be generated in a random manner, it can be shared by a plurality of memory blocks having different specifications (bit / word size).

In the above description, the case where the OVF signal is output from the defective memory cell address holding unit 8 has been described, but it goes without saying that the full flag signal described in the sixth embodiment may be output. Absent.

As described above, according to the twelfth embodiment, in addition to the effects of the eleventh embodiment, a circuit for a self test such as a self test pattern generation unit 94 includes a plurality of memory blocks 90 to 93. Since the circuit is commonly used, the size of the additional circuit can be reduced, the chip cost can be reduced, and the OVF signal / full flag signal becomes the logical sum output of the plurality of memory blocks 90 to 93. Since the self-test pattern generation unit 94 generates only the test pattern and the comparison is performed for each of the memory blocks 90 to 93, the self-test pattern generation unit 94 uses the memory blocks 90 to 93 having different configurations. An effect such as the fact that it becomes possible to commonly use 94 is obtained.

Embodiment 13 FIG. FIG. 24 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 13 of the present invention. In the figure, reference numeral 1 denotes a memory cell unit composed of a one-port RAM, 2 denotes a redundant unit, 3 denotes an address decoder, 6 denotes a data latch, and 7 denotes a data latch.
Is a comparison circuit, 8 is a defective memory cell address holding unit, 9 is a selector, and 81 is an address input selector, which are the same as those in the eleventh embodiment indicated by the same reference numerals in FIG. . An address holding buffer memory 83 is a 1RW memory having a plurality of words for holding an address input to the memory block. The write data is always stored in the redundant unit 2.
Is written to.

A read enable (RE) signal and a write enable (WE) signal are used as signals for controlling the read / write operation. Further, since the memory cell section 1 used in the thirteenth embodiment has only one read / write port as described above, in the next cycle of the write operation, the match of the immediately preceding write data is compared. Is not always possible. Therefore, the corresponding address is stored in the address holding buffer memory 83, and the write data is stored in the data latch 6.

When both the RE signal and the WE signal are disabled and the address to be tested is held in the address holding buffer memory 83, the address input selector 81 selects an address from the address holding buffer memory 83 to select the address. Output to the address decoder 3. As a result, the comparison circuit 7 compares the data read from the corresponding address in the memory cell unit 1 with the data held in the data latch 6, and if a mismatch is detected, the address is replaced with the defective memory. It is stored in the cell address storage unit 8. Note that this match comparison and holding of the defective memory cell address are performed in the same manner as in the second embodiment.

FIG. 25 is an explanatory diagram for describing the operation of the memory block according to the thirteenth embodiment for each cycle. FIG. 25 shows a system operation in this memory block, a test operation performed internally, and an address held in the address holding buffer memory 83 for each cycle. Hereinafter, the operation will be described in detail with reference to FIG. First, a write operation is performed on the address A in the first cycle. By this write operation, the address holding buffer memory 83
Holds address data “A”, and data latch 6
Holds write data. In the next second cycle, read and write operations are not performed.
The signal and the WE signal are disabled. During this period, the address data held in the address holding buffer memory 83 is based on “A” and the memory cell unit 1
The data is read from the memory cell at the address A, and the comparison circuit 7 compares the read data with the data held in the data latch 6. As a result, if a mismatch is detected, the data is stored in the redundant unit 2,
The address data is held in the defective memory cell address holding unit 8 as a defective memory cell address. If the result of the match comparison is a match, the address is not held in the defective memory cell address holding unit 8.

Next, in the third cycle, a read operation for address A is performed. When the result of the test operation performed in the second cycle does not match as the read data for the address A, data read from the corresponding memory cell of the redundant unit 2 indicated by the defective memory cell address is output. If they match, the data read from the address A of the memory cell unit 1 is output. Since the test operation for the address A is completed in the second cycle, the address data “A” held in the address holding buffer memory 83 is cleared in the third cycle. In the next fourth cycle, the read / write operation is not performed, and the RE signal and the WE signal are disabled. However, since the address holding buffer memory 83 is also cleared, the comparison circuit 7 performs the match comparison. No processing is performed.

Next, when a write operation to address B is performed in the fifth cycle, address data "B" is held in address holding buffer memory 83 in the same manner as in the first cycle, and the write data is held in data latch 6. Is done. Further, when the write operation for the address C is performed in the sixth cycle, the address data “C” is held in the address holding buffer memory 83 together with the address data “B” held in the previous fifth cycle. The write data is also held. If the read / write operation has not been performed in the seventh cycle, the data is compared with the address B held in the address holding buffer memory 83 in the same manner as in the second cycle. Further, if the read / write operation has not been performed in the eighth cycle, the data is compared with the address C held in the address holding buffer memory 83 in the same manner. Further, the address data B is cleared from the address holding buffer memory 83.

Thereafter, when a write operation is performed, the address data to be written is held in the address holding buffer memory 83 and the data is held in the data latch 6, and the RE signal and the WE signal are not written or read. When the enable period is reached, a match comparison is performed for the held addresses / data, and the address data in the address holding buffer memory 83 and the data in the data latch 6 for which the match comparison has been completed are cleared.

In the above description, the signal using the RE signal and the WE signal as the read / write control signal has been described, but the RW signal and the CS signal (module selection signal) may be used instead. It is.

As described above, according to the thirteenth embodiment, the yield is improved by replacing the redundant portion 2, the test cost can be reduced by not specifying the defective portion in advance, and the redundant portion 2 can be reduced. As a result, the replacement of unused addresses is not required, the change processing by H / W is not required, the cost can be reduced, and the malfunction of the system can be avoided by distributing data retention to other memories. There are the same effects as in the first embodiment, such as the possibility of becoming possible.

Further, since the repair process is performed using the cycle in which the read / write operation is not performed, the 1-port memory cell unit 1 can cope with the repair process. Since it can be realized, effects such as miniaturization of the chip and low cost can be obtained.

Embodiment 14 FIG. FIG. 26 is a block diagram showing a memory block mounted on a semiconductor integrated circuit device according to Embodiment 14 of the present invention. In the figure, 10
Reference numeral 0 denotes a memory cell unit serving as a main data storage unit, and 1
Reference numeral 01 denotes an address decoder of the memory cell unit 100. Reference numeral 102 denotes a data string holding unit that holds a frequently accessed data string or a data string whose access speed is to be increased and has a smaller capacity than the memory cell unit 100 and includes a plurality of memory cells. Reference numeral 103 denotes an address information holding unit that holds address information that specifies the location of the data string holding unit 102 where the data string is stored. A selector 104 selects one of the data read from the data string holding unit 102 and the data read from the memory cell unit 100, and outputs the selected data from the data output terminal DO.

A predefined data sequence, for example, A
LL “0” and ALL “1”, and when the memory block is used as an instruction memory, frequently used ones such as a nop (NOP) are held in the data string holding unit 102. As described above, these data strings are read from the data strings held in the small-sized data string holding unit 102 instead of the large-sized memory cell unit 100 to reduce power consumption. I have. Similarly, a data string that requires processing time, such as an operation processing instruction, is also held in the data string holding unit 102, and the data string holding unit 1 is used instead of the memory cell unit 100 having a large size.
By reading the data string from the address 02, the access time of the instruction read is shortened, and the allocated time for the arithmetic processing during the execution cycle is increased.

In order to shorten the access time of the data string held in the data string holding section 102, the address information from the address input terminal A is held before the address information is held in the memory cell section 100. Input to the unit 103. Further, in order to shorten the access time, the vicinity of the data output terminal DO, that is, the selector 10 is used.
4, a data string holding unit 102 is arranged.

When accessing the data string holding unit 102, the address information holding unit 103 stores the data string holding unit 1
02 is supplied to the data string holding unit 1 while controlling the selector 104 to supply the corresponding address.
02 is selected and output from the data output terminal DO. At that time, the address information holding unit 1
The transmission of the address information from the address decoder 03 to the address decoder 101 is stopped, and the memory cell unit 100 and the address decoder 101 are brought into a non-operating state. In addition, if it operates in a clock-synchronous manner, the control clock for the memory cell unit 100 is stopped so that the memory cell unit 100 and the address decoder 101 are made inoperative. The address information holding unit 103 also has a function for controlling these operations.

Note that the data string holding unit 102
M may be used to hold a data string corresponding to the use state, or a ROM may be used if a frequently accessed data string or a data string whose access speed is to be increased is known in advance. You may.

As described above, according to the fourteenth embodiment, data string holding section 102 holding a frequently used data string or a data string required to be accessed at high speed is replaced with memory cell section 100. Is smaller, the wiring capacity of the data propagation path is smaller, and
By arranging the data string holding unit 102 in the vicinity of the data output terminal DO, the wiring capacity can be further reduced, so that the access can be speeded up. By not accessing the memory cell unit 100, it is not necessary to charge and discharge the memory cell unit 100 having a large capacity, so that power consumption can be reduced.
When a ROM is used as 02, effects such as a reduction in chip area can be obtained.

A wide variety of different embodiments of the present invention can be constructed without departing from the spirit and scope of the present invention. The invention is not limited to the specific embodiments except as defined in the claims.

[0135]

As described above, according to the present invention, a memory cell means having a normal port for performing a normal read / write operation, a test port dedicated to a test, and a normal port to the memory cell means. Data latch means for temporarily holding write data to be written, and data written to the memory cell means from its normal port are read from the test port, and the read data is compared with the write data held in the data latch means. The comparing means to be performed, the redundancy means for holding the write data in place of the memory cell means when there is a mismatch in the match comparison by the comparing means, and the write data in the case where there is no match in the match comparison by the comparing means. Address holding means for holding information related to an address indicating the location of the memory cell means. Therefore, even if there is a defective portion in the memory cell means, its function can be replaced by the redundant means, so that the semiconductor integrated circuit device which is normally defective due to the defect can be rescued, and the yield can be improved. In addition, by providing a test port, a comparing unit and an address holding unit, a test can be performed during operation and replaced by software.
Since the process of repairing a semiconductor integrated circuit device having a defective memory cell, identifying a defective portion in a test before shipping, or performing hard wired change by laser trimming or the like is not required, This has the effect of reducing test costs.

According to the present invention, the data latch means comprises:
A plurality of data latches for temporarily storing write data to be written into the memory cell means from the normal port; And outputs the data held in the corresponding data latch. Thereafter, in the operation of writing / reading to that address, the comparison means does not perform the coincidence comparison.
Since the redundant means holding the write data corresponding to the address held in the address holding means is directly accessed, once a mismatch is detected, there is no need to perform a match comparison on the corresponding address thereafter. In addition to the shortening, there is an effect that the operation rate of the comparison unit is reduced and the power consumption can be reduced. When the address holding means and the redundancy means cannot cope with a large number of defective memory cells, the address holding means outputs an overflow signal. Therefore, the data holding is distributed to another memory or the like, and error processing is performed. Therefore, there is an effect that a malfunction of the system can be avoided.

According to the present invention, the data latch means
One write latch temporarily holds write data to be written to the memory cell means from the normal port, and the comparison means performs a match comparison during a write operation of the write data to the memory cell means. Holds the write data, and the address holding means holds the address indicating the location of the memory cell means in which the write data is written, and holds the address in the address holding means if a match is found in the subsequent match comparison by the comparing means. The written address is cleared or the address becomes overwritable, and the write data held in the redundant means is cleared or the write data becomes overwritable. There is no need to prepare a set, and the circuit scale can be reduced.
Chip cost can be reduced. In addition, it is possible to remedy a defective semiconductor integrated circuit device and improve the yield, and to reduce the test cost by performing a test during operation and replacing it with software, thereby reducing the redundant means. This has the effect of reducing chip cost by reducing the number of unused addresses and eliminating the need to replace unused addresses, and by enabling error processing based on overflow signals to avoid malfunction of the system.

According to the present invention, the data latch means
One data latch for temporarily holding write data written to the memory cell means from the normal port is provided. When the write data is written to the memory cell means, the redundancy means holds the write data and the address holding means sets the write data. The address indicating the location of the memory cell means in which the data is written is held, the comparing means performs a match comparison, and if not, the redundant means holds the write data as it is, the address holding means holds the address as it is, In the case of a match, the address held in the address holding means is cleared or the address becomes overwritable, and the write data held in the redundant means is cleared or the write data is overwritten. Since it is possible, there is no need to prepare multiple sets of data latches. , It can be made possible to reduce the circuit scale, reduce the chip cost. Also, for the address that once becomes unmatched, if it is determined that the data written next is not pseudo-failure, the redundant means can be temporarily released, and many redundant means can be used with less redundant means as a whole. Since defective portions can be relieved, this also has the effect of reducing the chip cost.

According to the present invention, the first decoder for decoding the address inputted when performing the read / write operation and activating the word line of the redundancy means, and activating the word line of the memory cell means Address decoding means provided with a second decoder for performing
The address holding means determines whether or not the same address as the address is held. If the same address is held, the first decoder activates the corresponding word line of the redundancy means, and if not, the first decoder activates the corresponding word line. Then, the second decoder activates the corresponding word line of the memory cell means, so that the defective semiconductor integrated circuit device can be rescued, the yield can be improved, and the test can be performed during operation. Implementing software replacement reduces test costs.It also reduces chip costs by reducing redundant means and eliminating the need to replace unused addresses.Error handling based on overflow signals can reduce system malfunctions. There is an effect that it is possible to avoid.

According to the present invention, when the redundancy means does not have enough space to substitute for the memory cell means, the full flag signal is asserted, so that the assertion of the full flag signal alerts the system and the data is transferred to another memory. Since it is possible to sort the data into blocks, there is an effect that the system can be prevented from being in an error state.

According to the present invention, when there is no space necessary for the redundancy means to replace the memory cell means, and when the comparison means makes a mismatch, the overflow signal is asserted. It is possible to perform error processing by the assertion of, so that malfunction of the system can be avoided, and even after the redundancy means has run out of space necessary to replace the memory cell means, Since the memory cell means can be used for the write operation until the data mismatch occurs, it is possible to reduce the frequency of error processing, and to suppress the decrease in system performance.

According to the present invention, a memory cell unit having a normal port for performing a normal read / write operation, a test port dedicated to a test, and write data written from the normal port of the memory cell unit are temporarily held. A data latch unit; and a comparison unit that reads data written to the memory cell unit from the normal port from the test port, and compares the read data with the write data held in the data latch for each bit. When a mismatch is found in the match comparison by the means, an address indicating the location of the memory cell means in which the write data is written, an address / bit information holding means for holding information on the mismatch detection bit, and a mismatch are detected. In the subsequent read operation for the address, Means for inverting the data read from the cell and outputting the inverted data, eliminating the need for redundant means, and correcting only the bits that need to be corrected without replacing the memory cell means for a plurality of bits including the defective part. Therefore, there is an effect that the chip cost can be further reduced.

According to the present invention, three or more odd-numbered memory cells having different structures, each having an individual address decoder and writing the same write data so as to have the same contents at the time of a write operation. When the same address is input to a plurality of address decoders and a plurality of address decoders perform a majority operation of an odd number of data read from a location specified by the address in a plurality of memory cell units, Means for judging the presence or absence of a defect in the means and outputting the result of the majority decision as read data, so that even if there is a defective portion in the memory cell means, the yield can be improved, and the majority can be improved. , It is not necessary to test in advance to identify defective parts,
The effect is that the test cost can be reduced. Further, since the data selected by the majority logic is output, the change processing by H / W such as laser trimming is not required, and the cost can be reduced, and the odd memory cell means having a different structure can be used. With this configuration, it is possible to detect a defect caused by the structure of the memory cell means. Further, since the address decoder is prepared for the memory cell means, not only the defect of the memory cell means but also the defect of the address decoder is obtained. There is an effect that repair can be performed even for a defect.

According to the present invention, each bit of the write data is written so as to have the same contents at the time of the write operation, the memory cell means having three or more odd-numbered memory cells, and the data written to the memory cell means. When a read operation is performed on the write data, a majority operation is performed on the odd-numbered bit data corresponding to each bit of the data read from the plurality of memory cells of the memory cell unit, and the plurality of memory cells of the memory cell unit are operated. And a majority decision means for judging the presence or absence of a defect in the memory cell and outputting the result of the majority decision as read data. Since there is no need to test in advance and specify a defective portion by means of a comparison, there is an effect that the test cost can be reduced. Also, since the data selected by the majority logic is output, H / H such as laser trimming is output.
The change processing by W becomes unnecessary, and the cost is reduced,
Since the bit lines to be subjected to the majority decision can be in the vicinity (adjacent), there are effects that the wiring can be shortened, the power consumption can be reduced, and the performance can be improved such as speeding up.

According to the present invention, a plurality of memory cell portions to which the same write data is written so as to have the same contents at the time of a write operation, and when the write data is written to the plurality of memory cell portions, And a parity bit holding unit that determines and holds the parity bit of a plurality of data read out from a plurality of memory cell units during a read operation. Check the parity bit
Since comparison means for selecting and outputting the correct data is provided, even if there is a defect in the memory cell means, it is corrected by the read data and the parity bits of the plurality of memory cell parts, so that the yield can be improved. Since the comparison is made dynamically, there is no need to specify a defective portion by performing a test in advance, and the test cost can be reduced. Further, since the correction is performed by using the plurality of memory cell units and the parity bit, a change process by H / W such as laser trimming is not required, and the cost can be reduced. Since it is sufficient to compare the read data, the memory cell portion can be reduced as compared with the case of performing majority selection, and there are effects such as reduction in chip area and reduction in chip cost.

According to the present invention, in a semiconductor integrated circuit device having at least one memory block, a self-test pattern generating means for generating a set of an address and data as a test pattern is provided. Means, data latch means for temporarily holding write data written in the memory cell means,
Comparing means for reading data written in the memory cell means and comparing read data with write data for coincidence;
When a mismatch is detected, the redundancy means for holding the data instead of the memory cell means, the address holding means for holding the address information specifying the location of the memory cell means where the write data is written,
An address input selector for selecting an address from the self-test pattern generating means and sending it to the memory cell means, and selecting and sending data from the self-test pattern generating means to the memory cell means when testing the memory cell means Since it has a data input selector, the yield is improved by replacement with redundant means, test costs are reduced by eliminating the need for identifying defective parts in advance, chip costs are reduced by reducing redundant means, and unused addresses are reduced. This eliminates the need for replacement and eliminates the need for H / W change processing such as laser trimming, thereby reducing costs and avoiding system malfunctions by distributing data retention to other memories and performing error processing. There is an effect that it becomes possible. Further, if this test operation is performed at the time of power-on or reset, or by executing a specially provided test mode, it is determined whether or not the address holding means and the redundant means prepared in advance become insufficient due to the observation of the overflow signal. Can be checked prior to normal operation, and a test before shipment can be performed. During that time, it is only necessary to set the test mode by asserting the trigger signal and observe the overflow signal / full flag signal. Since the test cost can be further reduced, and the match comparison is performed using write / read data instead of the expected value prepared in advance, there is an effect that a circuit for the self-test can be realized simply and with a small area. .

According to the present invention, each memory block includes a plurality of memory blocks including a memory cell unit, a comparing unit, a redundant unit, an address holding unit, an address input selector, and a data input selector. When testing, the self-test pattern generation means sends a set of address and data as a test pattern to a plurality of memory blocks, and each memory block has no space necessary for its redundant means to replace the memory cell means. Since the apparatus further includes an OR circuit that outputs a full flag signal and calculates the logical sum of the full flag signals from a plurality of memory blocks, a circuit for a self test such as a self test pattern generation unit is common to a plurality of memory blocks. Since it is used, the size of the additional circuit can be reduced, Reduction of bets is Hakare, since the overflow signal / full flag signal is a logic sum output of the plurality of memory blocks, there is an effect that it is possible to reduce the circuit signal line.

According to the present invention, each of the plurality of memory blocks includes a memory cell unit, a comparing unit, a redundant unit, an address holding unit, an address input selector, and a data input selector. At the time of testing, the self-test pattern generating means sends a set of address and data to a plurality of memory blocks as a test pattern, and each memory block has no space necessary for its redundant means to replace the memory cell means. If the comparison results in a mismatch, the overflow signal is output, and the device further includes an OR circuit for calculating the logical sum of the overflow signals from the plurality of memory blocks. Only for each memory block Because doing, there are effects such as it is possible to commonly use the self-test pattern generating means in different memory blocks of the structure.

According to the present invention, the memory cell means, the data latch means for temporarily holding write data to be written to the memory cell means, and the data written to the memory cell means are read out, and the read data and the data latch means are read out. A comparison unit that compares the held write data and a comparison unit.
A redundancy means for holding write data in place of the memory cell means, an address holding buffer memory for holding an input address, and a memory cell means to which the write data is written when the comparison by the comparison means results in a mismatch. And an address input selector for reading an address input from the address holding buffer memory when both reading and writing are disabled and sending it to the memory cell means. When both reading and writing are disabled, the comparing means is enabled. Therefore, the yield is improved by replacing with the redundant means, and it is not necessary to specify a defective portion in advance, thereby reducing the test cost.
By reducing the redundant means, the chip cost is reduced, the replacement of the unused address becomes unnecessary, the change processing by H / W becomes unnecessary, the cost can be reduced, and the data retention is distributed to other memories. There is an effect that a malfunction of the system can be avoided. Further, since the repair process is performed using the cycle in which the read / write operation is not performed, the 1-port memory cell unit 1 can cope with the repair process. In general, the 1-port memory can be realized with a smaller area. This has the effect of reducing the size and cost of the chip.

According to the present invention, the memory cell means, the data string holding means having a smaller capacity than the memory cell means, and holding the data string which is frequently used or the data string which requires a long processing time. When an address holding a data string is held, and a frequently used data string or a data string requiring a long processing time is accessed, the address holding the data string is stored in a data string holding unit. Data address holding means for sending frequently used data strings or data strings requiring high-speed access, since the capacity is smaller than that of the memory cell means. The wiring capacity of the data propagation path can be reduced, and the wiring capacity can be reduced by arranging the data string holding means near the data output end. Therefore, it is possible to speed up the access, and when accessing the data string holding means, the memory cell means is not accessed so that the large capacity memory cell means is not charged / discharged. Power consumption can be reduced,
Further, when a ROM is used as the data string holding means,
This has the effect of reducing the chip area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for describing an operation of a memory block in Embodiment 1 for each cycle.

FIG. 3 is a flowchart showing a procedure of a write operation of a memory block according to the first embodiment;

FIG. 4 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram for describing an operation of a memory block in a second embodiment for each cycle;

FIG. 6 is a flowchart illustrating a procedure of a write operation of a memory block according to the second embodiment;

FIG. 7 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 8 is an explanatory diagram for describing an operation of a memory block according to a third embodiment for each cycle.

FIG. 9 is a flowchart illustrating a procedure of a write operation of a memory block according to the third embodiment;

FIG. 10 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing an internal configuration of a defective memory cell address / bit information holding unit according to a fourth embodiment;

FIG. 12 is a flowchart illustrating an operation procedure of a defective memory cell address / bit information holding unit according to the fourth embodiment;

FIG. 13 is a block diagram showing a configuration of an address decoder in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 14 is a flowchart showing a read / write operation procedure according to the fifth embodiment.

FIG. 15 is a block diagram showing a main part of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 16 is a flowchart showing an operation procedure of a flag process according to the sixth embodiment.

FIG. 17 is a block diagram showing a main part of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 18 is a flowchart illustrating an operation procedure of a flag process according to the seventh embodiment.

FIG. 19 is a block diagram showing a main part of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 20 is a block diagram showing a main part of a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

FIG. 21 is a block diagram showing a main part of a semiconductor integrated circuit device according to a tenth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 11 of the present invention.

FIG. 23 is a block diagram showing a main part of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of a memory block mounted on a semiconductor integrated circuit device according to Embodiment 13 of the present invention.

FIG. 25 is an explanatory diagram for describing an operation of a memory block in a thirteenth embodiment for each cycle;

FIG. 26 is a block diagram showing a main part of a semiconductor integrated circuit device according to a fourteenth embodiment of the present invention.

[Explanation of symbols]

1 memory cell section, 2 redundant section, 3 address decoder, 4 address decoder, 5 address latch, 6
Data latch, 7 comparison circuit, 8 defective memory cell address holding section, 9 selector, 10 memory cell section, 11
Address decoder, 12 Address decoder, 13
Address latch, 14 data latch, 15 comparison circuit, 16 defective memory cell address / bit information holding unit, 17 selector, 20 defective memory cell address register, 21 bit information register, 22 correction flag, 23 address comparison circuit, 24 selector, 25
OR circuit, 26 AND circuit, 30 first decoder,
31 second decoder, 40, 41 memory block, 42
Data processing unit, 43 defective memory cell address register, 44 use flag, 45 AND circuit, 50, 5
1, 52 memory cell units, 53, 54, 55 address decoders, 56 majority selection circuits, 60 memory cell units, 61 address decoders, 62, 63, 64 memory cells, 65, 66, 67 bit lines, 68 majority selection circuits, 70, 71 memory cell section, 72 address decoder, 73 parity bit holding section, 74 comparison circuit, 80 self test pattern generation section, 81 address input selector, 82 data input selector, 83 address holding buffer memory, 90, 91, 92, 93 memory block, 94 self-test pattern generator, 95
OR circuit, 100 memory cell unit, 101 address decoder, 102 data string holding unit, 103 address information holding unit, 104 selector.

Claims (16)

[Claims] 1. A memory cell means having a normal port for performing a normal read / write operation, a test port dedicated to a test, and a data latch means for temporarily holding write data written from the normal port to the memory cell means. Comparing means for reading data written to the memory cell means from the normal port from a test port, and comparing the read data with the write data held in the data latch means; and If a match does not match,
A redundancy unit that holds the write data in place of the memory cell unit; and
A semiconductor integrated circuit device comprising: address holding means for holding information on an address indicating a location of the memory cell means in which the write data is written. 2. The data latch means includes a plurality of data latches each of which temporarily holds write data to be written to the memory cell means from a normal port, and an address of the memory cell means that has become inconsistent in the comparison by the comparison means. At the time of the first read operation, the data held in the corresponding data latch of the data latch means is output. Thereafter, in the operation of writing / reading to the address, the comparison by the comparison means is not performed. 2. The semiconductor integrated circuit device according to claim 1, wherein the redundant means holding the write data corresponding to the address held in the address holding means is directly accessed. 3. The data latch means has one data latch for temporarily holding write data written to the memory cell means from a normal port, and the comparison means matches when the write data is written to the memory cell means. A comparison is made, and if they do not match, the redundancy unit holds the write data, the address holding unit holds an address indicating the location of the memory cell unit where the write data is written, and a subsequent match by the comparison unit. If the comparison indicates a match, the address held in the address holding means is cleared or the address becomes overwritable, and the write data held in the redundant means is cleared. 2. The semiconductor integrated circuit according to claim 1, wherein the write data is written or the write data becomes overwritable. Apparatus. 4. The data latch means has one data latch for temporarily holding write data written to a memory cell means from a normal port, and the redundant means is provided when the write data is written to the memory cell means. While holding the write data, the address holding unit holds an address indicating the location of the memory cell unit in which the write data is written, and the comparison unit performs a match comparison. Data, and the address holding means holds the address as it is.
The address held in the address holding means is cleared or the address becomes overwritable, and the write data held in the redundant means is cleared or the write data is overwritten. 2. The semiconductor integrated circuit device according to claim 1, wherein said device is enabled. 5. A first decoder for decoding an address inputted when performing a read / write operation and activating a word line of a redundancy means, and a first decoder for activating a word line of a memory cell means. Address decoding means provided with the first and second decoders. The address holding means determines whether or not the same address as the address is held. 2. The semiconductor integrated circuit device according to claim 1, wherein said decoder activates a corresponding word line of said redundant means, and if not, said second decoder activates a corresponding word line of said memory cell means. 6. The semiconductor integrated circuit device according to claim 1, wherein the full flag signal is asserted when there is no space necessary for the redundancy means to replace the memory cell means. 7. The semiconductor integrated circuit device according to claim 1, wherein an overflow signal is asserted when there is no space necessary for the redundancy means to substitute for the memory cell means and when the comparison means makes a mismatch in the comparison. . 8. A memory cell means having a normal port for performing a normal read / write operation and a test port dedicated to a test, and a data latch means for temporarily holding write data written from the normal port of the memory cell means. Comparing means for reading data written to the memory cell means from the normal port from a test port, and performing bit-by-bit matching comparison between the read data and the write data held in a data latch; If there is a mismatch in the match comparison by means,
An address indicating the location of the memory cell unit in which the write data is written, an address / bit information holding unit for holding information on a mismatch detection bit thereof, and a subsequent read operation for the address where the mismatch is detected, Means for inverting and outputting data read from a memory cell for a mismatch detection bit. 9. An odd number of three or more memory cell units having different structures, each having an address decoder individually, and the same write data is written so as to have the same contents at the time of a write operation. When an operation is performed and the same address is input to the plurality of address decoders, a majority operation is performed on an odd number of data read from a location specified by the address in the plurality of memory cell units, and A semiconductor integrated circuit device comprising: majority decision means for judging the presence or absence of a defect and outputting the result of majority decision as read data. 10. A memory cell unit having three or more odd-numbered memory cells in which each bit of write data is written so as to have the same contents at the time of a write operation; When a read operation is performed on the plurality of memory cells of the memory cell unit, a majority operation is performed on odd-numbered bit data corresponding to each bit of data read from the plurality of memory cells of the memory cell unit. A semiconductor integrated circuit device comprising: majority decision means for judging the presence or absence of a cell defect and outputting the result of majority decision as read data. 11. A plurality of memory cell portions to which the same write data is written so as to have the same contents in a write operation, and a parity of the write data when the write data is written to the plurality of memory cell portions. A parity bit holding unit that obtains and holds bits; and performs a match comparison of a plurality of data read from the plurality of memory cell units during a read operation, and when the data does not match, stores the data in the parity bit holding unit. And a comparing means for checking the parity bit and selecting and outputting the correct data. 12. A semiconductor integrated circuit device comprising at least one memory block, comprising: a self-test pattern generating means for generating a set of an address and data as a test pattern; wherein the memory block comprises: a memory cell means; Data latch means for temporarily holding the write data written to the memory cell means, comparison means for reading the data written to the memory cell means and comparing read data with the write data for coincidence; Redundant means for retaining the data in place of the memory cell means;
An address holding unit for holding address information specifying a location of the memory cell unit in which the write data is written; and an address from the self-test pattern generation unit for selecting the memory when testing the memory cell unit. A semiconductor integrated circuit device comprising: an address input selector for transmitting to a cell unit; and a data input selector for selecting data from the self-test pattern generating unit and transmitting the selected data to the memory cell unit when testing the memory cell unit. . 13. Each of the plurality of memory blocks includes a memory cell unit, a comparing unit, a redundancy unit, an address holding unit, an address input selector, and a data input selector. The self-test pattern generating means sends the set of address and data as a test pattern to the plurality of memory blocks, and the memory blocks do not have enough space for their redundant means to replace the memory cell means. 13. The semiconductor integrated circuit device according to claim 12, wherein the device outputs a full flag signal, and the device further comprises an OR circuit for calculating a logical sum of the full flag signals from the plurality of memory blocks. 14. Each of the plurality of memory blocks includes a memory cell unit, a comparing unit, a redundancy unit, an address holding unit, an address input selector, and a data input selector. The self-test pattern generating means sends a set of address and data to the plurality of memory blocks as a test pattern, and each of the memory blocks has no space necessary for its redundant means to substitute for the memory cell means. 13. The semiconductor integrated circuit according to claim 12, wherein an overflow signal is output when there is a mismatch in the comparison by said comparing means, and said apparatus further comprises an OR circuit for calculating a logical sum of the overflow signals from said plurality of memory blocks. apparatus. 15. A memory cell means, a data latch means for temporarily holding write data written to the memory cell means, and reading data written to the memory cell means,
A comparing means for comparing the read data with the write data held in the data latch means; and
A redundancy unit that holds the write data in place of the memory cell unit; an address holding buffer memory that holds an input address;
Address holding means for holding information relating to an address indicating the location of the memory cell means in which the write data has been written; and when both reading and writing are disabled, reading the input address from the address holding buffer memory And an address input selector for sending to the memory cell means, and when both reading and writing are disabled, the comparing means is enabled. 16. A memory cell unit, a data column holding unit having a smaller capacity than the memory cell unit for holding a frequently used data column or a data column requiring a long processing time, and a data column of the data column holding unit. Is held, and the frequently used data string,
If a time-consuming data string is accessed,
A semiconductor integrated circuit device having address information holding means for sending an address holding the data string to the data string holding means.