JP2001268150A - Linearizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit configuration with which circuit scale is reduced and a high speed operation and high-accuracy compensation is realized in a nonlinear compensation circuit of an adaptive predistortion system having a local demodulator. SOLUTION: The fluctuation range of an input signal level is expressed with a plurality of signal level representative points, a compensation coefficient is calculated only at the representative points, and compensation coefficients at other levels are found by interpolation so that the circuit scale can be reduced and operations can be accelerated. Besides, concerning the calculation of the compensation coefficient, the calculation is recursively performed by a feedback loop using a cumulative multiplier so that high-accuracy compensation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a non-linear compensation circuit, and more particularly to a circuit (linearizer) for compensating for non-linear characteristics of a power amplifier used in a digital radio.

[0002]

2. Description of the Related Art With the rapid spread of digital radios such as mobile radios, demands for higher power and higher efficiency of power amplifiers in transmitters have been increasing, and development of both devices and circuits has been actively carried out. I have. 2. Description of the Related Art In a digital radio, linearity of input / output amplitude characteristics of a power amplifier is strictly required in order to prevent adjacent channel interference due to high-order distortion caused by nonlinear input / output amplitude characteristics of a power amplifier. However, since it is difficult to increase power and increase efficiency while maintaining good linearity, it is important to apply a nonlinear compensation technique using a linearizer. Linearizers for compensating for nonlinear characteristics of power amplifiers are roughly classified into a feedforward system, a feedback system, and a predistortion system.

The feedforward method is a method of extracting a part of the output of a power amplifier, subtracting a separately generated undistorted signal component to create a distortion component, and subtracting this from the output of the power amplifier to compensate for the distortion. , High frequency (Radio Fr
equency, hereinafter referred to as RF). The feedback method is a method of compensating for distortion by applying negative feedback to the power amplifier.
This is a method in which negative feedback is applied at various points in the ency (intermediate frequency) band and BB (Base Band). The pre-distortion method is a method in which nonlinear characteristics opposite to the distortion characteristics generated in a power amplifier are given to an input signal in advance and then input to the power amplifier, in which signal processing is performed before the power amplifier. The pre-distortion method can also handle RF, IF, and BB bands.

[0004] Among the above three types of linearizers, the feedback system automatically follows the characteristic fluctuation of the power amplifier, while the other systems require adaptive compensation control for adaptively detecting the characteristic fluctuation. For complex signal processing such as adaptive signal control, digital signal processing is easier than analog circuit technology. However, since digital signal processing is not good at handling high-frequency signals, adaptive control by digital signal processing is mainly applied to a predistortion method.

The principle of predistortion nonlinear compensation will be described with reference to FIG. FIG. 2A is a diagram illustrating an example of the input / output characteristics of the power amplifier. FIG. 2B is a block diagram showing a configuration of a conventional nonlinear compensation power amplifier (linearizer) using a predistortion method.
217 is an I component input terminal, 218 is a Q component input terminal, 20 is a complex multiplier, 21 is an inverse characteristic calculator, 22 is a quadrature modulator, 23 is a quadrature demodulator, 24 is a power amplifier (HPA), and 219 is an output Terminal.
FIG. 2 is a schematic diagram for explaining the principle.
The frequency converter for converting the signal into a signal is omitted.

In FIG. 2, the non-linear characteristic of the power amplifier is the input signal level p (p ² = x _I ² + x _Q ² , where x _I is the in-phase component amplitude of the signal and x _Q is the quadrature component amplitude). A (p) e ^j φ ^(p) = A (p) cos φ (p) + jA (p) sin φ (p) 関 数 Equation (1) is given as a function. In equation (1), A (p) represents a nonlinear component of amplitude, and φ (p) represents a nonlinear component of phase. This non-linear characteristic, the output signal of the HPA24 _{is, y = y I + jy Q} = A (p) e j φ (p) (x I + jx Q) = A (p) (x I cosφ (p) - x Q sinφ (p)) + jA (p) (x _I sinφ (p) + x _Q cosφ (p)) ‥‥‥ (2)

The amplitude part of the output signal y in equation (2) (y _I ² + y _Q ² )
FIG. 2A shows a state of change with respect to the input signal level p of ^1/2 . However, the output signal level is normalized by the small signal gain. In general, the amplitude non-linearity of a power amplifier is such that the output amplitude decreases with an increase in the input signal level p, and FIG.
Tend to be smaller than the 45 ° line. Therefore, to obtain the output amplitude y, instead of x = y as the input signal level,
x 'level signal must be input. To obtain x ′, the following equation, which is the inverse of the nonlinear characteristic (Equation (1))
(3) is obtained, and the signal level p of the input signal x is substituted into this. A ^-1 (p) e ^-j φ ^(p) = a _I + ja _Q = A ^-1 (p) cosφ (p) − jA ^-1 (p) sinφ (p) ‥‥‥ Equation (3)

In FIG. 2B, an in-phase component amplitude x _I of a signal is input through an input terminal 217, and a quadrature component amplitude y _I of the signal is input through an input terminal 218. These signal amplitudes are passed through a complex multiplier 20 and a quadrature modulator 22 to be applied to an HPA 24 and amplified.The amplified output signal y of the HPA 24 is output via an output terminal 219, while the output signal y is It is provided to a demodulator 23. The output signal y of the HPA 24 is demodulated by the quadrature demodulator 23 and input to the inverse characteristic calculator 21 as y _I + ji _Q. Similarly input signal x = x _I + jx _Q also inputted from the input terminal 217 and 218 to the inverse characteristics calculator 21. The inverse characteristic calculation unit 21 calculates these x and y
Calculate the inverse characteristic x / y from the data of The inverse characteristic x / y found
Substituting the input signal level p into
^{A -1 (p) e -j φ} (p) = search of a _I + ja _Q, giving the complex multiplier 20. In the complex multiplier 20, the input signal x is multiplied by a complex to obtain a nonlinear correction signal x ', which is provided to the HPA 24.

According to the principle of the pre-distortion described above, since the inverse characteristic of the HPA 24 is constantly monitored by the quadrature demodulator 23, the characteristic can be adaptively followed even if the HPA 24 causes a characteristic change due to a temperature change or the like. Yes, highly accurate nonlinear compensation can be realized. Takabayashi, Orihashi, Matsuoka, Morii, "Study of Linear Compensation for Transmission System Using Digital Quadrature Modulator / Demodulator", as a conventional example of an adaptive predistortion type linearizer using digital signal processing, IEICE 1998 Society Conference, B-5 There is a compensation circuit reported in -4. FIG. 3 shows a schematic configuration of this conventional example.

FIG. 3 is a block diagram showing a configuration of a conventional adaptive predistortion type nonlinear compensation circuit. 201 is an I component input terminal, 202 is a Q component input terminal, 30 is a look-up table (LUT), 31 is a power calculator (PER), 32
33 is a complex multiplier, 34 is a coefficient calculation unit, 35 is a data update unit,
10 is a quadrature modulator, 11 is a quadrature demodulator, 12 is a D / A converter, 13
Is an A / D converter, 14 and 17 are frequency mixers, 15 and 16 are local oscillators, 18 is an HPA, and 19 is a directional coupler. In the figure, two parallel signal lines are signals represented by complex signals (in-phase components are real parts and quadrature components are imaginary parts).

[0011] In FIG. 3, I-component x _I of the modulated input signal via the input terminal 201, also via the Q component x _Q input terminal 202, are respectively supplied to the complex multiplier 32. Complex multiplier
At 32, the input modulated input signal is multiplied by the nonlinear compensation coefficient given from the multiplier 33, and is given to the quadrature modulator 10 as a signal subjected to predistortion compensation. The quadrature modulator 10 performs modulation and supplies the modulated signal to the D / A converter 12. D / A converter 12
Then, the modulated signal is converted into an analog signal and supplied to the frequency mixer 14. Modulation signal of the analog is mixed with the local oscillation signal f _IF from a local oscillator 15 by the frequency mixer 14 is frequency-converted to an RF band, given HPA18. HPA18
Amplifies the signal to a predetermined level and outputs it via the output terminal 203.

The signal amplified by the HPA 18 is supplied to the directional coupler 1
A part is taken out by 9 and given to the frequency mixer 17. In the frequency mixer 17, a signal that is a part of the output of the HPA 18 is mixed with the local oscillation signal f _IF ′ of the local oscillator 16, and supplied to the A / D converter 13 as an IF band signal. The A / D converter 13 converts the IF band signal into a digital signal and supplies the digital signal to the quadrature demodulator 11. The quadrature demodulator 11 demodulates the input signal into an in-phase component signal and a quadrature component signal, and supplies the demodulated signal to the data updating unit 35 as an output data signal of the digital power amplifier.

[0013] Data updating unit 35, apart, and I components x _I and Q components x _Q of the modulated input signal via the input terminal 201 and 202 are given respectively. The data updating unit 35 updates the input data and the output data with the given modulation input signal and output data signal, respectively.
The updated data is provided to the coefficient calculator 34.

[0014] The I component x _I and Q components x _Q of the modulated input signal, it is further provided to the power calculation unit 31. Power calculator
At 31, the input signal level of the given modulated input signal is calculated, and the calculated input signal level is stored in a ROM (Rea
d Only Memory) and a coefficient calculation unit that calculates a variation nonlinear compensation coefficient.
Give to 34.

The coefficient calculating section 34 calculates a nonlinear compensation coefficient for the variation based on the input signal level given from the power calculating section 31 and the update data given from the data updating section 35. In the reference table 30, the power calculation unit
The input level value given from 31 is given to the complex multiplier 33 as a fixed non-linear compensation coefficient converted into a value compensated by a lookup table created in advance.

The complex multiplier 33 performs a complex multiplication of the fixed nonlinear compensation coefficient and the variation nonlinear compensation coefficient that have been input, obtains a nonlinear compensation coefficient for the modulated input signal, and supplies this to the complex multiplier 32. Complex multiplier 32, the I component x _I and Q components x _Q of the modulated input signal applied through an input terminal 201 and 202, complex multiplication by the nonlinear compensation coefficient given from the complex multiplier 33, Perform pre-distortion nonlinear compensation operation.

That is, in the above-described conventional example, the nonlinear characteristic of the HPA 18 is divided into a fixed component and a variable component, and the fixed component is compensated by a look-up table 30 created in advance, and the deviation between the fixed component and the current characteristic is calculated by the variation component. In this method, a predistortion compensation operation is performed adaptively. When calculating the variation nonlinear compensation coefficient in the coefficient calculator 34, the variation of the nonlinear characteristic is approximated by a second-order approximation polynomial, and the approximation coefficient is calculated as LM
It is determined by the S (least square error) algorithm. Since the non-linear characteristics of a power amplifier fluctuate due to factors such as power supply and temperature fluctuations and aging, a storage device capable of performing a table reference corresponding to the inverse characteristics of all the non-linear characteristics has a huge storage capacity. Need.
Therefore, in the above-described conventional technique, the inverse characteristic is divided into a fixed component and a variable component, and the reference table is used only for the fixed component.

[0018]

The above-mentioned prior art includes the following:
Since the non-linear characteristic of the power amplifier is a function of the input signal level, the resolution of the input signal level must be increased in order to accurately realize the inverse characteristic of the non-linear characteristic. However, there is a disadvantage that a considerable storage capacity is required for the reference table.

For the variation of the non-linear characteristic, the approximation formula is used in the above-described conventional example, and the coefficient of the approximation formula is obtained by the LMS algorithm. However, this algorithm has a drawback that the convergence is slow, so that the data update must be repeated many times (about several hundred times) and the processing speed is slow. Further, in a modulator implemented by a digital circuit, since a signal is sampled, a long acquisition time is required to acquire data over the entire range in which the input signal level fluctuates. Therefore, there is a disadvantage that the update process of the inverse characteristic data for the fluctuation is slow.

Further, when obtaining the inverse characteristic of the variation,
The non-linear characteristic of the power amplifier is obtained by approximating it with a polynomial expression.However, in order to speed up convergence, the order of the approximate polynomial expression must be reduced, and the approximation accuracy of the non-linear characteristic is reduced. there were.

In addition, the inverse characteristic of the fixed component must be measured in advance and written in a look-up table by measuring the nonlinear characteristic of the power amplifier. In order to do this, a measurement circuit different from the above-described linearizer is required, and there is a disadvantage that this look-up table must be created for each individual power amplifier.

In addition, since the radio cannot be operated during the time when the inverse characteristic of the fluctuation is obtained, there is a disadvantage that a preparatory operation is required before the normal operation of the radio.

As described above, the prior art has the following disadvantages. (1) The circuit scale is large because a large-capacity memory and an LMS algorithm are used. (2) The convergence of the inverse characteristic calculation of the variation is slow. (3) Low nonlinear compensation accuracy. (4) Initial measurement at the time of manufacturing (acquisition of fixed data) and switching of the operation mode of the radio are required.

An object of the present invention is to eliminate the above-mentioned disadvantages and to provide a linearizer having high nonlinear compensation accuracy. A second object of the present invention is to provide a linearizer which eliminates the above-mentioned disadvantages, has a small circuit scale, and can operate at high speed. A third object of the present invention is to provide a linearizer which can eliminate the above-mentioned drawbacks and can operate automatically without adjustment and without maintenance. Still another object of the present invention is to provide a linearizer which can be easily realized by a digital circuit without using division and high-precision function calculation which are not generally strong in digital signal processing.

[0025]

In order to achieve the above object, the linearizer of the present invention performs a high-precision inverse operation by directly calculating input / output data without using an approximation formula for calculating the inverse characteristic. The characteristics are determined.

In order to achieve the second object, the non-linear compensation circuit of the present invention does not calculate the inverse characteristic over all signal levels, but performs the inverse characteristic calculation only at a signal level representative point selected in advance. For the other levels, calculation is performed by interpolating the inverse characteristic at the level representative point. In addition, when acquiring data, the inverse characteristic at the level representative point is obtained by interpolating from the acquired signal level. Accordingly, it is not necessary to calculate the inverse characteristic over all signal levels, and only the data at the level representative points need to be calculated and stored, so that the circuit scale can be reduced and the operation speed can be increased.

Further, in order to achieve the third object, in the calculation of the inverse characteristic data, the non-linear compensation circuit of the present invention uses an accumulative multiplier comprising a multiplier and a delay register for the amplitude non-linear characteristic. A cumulative adder composed of a multiplier, an adder, and a delay register is used for the phase nonlinear characteristic. In the accumulator, the input / output signal level ratio is input and accumulated in the form of a product. Further, the cosine and sine values of the input / output signal phase difference are input to the phase accumulator, and the cosine and sine values of the sum of the phase differences are accumulated in the delay register. If a feedback loop is formed by the complex multiplier for inverse characteristic compensation and the nonlinear power amplifier, the data value of the delay register of the accumulator will converge to the reciprocal of the input / output signal level ratio of the HPA. The input / output signal level ratio (that is, the input value of the accumulator) converges to 1 (the input value of the accumulator adds to 0). When the nonlinear characteristic fluctuates, the input value of the accumulative multiplier becomes a value other than 1 (the input value of the accumulator is not 0), so that the loop operates to converge again to the fluctuated value. Thus, a compensation circuit capable of automatically performing a nonlinear compensation operation can be realized.

Further, in the present invention, the reciprocal square root and the reciprocal are calculated by the recurrence formula by the Newton method in order to calculate the nonlinear inverse characteristic without using the division operation. As a result, a nonlinear compensation circuit can be easily realized even in a digital signal processor without a division instruction.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of a nonlinear compensation circuit according to the present invention, basic matters relating to the present invention will be described. As described in the section of the means for solving the problem, the nonlinear characteristic of the power amplifier is a function of the input signal level p, but performing the calculation over the entire fluctuation range of P (0 to the maximum level p _max ) is as follows. The amount of arithmetic processing is too large to be realized. Therefore, the variation range of p is, for example, N equal intervals (Δ
p = p _max / N, where N is an integer value, and inverse characteristic data is calculated only for N number of level representative values p _i (p _i = iΔp, i = 0 to N). Of course, the level division is not limited to a fixed interval, but may be performed at any predetermined interval.

On the other hand, the obtained data and the data used for the predistortion can take any value in the fluctuation range of p, so that the calculation is performed by interpolation. Data interpolation Lagrange the M-th order interpolation polynomial _{f (x) = Σ j =} 0 M f j [Π k ≠ j (x - p k) / (p j - p k)] = Σ j = 0 M f j C _j (x) 行 う Performed by equation (4). Equation (4), M + 1 points (p ₀ , f ₀ ), (p ₁ , f ₁ ),
This is an Mth-order polynomial passing through ‥‥‥, (p _M , f _M ).

In order to accurately determine the value f (p) at x = p, M + 1 points p ₀ , p ₁ , ‥‥‥, p _M are converted into N + 1 data p ′ _i ( = iΔp, i = ₀ to N, M <N), p is p ₀
Select so as to be located at the center of ~ p _M so as to satisfy equation (5) or equation (6). _{p 0 = p 'i - M} / 2, ‥‥‥, p M / 2 = p' i, ‥‥‥, p M = p 'i + M / 2 ‥‥‥ equation (5) where, p' _i -Δp / 2 <p <p ' _i + Δp / 2 (M is an even number) p ₀ = p' _{i- (M-1) / 2} , ‥‥‥, p _{(M-1) / 2} = p ' _i , ‥‥‥, p _M = p ′ _{i + (M + 1) / 2} ‥‥‥ (6) where p ′ _i <p <p ′ _{i + 1} (M is an odd number) The accuracy of the interpolation is the degree of the polynomial And the smaller the step of the level representative point, the better. Of course, to be able to interpolate, f must be a function of only x and a function that is continuous with x.

Next, a method for calculating a nonlinear inverse characteristic of the power amplifier according to the present invention will be described. As described in the description of the related art, the non-linearity has its amplitude and phase expressed as a function of the input signal level p as shown in Expression (1). on the other hand,
Obtaining data that can be in-phase and quadrature components of the input signal _{(x I, x Q, y} I, y Q) a and, the form of the quadrature component and the inverse characteristic data also in-phase component for performing nonlinear compensation (a _I, a _Q ). Therefore, the conversion between the amplitude phase component and the in-phase quadrature component is performed not by the conversion by the trigonometric function table but by the calculation, thereby preventing the accuracy from being lowered.

That is, the nonlinear characteristic A (p) e ^-j φ of the power amplifier
^(p) is given as the ratio of the input signal of the power amplifier _{(x = x I + jx Q} ) and the output signal _{(y = y I + jy Q} ). Therefore,
The inverse characteristic A ^-1 (p) e ^-j φ ^(p) is given by equation (7). A ^-1 (p) e ^-j φ ^(p) = (x _I + j x _Q ) / (y _I + jy _Q ) = ((x _I y _I + x _Q y _Q ) ^-j (x _I y _Q- x _Q y _I )) / (y _I ² + y _Q ² ) ‥‥‥ (7)

By comparing equation (7) and equation (3), equation (8) is obtained as inverse characteristic data.

Further, x ² = x _I ² + x _Q ² , y ² = y _I ² + y _Q ² ,
If xy = ((x _I ² + x _Q ² ) (y _I ² + y _Q ² )) ^1/2 , then A ^-1 (p) =
Since xy / y ² is obtained, the following equation (9) is obtained. a _I = xyCOSφ (P) / y ² A _Q = −xysinφ (p) / y ² ‥‥‥ (9)

Since the variables (x _I , x _Q , y _I , y _Q ) in the equation (8) depend not only on the function of the level p but also on the phase, the data whose amplitude and phase can take various values are obtained. It cannot be interpolated and found as a function of p. Therefore, as variables used for interpolation, variables (x ² , y ² , xy cos φ, −xy sin φ
) Is used to calculate the inverse characteristic according to equation (9).

Equation (8) can be calculated by one data acquisition, but requires a high-speed DSP (digital signal processor) equipped with a division operation. Further, in an actual wireless device, the non-linear characteristics of the power amplifier fluctuate with time due to fluctuations in the power supply voltage and the ambient temperature. As nonlinear compensation in such a case, compensation control that converges to the target characteristics by multiple data acquisitions is sufficient, and DSP does not require high-speed operation, so a low-cost, low-power-consumption processor is sufficient. .

Referring to FIG. 4, an operation example of the adaptive predistortion unit for performing nonlinear compensation using a feedback loop will be described. FIG. 4 is a block diagram showing a configuration of a nonlinear compensation loop (adaptive predistortion) unit using a feedback loop. 204 is an input terminal, 40 is an inverse characteristic compensator, 41 and 45 are delay registers, 42 is a multiplier, 43 is a cumulative multiplier, 44 is an adder, 46 is a cumulative adder, 47 is a complex number operation circuit, 48 Is a power amplifier (HP
A) and 205 are output terminals.

In FIG. 4, an input signal x is supplied to an input terminal 204.
To the inverse characteristic compensator 40 and the complex number ratio operation circuit 47
It is. In the inverse characteristic compensator 40, the inverse characteristic coefficient A_n ^-1e^-jφⁿBut
Hung, A_n ^-1e^-jφⁿ・ As x, give to HPA48. HPA
At 48, the input signal A_n ^-1e^-jφ ⁿ・ X is nonlinear gain Ae^-jΦ
Multiply and output signal y = Ae^-jΦA_n ^-1e^-jφⁿ・ Output x
You.

The output signal y is output from the output terminal 205 and is also supplied to the complex ratio calculating circuit 47. Therefore, the input signal x and the output signal y are input to the complex number ratio operation circuit 48,
The complex ratio operation circuit 48 calculates the inverse ratio a _n ^-1 of the input / output signal at the time point _n.
Calculate e ^-j φ = x / y. The obtained amplitude inverse ratio a _n ^-1 is given to the accumulative multiplier 43 constituted by the delay register 41 and the multiplier 42, and the inverse characteristic coefficient stored in the delay register 41 by the multiplier 42 one time before is stored. The product is multiplied by A _n-1 ^-1 to calculate an inverse characteristic coefficient An _n ^-1 at the time point n, and the result is given to the inverse characteristic compensator 40. That is, A _n ^-1 = an _n ^-1 A _n ^{-1 -1} = Π _n (a _n ^-1 ). Also,
The input / output phase difference φ is supplied to a cumulative adder 46 composed of a delay register 45 and an adder 44, and the adder 44 stores the phase accumulated value φ _n−1 stored in the delay register 45 one time before.
To calculate the phase accumulated value φ _n at the time point _n , and also applies the same to the inverse characteristic compensator 40. That is, -φ _n = -φ-φ _n-1
= Σ _n (φ).

In the configuration of FIG. 4, the initial value A ₀ of the delay register 41 is
^-1 is 1, and the initial value φ ₀ of the delay register 45 is 0. When the nonlinear compensation loop converges, y = Ae ^j ΦA _n ^-1 e
Since the ^{-j φ n} · x = x, the amplitude A _n ^-1 converges to A ^-1, a _n
^-1 converges to 1. The phase φ _n is the phase characteristic Φ of the HPA48.
And φ converges to 0. A _n ^-1 = A ^-1 = ((x _I ² + x
_Q ² ) / (y _I ² + y _Q ² )) ^1/2 is equal to x / y obtained by the instantaneous calculation. Therefore, when this is substituted into equation (8), a _I and a
_{As Q} , the inverse characteristic of HPA48 is determined by the nonlinear compensation loop. _{a I = (x I y I} + x Q y Q) A n -1 / (xy) a Q = (x Q y I - x I y Q) A n -1 / (xy) However, xy = (( x _I ² + x _Q ² ) (y _I ² + y _Q ² )) ^1/2 ‥‥‥ Equation (10)

In the non-linear compensation loop using the cumulative multiplier 43 and the cumulative adder 46, the inverse ratio a ^-1 e ^-j φ at each time point does not have to be exactly equal to x / y. Therefore, the operations such as the reciprocal square root and the reciprocal required for calculating the inverse characteristic can be performed by recurrence calculation using the Newton method. Newton's method approximates the function f (x) with a tangent to the approximate value _xn , x
This is a solution method that asymptotically obtains the solution of f (x) by setting the intersection with the axis as a new approximate value _{xn + 1} . The slope of the tangent at x _n is y _n ′ = f ′
(X _n) is given by (derivative at x _n), and, y _n '= y _n
Since / (x _n -x _{n + 1} ) is satisfied, the recurrence formula becomes the formula (11). x _{n + 1} = x _n -y _n / y _n ′ (11)

To solve f (x) = a by Newton's method, it is transformed to solve y = f (x) -a = 0. Substituting this into equation (11) gives equation (12). _{x n + 1 = x n -} (f (x n) -a) / f '(x n) ‥‥‥ formula (12) With the recurrence formula by Newton's method, even DSP no division operation instruction, The reciprocal number can be obtained, and the square root operation can be obtained with high accuracy without using a table reference or the like.

Following the basic matter described above, the linearizer of the present invention will be further described with reference to FIG.
FIG. 11 is a block diagram showing the configuration of one embodiment of the linearizer of the present invention. 201 is an in-phase component x _I input terminal of the input signal x, 202 is a quadrature component x _Q input terminal of the input signal x, 2 is a level detector (PWR), 3 is a complex multiplier, 4 'is a second interpolator,
6 'is an inverse characteristic calculator, 7' is a second interpolator, 9 'is a data input unit, 10' is a quadrature modulator, 11 'is a local quadrature demodulator, 18'
Is a power amplifier (HPA), 19 is a directional coupler, 245 and 246 are delay registers, 247 is a cumulative multiplier, 248 is a cumulative adder, 20
3 is an output terminal. Level detector 2, complex multiplier 3, second interpolator 4 ', inverse characteristic calculator 6', second interpolator 7 ',
Data input section 9 ', quadrature modulator 10', local quadrature demodulator 1
1 ', the delay registers 245 and 246, the accumulator 247, and the accumulator 248 constitute a substantially adaptive predistortion unit.

FIG. 11 shows a configuration provided with a local quadrature demodulator 11 ′ in order to obtain the nonlinear characteristics of the HPA 18.
The ratio of the output signal y and the input signal _{x (y / x = a n} e j Δφ) is calculated and accumulated multiplied by the inverse characteristic calculation unit 6 'this (A = a _n · A
_n−1 ) and cumulative addition (φ _n = Δφ + φ _{n −1} ) to obtain a non-linear characteristic (A exp (jφ _n )). The reciprocal is complex-multiplied with the input signal x to obtain a nonlinear compensation signal x '. To simplify the configuration of the inverse characteristic calculation, the HPA input signal change range is set to N
Divide, find the inverse characteristic only at the division point, interpolate at other points,
And the inverse interpolation. With the above configuration, in the adaptive predistortion of this method, the initial values 1 and 0 are stored in the registers of the accumulative multiplier 247 and the accumulator 248.
As a result, the nonlinear characteristic is obtained asymptotically, so that a special test signal for measuring the nonlinear characteristic of HPA18 is not required.

One embodiment of the linearizer according to the present invention shown in FIG. 11 will be described in more detail with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the linearizer of the present invention. 201 is an I component input terminal, 202 is a Q component input terminal, 1 is a nonlinear compensator, 2 is a level detector (PWR), 3 is a complex multiplier, 4 is a second interpolator, and 5 is a second memory ( Inverse characteristic memory), 6 is an inverse characteristic calculation unit, 7 is a first interpolation unit, 8 is a first memory, 9 is a data input unit, 10 is a quadrature modulator, 11 is a quadrature demodulator, and 12 is D / A A converter, 13 is an A / D converter, 14 and 17 are frequency mixers, 15 and 16 are local oscillators, 18 is an HPA, 19 is a directional coupler, and 203 is an output terminal. The level detector 2, the complex multiplier 3, the second interpolator 4, the second memory 5, the inverse characteristic calculator 6, the first interpolator 7, the first memory 8, and the data input unit 9 The part constitutes the non-linear compensator 1, and all perform digital signal processing. In the figure, two signal lines drawn in parallel are complex signals having the real component of the in-phase component and the imaginary component of the quadrature component.

In FIG. 1, via an I component input terminal 201
I component, and Q component via Q component input terminal 202,
It is provided to the level detector 2 and the complex multiplier 3, respectively.
This modulated input signal _{x (= x I + jx Q} ) becomes to be given respectively to the level detector 2 and the complex multiplier 2.

In the level detector 2, the input signal level p (p ²
= x _I ² + x _Q ² ), and the complex multiplier 3 multiplies the nonlinear inverse characteristic A ^-1 (p) e ^-j φ ^(p) according to the input signal level p to perform pre-distortion compensation . The predistortion compensation signal x ′ (x ′ = A ⁻¹ (p) e ^−j φ ^(p) ×) is supplied to the quadrature modulator 10. The quadrature modulator 10 modulates the input pre-distortion compensation signal x ′ to perform a D / A conversion.
Give to 12. The D / A converter 12 converts the modulated signal into an analog value, and supplies the analog modulated signal to the frequency mixer 14.

In the frequency mixer 14, the analog modulated signal is mixed with the local oscillation signal f _IF of the local oscillator 15, frequency-converted into an RF band signal, and supplied to the HPA 18. The HPA 18 amplifies and outputs the input signal. The output of the HPA 18 is output via an output terminal 203, and a part of the output is taken out by a directional coupler 19 and supplied to a frequency mixer 17.

[0050] In a frequency mixer 17, a part of the inputted output signal, frequency conversion into an IF band signal by mixing with the local oscillator signal of local oscillator 16 f _{I F} '. The IF band signal is converted into a digital signal by the A / D converter 13, and the converted digital signal is provided to the quadrature demodulator 11.

[0051] In the quadrature demodulator 11 demodulates the input signal, and outputs an output signal _{y (y = y I + jy} Q). The in-phase component y _I and the quadrature component y _Q of the output signal y and the input signal level p
When, the phase component x _I and the quadrature component x _Q of the modulated input signal x,
The data is input to the data input unit 9.

The data input unit 9 performs the following variable conversion. x ² = x _I ² + x _Q ² , y ² = y _I ² + y _Q ² , xy cosφ = x _I y _I + x _Q y _Q , -xy sin φ = x _Q y _I -x _I y _Q , ( However ^{_{xy = ((x I 2 +}} x Q 2) (y I 2 + y Q 2)) 1/2) ‥‥‥ formula (13) output data obtained by the equation (13) (x ^2, y ² , x
y cosφ, -xy sinφ) is the first memory (data memory)
Given to 8.

In the first memory 8, these data are
The nearest input level representative value p _{i of} the first memory 8 (i = 0 to
N, is written in p ₀ = _0, p _N = the storage area of the p _max). When the entire memory area of the first memory 8 has been written, the first interpolation unit (interpolation unit 1) 7 sets the first memory 8
Is interpolated and the data value (x
^2, y ^2, xy ^cosφ, to calculate the -xy sin [phi).

Further, in the inverse characteristic calculating section 6, the nonlinear inverse characteristic A ^-1 (p _i ) e ^-j φ ^(pi) = a _I at the input level representative value p _i.
+ en Find _Q by equation (9) and write it to the second memory (inverse characteristic memory) 5. The second interpolator (interpolator 2) 4 interpolates the nonlinear inverse characteristic data at the input level representative value p _i written in the second memory 5 to obtain the input signal level p detected by the level detector 2. Is calculated. The nonlinear inverse characteristic with respect to the modulated input signal x thus obtained is input to the complex multiplier 3 to perform a pre-distortion nonlinear compensation operation.

As described above, according to the embodiment of the present invention shown in FIG. 1, since the direct calculation is performed without using an approximate expression for calculating the inverse characteristic, highly accurate nonlinear compensation can be performed. . Since the calculation is performed by interpolation at points other than the representative level points, the accuracy is slightly lowered. However, it is possible to easily increase the accuracy by increasing the number of representative level points or increasing the order of the interpolation formula. Further, by performing the inverse characteristic calculation only at the representative level point, it is possible to reduce the circuit scale and realize a circuit that can operate at high speed. Further, since the characteristics of the power amplifier are constantly monitored and followed by the local demodulator without using the reference table, no adjustment and automatic control are possible.

The details of the data input section 9 and the first memory (data memory) 8 in the embodiment of the present invention shown in FIG. 1 will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of one embodiment of the data input unit and the data memory unit of the present invention. 20
6 is an x _I component input terminal, 207 is an x _Q component input terminal, 208 is an HPA output input terminal, 50 and 51 are delay circuits, 52 is a quadrature demodulator, and 53 and
54,56 and 57,59,510,512 and 513 are multipliers, 55,58,51
1, 514 is an adder, 515 is a memory control circuit, and 516 is a memory.

In FIG. 5, the output signal y of the power amplifier (HPA) is given to the orthogonal demodulator 52 via the input terminal 208,
The in-phase component x _I and the quadrature component x _Q of the modulated input signal is applied respectively to the delay circuits 50 and 51. Quadrature demodulates the demodulator 52, and outputs the orthogonal component y _Q-phase component y _I. In-phase component
y _I is given to multipliers 59 and 512, and
Two are given at the same time for multiplication. Further orthogonal components
y _Q is given to multipliers 510 and 513, and
Two are given at the same time for multiplication.

[0058] The modulated input signal is delayed respectively by the delay circuit 50 and 51, performs alignment HPA output signal y = y _I + jy _Q and time to come back to the data input unit through the quadrature demodulator 52. The delayed in-phase component x _I is simultaneously provided to the multiplier 53 for squaring, and the delayed in-phase component x _Q is simultaneously provided to the multiplier 54 for squaring. .

The signals respectively squared by the multiplier 53 and the multiplier 54 are supplied to the adder 55, and added by the adder 55, whereby x ² (x ² = x _I ² ) of the equation (13) is obtained. + x _Q ² Is output from the adder 55. Output x ² of the adder 55 is supplied to the memory control circuit 515 and memory 516. Similarly,
The signals respectively squared by the multiplier 56 and the multiplier 57 are given to the adder 58, and added by the adder 58, whereby the equation
Y ² of ^{(13) (y 2 = y} I 2 + y Q 2 ) Is output from the adder 58. Output y ² of adder 58 is provided to memory 516.

[0060] The output signal of the delay circuit 50 x _I is the multiplier 59
And also given a multiplier 513, the output signal x _Q of the delay circuit 51 is also supplied with the multiplier 510 and multiplier 512. The output of the multiplier 59 and the output of the multiplier 510 are respectively given to the adder 511,
By being added by the adder 511, the xy cosφ of the equation (13) is obtained.
_{(Xy cosφ = x I y I} + x Q y Q) of the calculation result c adder 511
Output from The output c (c = xy cosφ) of the adder 511 is provided to the memory 516. Similarly, the output of the multiplier 513 and the output of the multiplier 512 are given to the adder 514, respectively.
The addition by the adder 514 (however, the output of the multiplier 513 is subtracted) results in -xy sinφ (-xy sinφ = x _Q
y _I - x _I y _Q) of the calculation result s are outputted from the adder 514.
The output s (s = −xy sinφ) of the adder 514 is provided to the memory 516.

Next, in the memory control circuit 515, the input x
^The input signal level p is obtained by calculating p = (x _I ² + x _Q ² ) ^1/2 = (x ² ) ^1/2 from the data of ² .

The input signal level p is from 0 to the maximum input level.
Any value between p _max can be taken. Therefore, the range of fluctuation of the input signal level p is divided into N at predetermined intervals (N is a natural number)
Then, the storage area of the memory 516 is divided into 0 to N (N + 1) as shown in FIG. 5B, for example. (P _i-1 + p
_i ) / 2 <p <( _pi + _{pi + 1)} ) / 2 data (
x ² , y ² , c, s) are stored in the i-th storage area, and a flag F indicating that data has been stored is set to 1. If the new data is a storage area in which data has already been stored, the input signal level value p of the new and old data is compared, and data closer to the level representative value p _i is left. The above operation is repeated until the flags F of all storage areas of the memory 516 are set.

According to the embodiment of FIG. 5, since it is not necessary to acquire data over the entire fluctuation range of the input signal level, the time required for data acquisition can be shortened and the storage capacity of the memory can be reduced. Further, by obtaining data close to the level representative value, it is possible to increase the accuracy of the inverse characteristic calculation. Further, input and output data to be written into the memory signal itself _{(x I, x Q, y} I, y Q) instead of (
(x ² , y ² , c = xy cos φ, s = −xy sin φ), so that the condition that the variable at the time of interpolation becomes a continuous function of the input signal level p can be satisfied.

A specific embodiment of the first interpolation section in FIG. 1 will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of one embodiment of the first interpolation unit of the present invention. 209 denotes an input terminal for the input signal level p, the x ₀ ² input terminal 210, the x ₁ ² input terminals 211, 212 x ₂ ² input terminal, 213 is an input terminal of f _0, 2
14 an input terminal of the f _1, 215 is an input terminal of f _2, 60~65,619,
620 is an adder, 66-68 is a divider, 69,610,611,615-61
8 is a multiplier, 612 to 614 are data registers, 621 to 623 are square root operation circuits, 242 is an input terminal for value -1, and 216 is an interpolation output f
This is the output terminal of (p).

For interpolation, a Lagrangian interpolation polynomial shown in equation (4) is used. FIG. 6 shows an example in which the order of the interpolation polynomial is quadratic. If the order M = 2 in the equation (4), the interpolation polynomial is the following equation (14). _{f (p) = f 0 (} p - p 1) (p - p 2) / ((p - p 1) (p - p 2)) + f 1 (p - p 0) (p - p 2) / _{((p 1 - p 0)} (p 1 - p 2)) + f 2 (p - p 0) (p - p 1) / ((p 2 - p 0) (p 2 - p 1)) ( provided that , P _i = (x ² ) _i ^1/2 ) ‥‥‥ (14)

Equation (14) is expressed as (p ₀ , f ₀ ), (p ₁ , f ₁ ),
This is a second-order polynomial that passes through three points (p ₂ , f ₂ ). f _i represents four data (x ² , y ² , xy cos φ, -xy sin φ). The input signal level p _i is (x ² )
It can be obtained by _i ^1/2 . In order to perform interpolation with high accuracy, p ₀ and p are set so that the level point p to be interpolated is close to p _1.
1, choose the p _2.

In the calculation of the interpolation coefficient of the equation (14), the following equation is used.
(15) Interpolating polynomial _{f (p) = -f 0 c} 0 - f 1 c 1 - f 2 c 2 ‥‥‥ formula (16), and the interpolation coefficient is found to be used in common to the interpolation of the four data.

The operations of the equations (15) and (16) are executed by the configuration of FIG. First, (p _i-1
+ p _i ) / 2 <p <(p _i + p _{i + 1} ) / 2 is obtained, and x is obtained from the (i−1, i, i + 1) th storage areas of the first memory.
^{The two} data are read out and supplied to the square root operation circuits 621, 621 and 623 from the input terminals 210, 211 and 212, respectively, and the signal level data p ₀ ,
Find p ₁ and p ₂ .

The input signal level p is input via the input terminal 209.
The outputs p ₀ of the square root operation circuit 621 are added to the adders 60, 61, and 62. The output p ₁ of the square root operation circuit 622 is added to the adder 61, and the output p ₂ of the square root operation circuit 623 is added. Container 6
Given to 2 respectively. , As a result, adders 60, 61, 6
2 calculates pp ₀ , pp ₁ , and pp ₂ , respectively, and provides the results to the dividers 67, 68, and 66 as dividend values.

The adders 65, 63, and 64 calculate p ₁ -p ₂ , p ₂ -p ₀ , and p ₀ -p ₁ , respectively.
Give to 7, 68, 66. Based on these input data, the dividers 67, 68, and 66 calculate d ₀ , d ₁ , and d ₂ in equation (15).
The output d _{0 of the} divider 67 is given to multipliers 610 and 611, and the output d _{1 of the} divider 68 is given to multipliers 69 and 610, and the divider 66
Output d ₂ of given to the multiplier 69 and 611.

The interpolation coefficient c ₀ is calculated by the multiplier 69, and the obtained interpolation coefficient c ₀ is given to the data register 612 and stored. Similarly, the interpolation coefficient c ₁ is calculated by the multiplier 611, the obtained interpolation coefficient c ₁ is given to the data register 613 and stored, the interpolation coefficient c ₂ is calculated by the multiplier 610, and the obtained interpolation coefficient c ₂ is The data is supplied to the data register 614 and stored.

Next, the amplitude square values x ² _i−1 , x ² _i , x ^{2 of the} input signal are stored from the (i−1, i, i + 1) th storage area of the first memory 8.
_{i + 1} is read out and set as f ₀ , f ₁ , f ₂ in equation (16), and input terminal 21
The signals are supplied to multipliers 615, 616, and 617 via 3, 214, and 215, respectively. The multiplier 615 multiplies the interpolation coefficients c ₀ to f ₀ input, given to the multiplier 618 obtains a c ₀ f _0. The multiplier 616
In multiplies the interpolation coefficients c ₁ to f ₁ input, given to the adder 619 obtains the c ₁ f _1. Further, the multiplier 617 multiplies the input f ₂ by the interpolation coefficient c ₂ , obtains c ₂ f ₂ , and gives it to the adder 620.

The multiplier 618 multiplies the value -1 given from the input terminal 242, and supplies -c ₀ f ₀ to the adder 619. Then, in the adder 619, c ₁ f ₁ given from the multiplier 616 is obtained from -c ₀ f _0.
Is subtracted and given to the adder 620 as -c ₀ f ₀ -c ₁ f ₁ . Further, the adder 620 subtracts c ₂ f ₂ given from the multiplier 617 from −c ₀ f ₀ −c ₁ f ₁ , and calculates −c ₀ f ₀ −c ₁ f ₁ −c ₂ f ₂ (= f (p)) via the output terminal 216. As described above, the signal is output as the input signal amplitude square value x ² (p) at the input signal level p. The same operation is performed using the output signal amplitude squared values y ² and x
This is performed for y cosφ and -xy sinφ.

In the first embodiment of the interpolation shown in FIG. 6, since the data interpolation is performed using the data on both sides of the input signal level point to be interpolated, the interpolation can be performed with high accuracy. In addition, since the interpolation coefficient can be used in common for the four pieces of data, the amount of calculation processing can be greatly reduced.

In the embodiment shown in FIG. 6, the interpolation coefficient is obtained by using a divider. However, a DSP (Digital Signal Processor) generally used does not often have a divider. In this case, division is performed by referring to a table or program processing. However, there is a problem that the operation accuracy is reduced and the processing speed is reduced. Therefore, an embodiment of a reciprocal operation circuit capable of calculating a reciprocal at high speed will be described with reference to FIG.

FIG. 7 is a block diagram showing the configuration of one embodiment of the reciprocal operation circuit of the present invention. FIG. 7A shows a reciprocal operation circuit, and FIG. 7B shows a division circuit. 220 is an input terminal for inputting the input value x, 221 is an input terminal for the value 2, 70, 73, and 75 are multipliers, 71 is a delay register, 72 is an adder, 74 is an inverse operation circuit, and 222 is an input value b. Output terminal for outputting the reciprocal 1 / x.

In order to calculate the reciprocal in FIG.
The recurrence formula (equation (12)) by the Newton method described above is used. To find the reciprocal x = 1 / b when the input value is b, solve f (x) = 1 / x−b = 0. by differentiating the f (x), f 'and ^{(x) = -1 / x 2} , it is substituted into Equation (12), a recurrence formula (formula (17)) is obtained. (However, the number of repetitions n is shifted by 1).

In order to execute equation (17) in a circuit, as shown in FIG.
The product is multiplied by x _n-1 (previous calculation result) stored in 1 and the multiplication result is added by the adder 72 (the value given from the input terminal 221).
Subtract from 2 and add to the output of adder 72 again by multiplier 73.
Multiply by _n-1 to get a new calculation result _xn . _xn is stored in the delay register 71 for the next calculation. By repeatedly executing the above operation, _xn converges to 1 / x (the reciprocal of the input value x). If the initial value set in the delay register is close to the result, fast convergence is achieved and sufficient accuracy can be obtained by repeating about three times.

In order to execute the division by the reciprocal operation circuit shown in FIG. 7A, the reciprocal operation circuit 7 shown in FIG.
The reciprocal of the divisor x is obtained by 4 and the dividend 18 is multiplied by the multiplier 75 by the multiplier 75, whereby the quotient y / x can be calculated. According to the embodiment shown in FIG. 7, a reciprocal can be obtained with high accuracy even in a DSP having no division instruction.

The inverse characteristic calculator shown in the embodiment of FIG.
Although it can be constructed by directly calculating (8), as shown in equation (8), a division operation is required, and a high-speed DSP is required even if the reciprocal operation circuit of FIG. 7 is used. Become.
Thus, FIG. 8 shows an embodiment of an inverse characteristic calculating unit that asymptotically calculates an inverse characteristic by using a feedback loop as shown in FIG.

FIG. 8 is a block diagram showing the configuration of an embodiment of the inverse characteristic calculator according to the present invention. 226 x ² input terminal, 227
y ² input terminals, the xy cos [phi input terminals 228, 229 -xy sin [phi
Input terminals, 80, 82, 83, 86 to 89, 811, 812, 816, 817 are multipliers, 810, 813 are adders, 81 is a reciprocal square root circuit,
84, 814, 815 are delay registers, 85 is a cumulative multiplier, 818 is a trigonometric function accumulator, 230 is a _I output terminal, 231 is a _Q output terminal,
Numeral 818 is a trigonometric function accumulator composed of circuit elements of multipliers 88, 89, 811, 812, adders 810, 813 and delay registers 814, 815.

In FIG. 8, interpolation data x ² , y ² , xy cos φ, -x at the signal level representative value p _i obtained by the first interpolation unit 7
y sinφ is input via input terminals 226 to 229, respectively. That is, x ² is provided to multipliers 80 and 82 via input terminal 226, y ² is provided to multiplier 80 via input terminal 227, and xy cos φ is provided to multiplier 86 via input terminal 228. And -xy sinφ is supplied to the multiplier 87 via the input terminal 229.

The product is multiplied by a multiplier 80 (output = x ² y ² ), and 1 / xy is obtained by a reciprocal square root operation circuit 81. 1 / xy found
Is supplied to the multiplier 82, the multiplier 86, and the multiplier 87. The multiplier 82 multiplies the x ² and 1 / xy, calculating the inverse ratio a _n ^-1 = x / y of the input signal at time n. The inverse ratio a _n ^-1 is given to an accumulator 85 composed of a delay register 84 and a multiplier 83, and the multiplier 83 reads the inverse ratio from the third memory in advance and sets the inverse one before the previous time in the delay register 84. The inverse characteristic coefficient A _n ^-1 at the time point _n is calculated by multiplying the characteristic coefficient A _n-1 ^-1 .

On the other hand, the interpolation data xy cosφ and -xy sinφ
Is multiplied by 1 / xy obtained by the reciprocal square root operation circuit 81 by multipliers 86 and 87 to obtain cos φ and −sin φ. The cosine value and sine value of the obtained input / output phase difference φ are accumulated by the trigonometric function accumulator 818. Trigonometric function accumulator 818
Is a circuit formed from the addition formula of the trigonometric function represented by the equation (18), and the cosine and sine values of the accumulated phase difference φ _n are stored in the delay registers 814 and 815. cosφ _n = cos (φ _n-1 + φ), = cosφ _n-1 cosφ _- sinφ _{n -1} sinφ, -sinφ _n = -sin (φ _n-1 + φ), = -sinφ _n-1 cosφ-cosφ _n-1 -sinφ, ‥‥‥ (18)

The cosine value output and the sine value output of the trigonometric function accumulator 818 are multiplied by A _n ^-1 obtained by the accumulating multiplier 85 and the multipliers 816 and 817.
, Respectively, to obtain inverse characteristic data a _I and a _Q , which are output from output terminals 230 and 231 respectively. The inverse characteristic data a _I and a _Q at the obtained signal level representative value p _i are stored in the i-th storage area of the second memory. The data of the delay register 84 of the accumulator 85 and the trigonometric function accumulator 818
Of the delay registers 814 and 815 of the third memory
In the second storage area. In this way, the inverse characteristic data for all the signal level representative values p _i (i = 0 to N) is calculated.

In the embodiment shown in FIG. 8, as described with reference to FIG. 4, since the cumulative multiplier is provided in the feedback control loop, the input / output signal level inverse ratio a _n ^-1 at the time point _n causes some error. Even if it is included, _An- ¹ converges to the desired value A- ¹ (the reciprocal of the input / output level ratio of the power amplifier). Referring to FIG. 9, a specific embodiment of the reciprocal square root operation circuit used in the embodiment of FIG. 8 will be described.

FIG. 9 is a block diagram showing the configuration of one embodiment of the reciprocal square root operation circuit of the present invention. 232 is an input terminal, 90, 91, 93 and 94 are multipliers, 92 is an adder, 95 is a delay register, 243 is a value 3 input terminal, 244 is a value 1/2 input terminal,
233 is an output terminal. In order to calculate the reciprocal square root, a recurrence formula (formula (12)) by the Newton method is used as in the case of the reciprocal calculation in FIG. Transform the reciprocal square root x = a- ^{1 / 2} of the input value a into x- ² = a and solve f (x) = x- ^2-2a = 0. f
Differentiating (x) gives f ′ (x) = − 2x− ³ . f (x)
And f ′ (x) are substituted into equation (12), and the following equation (19) is the recurrence equation obtained (however, the number of repetitions n is shifted by 1). x _n = x _n-1 + x _n-1 ³ (x _n-1 ^-2 -a) / 2 = x _n-1 (3-ax _n-1 ² ) / 2

As shown in equation (19), first, the input value x given via the input terminal 232 is stored in the delay register 95 by the multipliers 90 and 91, and x _n-1 (previous calculation result) and 2 Performs degree multiplication. Next, the multiplication result is input to the input terminal 243 by the adder 92.
Subtract from the number 3 given by. Then, the multiplier 93 again stores the subtraction result in the delay register 95 x
Multiply _n-1 . Further, the multiplier 94 multiplies the numerical value か ら given from the input terminal 244 by multiplication to obtain a new calculation result _xn via the output terminal 233. The new calculation result _xn is stored in the delay register 95 for the next calculation.

By repeatedly executing the above operation, _xn becomes x
Converges to ^-1/2 (reciprocal square root of input value x). If the initial value set in the delay register is close to the result, convergence is fast. In the embodiment shown in FIG. 9, since the division is not used only by the multiplication operation, the reciprocal square root can be obtained with high accuracy by a normal DSP.

Referring to FIG. 10, a specific embodiment of the second interpolation unit 4 according to the present invention will be described. FIG. 10 is a block diagram showing a configuration of one embodiment of the second interpolation unit of the present invention.
234 is an in-phase component p _I input terminal of the input signal p, and 235 is an input signal p
Quadrature component p _Q input terminals of, 236 f ₀ input terminal, 237 is f ₁ input terminal, 238 is f ₂ input terminal, 240 is numeric 1/2 input terminal, 241
Is a 1 / Δp input terminal, 100, 102, 104, 107, 108, and 1010 are adders, and 101, 102, 105, 106, and 109 are multipliers.

In the interpolation, as in the embodiment of FIG.
The Lagrangian interpolation polynomial shown in FIG. However, in the second interpolation unit 4, since the denominator of the interpolation coefficient is given by the signal level representative value p _i = iΔp (Δp = p _max / N), when the interpolation coefficient is normalized by Δp, the equation (4) The interpolation polynomial is p-p _K (K is M / 2 (M = even), or (M-1) /
2 (M = odd number)) can be transformed into the form of a power series.
It is represented by _{f (p) = Σ j =} 0 M f j [Π k ≠ j (p - p k) / (p j - p k)] = Σ l = 0 M d l (f j, p j) (p - p _K ) ^l Equation (20)

The interpolation coefficient d _l (f _j , p _j ) in equation (20) is given by 2
Specifically, for the case of the following interpolation polynomial, the equation (1
In 4), p ₁ -p ₂ = -Δp, p ₂ -P ₀ = 2Δp
, P ₀ −p ₁ = −Δp, and p−p ₁ = Δ · Δp, p−p ₀ = (Δ + 1) · Δp, p−p ₂ = (Δ
−1) · Δp, so the interpolation polynomial is given by equation (21) (however, Δ = (p−p ₁ ) / Δp). _{f (p) = f 0/} 2 (Δ 2 - Δ) - f 1 (Δ 2 - 1) + f 2/2 (Δ 2 + Δ) = (f 0/2 - f 1 + f 2/2) Δ ² + (f ₂ −f ₀ ) / 2Δ + f ₁ = d ₂ Δ ² + d ₁ Δ + d ₀ ‥‥‥ Equation (21) That is, in Equation (21), a division operation is used to calculate the interpolation coefficient. It becomes unnecessary.

An embodiment in which the operation of equation (21) is executed by a circuit will be described with reference to FIG. A signal level representative value p _i = iΔp closest to the input signal level p is obtained, and i−1,
i, the i + 1 th storage area, reads the inverse characteristic data _{a I, p 1 = p i} , f 0 = a I i-1, f 1 = a I i, f 2 = a I
^{i + 1} . The adder 100 calculates the in-phase component pp ₁ from the input signals p ₀ and p ₁ given from the input terminals 234 and 235, and further, the multiplier 101 gives 1
/ Δp to obtain Δ = (p−p ₁ ) / Δp. The obtained Δ is given to the adder 105 and the multiplier 109, respectively.

Further, the input terminals 23 are output by the multipliers 102 and 106.
The _value f ₀ given from 6 and the _value f ₂ given from the input terminal 238 are multiplied by the numerical value 1/2 given from the input terminal 240 to obtain 1/2. And this 1 / 2f ₀ data and 1/2
the data f ₂ is applied to an adder 103 and the adder 107. Further, f ₁ is given to adder 104 and adder 1010 via input terminal 237 as coefficient d ₀ .

The adder 103 performs addition, and 1 / 2f ₀ +1/2
given to the adder 104 outputs f _2, by subtracting the d ₀ in the adder 107, 1 / 2f ₂ - give _{1 / 2f 0 (= d 1} ) to output the adder 108. Further, the adder 104 subtracts f ₁ to obtain a coefficient d ₂ =
f _0/2 - give f ₁ + f _2/2, providing a system number d ₂ to the adder 105.

[0096] In multiplier 105, by multiplying the delta entered the system number d ₂ given in (d ₂ delta) adder 108, the adder 108 adds the value as a system number d ₁ (d ₁ + d ₂ Δ) is given to the multiplier 109. The multiplier 109 multiplies the value (d ₁ + d ₂ Δ) of the adder 108 by Δ (d ₁ Δ + d ₂ Δ ² ) and supplies the result to the adder 1010. The adder 1010, the d ₀ (= f ₀₎ to _{(d 1 Δ + d 2 Δ} 2) was added, interpolated output f
(Δ), that is, the inverse characteristic data a at the input signal level p
_I get. Perform also a _Q the same calculation. FIG.
In the embodiment, it is computed in the same configuration for a _I and a _Q,
Moreover, a division operation is unnecessary, and a high-speed and high-precision interpolation operation can be performed.

In the embodiment of the present invention described above, since the feedback loop is used, the operation is performed so as to automatically converge even if there are fluctuations in the characteristics of the power amplifier, contamination of noise, and errors in calculation. When the operation of the wireless device is completed, the data stored in the second and third memories is saved in the non-volatile memory, and the data saved when the operation is resumed is initialized in the second and third memories. By operating after that, there is an advantage that convergence of the feedback loop can be performed in a very short time.

FIG. 11 shows a schematic configuration of the adaptive predistortion proposed this time. FIG. 11 is a block diagram showing the configuration of one embodiment of the linearizer of the present invention.
Local quadrature demodulator 1
1 ′. A ratio (y / x = an · e ^j Δφ) of the output signal y and the input signal x is calculated, and the result is cumulatively multiplied (A _n = an · A _n−1 ) and cumulatively added (φ _n ) by the inverse characteristic calculation unit. =
Δφ + φ _n−1 ) to determine the nonlinear characteristic (A _n exp (jφ _n )).
The reciprocal is complex-multiplied with the input signal to obtain a nonlinear compensation signal x ′
Get. To simplify the configuration of the inverse characteristic calculation, HPA18 '
The input signal change range is divided into N, the inverse characteristic is obtained only at the division points, and the other points are calculated by interpolation and inverse interpolation. With the above configuration, in the adaptive predistortion of this method, the accumulative multiplier 247 and the accumulator 248
No initial test signals for measuring the nonlinear characteristics of the HPA 18 'are required since the initial values 1 and 0 are given to the registers of the HPA 18' and the nonlinear characteristics are asymptotically determined.

Computer simulation was performed by giving amplitude-phase non-linear characteristics as shown in FIG. 12 as a characteristic model of HPA. FIG. 13 shows the specifications of the modulation scheme and the adaptive pre-distortion unit. FIG. 14 shows HPA output signal spectra before and after compensation.

In the adjacent channel (f _C ± 12.5 KHz, f _C is the carrier frequency), an improvement of about 20 dB was obtained. The convergence time from the initial values (A ₀ = 1, φ ₀ = 0) was about 400 symbols (50 msec). The amount of leakage power improvement depends on the number N of level divisions, and if the number N of divisions is increased, further improvement can be expected. Further, the convergence time can be greatly reduced by using the initial value of the inverse characteristic calculation unit as the previous data.

[0101]

As described above, according to the present invention, in a nonlinear compensation circuit for compensating for the nonlinear amplitude characteristic of a power amplifier by using an adaptive predistortion method, the nonlinear compensation can be performed directly without using a lookup table or an approximate expression. Can be calculated, and highly accurate nonlinear compensation can be performed. Also, no special test signal is required. Furthermore,
Since the calculation of the inverse characteristic is performed only for a small number of signal level representative points, it is not necessary to obtain the nonlinear characteristic data over the entire range of level fluctuation. Therefore, the operation of the nonlinear compensation circuit can be performed at high speed, and the circuit scale can be reduced. Furthermore, since the reference table is not used, there is no need to measure the initial characteristics at the time of manufacture, no inspection by a special test signal is required, and the nonlinear compensation operation is automatically performed during the normal operation of the radio. Can be. Further, even if the characteristics of the power amplifier fluctuate due to temperature, power supply voltage, temporal fluctuation, etc., the characteristic is always monitored with the local demodulator, so that the nonlinear compensation characteristic does not change. Further, since the present invention does not require processes such as a division operation and a function calculation, it can be realized by a method using a generally used digital circuit or software processing using a DSP. A non-linear compensation circuit with low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a linearizer according to the present invention.

FIG. 2 is a diagram illustrating the principle of non-linear compensation of a pre-distortion method.

FIG. 3 is a block diagram showing a configuration of a conventional adaptive pre-distortion type linearizer.

FIG. 4 is a block diagram showing a configuration for explaining the operation principle of the nonlinear compensation loop of the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment of a data input unit and a data memory unit according to the present invention.

FIG. 6 is a block diagram illustrating a configuration of an embodiment of a first interpolation unit according to the present invention.

FIG. 7 is a block diagram showing a configuration of one embodiment of a reciprocal operation circuit of the present invention.

FIG. 8 is a block diagram showing a configuration of an embodiment of an inverse characteristic calculator according to the present invention.

FIG. 9 is a block diagram showing a configuration of one embodiment of a reciprocal square root operation circuit of the present invention.

FIG. 10 is a block diagram showing a configuration of an embodiment of a second interpolation unit of the present invention.

FIG. 11 is a block diagram showing a configuration of an embodiment of the linearizer of the present invention.

FIG. 12 is a diagram showing an HPA characteristic model used for computer simulation of the present invention.

FIG. 13 is a diagram showing specifications of a modulation scheme and an adaptive pre-distortion unit used in a computer simulation of the present invention.

FIG. 14 is a diagram showing a result of a computer simulation of the present invention.

[Explanation of symbols]

1: Non-linear compensator, 2: Level detector, 3: Complex multiplier, 4, 4 ': Second interpolator, 5: Second memory,
6, 6 ': inverse characteristic calculator, 7, 7': first interpolator,
8: First memory, 9, 9 ': Data input section, 10, 1
0 ': Quadrature modulator, 11: Quadrature demodulator, 11': Local quadrature demodulator, 12: D / A converter, 13: A / D converter, 14: Frequency mixer, 15, 16: Local oscillator, 17: frequency mixer, 18: HPA, 19: directional coupler, 20: complex multiplier, 21: inverse characteristic calculator, 22: quadrature modulator, 23: quadrature demodulator, 24: HPA, 30: lookup table , 31: power calculator, 32: complex multiplier, 33: complex multiplier,
34: coefficient calculator, 35: data updater, 40: inverse characteristic compensator, 41: delay register, 42: multiplier, 43: cumulative multiplier, 44: adder, 45: delay register, 46: cumulative adder , 47: Complex ratio arithmetic circuit, 48: HPA, 5
0, 51: delay circuit, 52: quadrature demodulator, 53, 54: multiplier, 55: adder, 56, 57: multiplier, 58: adder,
59: Multiplier, 60-65: Adder, 66-68: Divider,
69: Multiplier, 70: Multiplier, 71: Delay register, 7
2: adder, 73: multiplier, 74: reciprocal operation circuit, 7
5: Multiplier, 80: Multiplier, 81: Reciprocal square root operation circuit,
82, 83: multiplier, 84: delay register, 85: cumulative multiplier, 86 to 89: multiplier, 90, 91: multiplier, 92: adder, 93, 94: multiplier, 95: delay register, 10
0: adder, 101, 102: multiplier, 103, 104: adder, 105, 106: multiplier, 107, 108: adder, 10
9: Multiplier, 201, 202: input terminal, 203: output terminal,
217, 218: input terminal, 219: output terminal, 245, 24
6: delay register, 247: cumulative multiplier, 248: cumulative adder, 510: multiplier, 511: adder, 512, 513: multiplier, 514: adder, 515: memory control circuit, 516:
Memory, 610, 611: Multiplier, 612-614: Data register, 615-618: Multiplier, 619, 620: Adder, 62
1 to 623: square root operation circuit, 810: adder, 811, 81
2: Multiplier, 813: Adder, 814: Delay register, 8
15: delay register, 816, 817: multiplier, 818: trigonometric function accumulator, 1010: adder.

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[Procedure amendment]

[Submission date] April 19, 2000 (2004.1.
9)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 11

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J090 AA01 AA41 CA21 CA65 CA92 FA08 FA17 GN03 KA00 KA15 KA26 KA32 KA33 KA34 KA46 KA53 KA55 KA68 MA11 NN11 SA14 TA01 TA02 TA03 5J091 AA01 AA41 CA21 KA65 KA17 KA17 KA17 KA17 KA34 KA46 KA53 KA55 KA68 MA11 SA14 TA01 TA02 TA03 5K004 AA05 FA09 FE10

Claims (18)

[Claims] 1. An input signal for inputting the determined inverse characteristic to the power amplifier in order to compensate for the nonlinear characteristic of the power amplifier used in the digital radio, in order to compensate for the nonlinear characteristic generated in the power amplifier. In the pre-distortion type linearizer provided in the above, an adaptive pre-distortion unit that calculates a ratio between the output signal of the power amplifier and the input signal is provided, and the inverse characteristic of the nonlinearity of the power amplifier is obtained based on the calculated ratio. Features a linearizer. 2. The linearizer according to claim 1, wherein:
The change range of the input signal of the power amplifier is divided into N (N
Is a natural number), the inverse characteristic of the nonlinearity is obtained at the divided point, and the inverse characteristic of the nonlinearity is obtained at other points by performing interpolation and inverse interpolation. 3. A method for monitoring the output of a power amplifier using a local quadrature demodulator, calculating a ratio between an input signal and an output signal, obtaining a nonlinear characteristic of the power amplifier, and compensating for the nonlinear characteristic. A non-linear compensation circuit that compensates for the non-linear characteristics of the power amplifier by inputting a non-linear compensation signal having a non-linear characteristic to the input signal to the power amplifier via a quadrature modulator. The square root of the sum of squares of the in-phase component (x _I ) and the quadrature component (x _Q ) is calculated, and the input signal level p (p ² = x _I ²
+ x _Q ² ), in-phase component (x _I ) and quadrature component (x _Q ) data of the input signal x, and the output signal
a data input section for acquiring in-phase component (y _I ) and quadrature component (y _Q ) data of y, and acquired input signal data (x _I and x _Q )
And output signal data (y _I and ^{_{y Q) x 2 = x I}} 2 + x Q 2, y 2 = y I 2 + y Q 2, xy cosφ = x I y I + x Q yy Q, -xy sinφ _{= x Q y I - x I} y Q ( however, phi is the phase difference between the input signal x and the output signal y) is converted into an intermediate processing data consisting of four values, and stores the intermediate processing data A first memory, a first interpolator for calculating intermediate processing data values for a plurality of predetermined input signal levels by interpolation from intermediate processing data stored in the first memory, and a first interpolator An inverse characteristic calculator for calculating an inverse characteristic of the non-linear characteristic of the power amplifier at the plurality of predetermined input signal levels from the intermediate processing data determined by the above, and storing the inverse characteristic data determined by the inverse characteristic calculator. By interpolation from a second memory to be stored and the inverse characteristic data stored in the second memory.
A second interpolator for calculating inverse characteristic data corresponding to the input signal level detected by the level detector; and a non-linear compensation operation by multiplying the input signal by the inverse characteristic data obtained by the second interpolator. And a complex multiplier for performing the following. 4. The linearizer according to claim 3, wherein
The plurality of predetermined input signal levels are set at predetermined intervals in a level range from 0 to a maximum input level (p _max ).
Input level representative value p _i (i = 0 to N) (N is a natural number)
N, p ₀ = 0, p _N = p _max ), and the calculation by the inverse characteristic calculation unit and the data storage in the second memory are performed only by the input level representative value. 5. The level detector of a linearizer according to claim 3, wherein a calculation of a square root of a sum of squares of the input signal amplitude (p = (x _I ² + x _Q ² ) ^1/2 ) is performed. , Reciprocal square root operation of the sum of amplitude squares (a- ^{1 / 2} is calculated for a)
And a reciprocal operation thereof (obtain b ⁻¹ for b), and the reciprocal square root operation is performed by a recurrence formula z _{n + 1} = z _n (3−az _n ² ) for obtaining a reciprocal square root by the Newton method. / 2 (where, a is an input value, n is a natural number, z ₁ is the initial value, z _n the n-th calculation result) is calculated using, the reciprocal operation, a recurrence formula z for obtaining the reciprocal by Newton's method A nonlinear compensation circuit characterized in that the signal level is asymptotically calculated by using _{n + 1} = z (where b is an input value). 6. The linearizer according to claim 3, wherein the input signal data obtained by the data input unit and the data of the input signal level obtained by the level detector are delayed. The output signal data obtained at the input section is time-aligned with the input signal level p
^{_{(= (X I 2 + x}} Q 2) 1/2) value of the input level representative value
For p _i (p _i = iΔp), input signal level p and input / output signal data in the range of (p _i-1 + p _i ) / 2 <p <(p _i + p _{i + 1} ) / 2 (X _I , x _Q , y _I , y
Simultaneously writing the intermediate processing data value calculated from _Q) as the i-th data of the first memory, sets the flag F _i to indicate that the data has been written, all flags are set when Wherein the data is transferred to the first interpolation unit. 7. The linearizer according to claim 6, wherein:
If the data obtained at the data input section has already been written to the first memory, the input signal levels of the newly obtained data and the already written data are compared, and the input level representative value p A linearizer characterized by storing and storing data closer to _i (p _i = iΔp). 8. The method according to claim 3, wherein
In the linearizer, writing to the first memory is performed.
At the end, the i-th input level representative value p _iAgainst
Intermediate processing data value (x^Two, Y^Two, Xy cosφ, -xy sinφ)
With M (M is a positive integer) data (j = i−M / 2
~ I + M / 2) to obtain the N input levels
Typical value p_i(I = 0 to N)
Resets the flag of the first memory when the calculation is completed
The first interpolator is configured to
Linearizer. 9. The linearizer according to claim 8, wherein a Lagrangian M-order interpolation polynomial is used for the interpolation. (Where x = p _i , f is x _I , x _Q , y _I , y _Q , and Π _k ≠ _j
Represents the product of all terms except k = j), and p _j and f _j (j = i−M / 2) are obtained from the first memory.
~ I + M / 2) to obtain an interpolation coefficient cc _j (x), and the input level representative value p _i (i =
Intermediate processing data values for ^{0 ~ N) (x 2,} yy 2, xy
cosφ, -xy sinφ). 10. The linearizer according to claim 9, wherein said interpolation coefficient c _j (x) = Π _k ≠ _j (x-p _k ) / (p _j -p _k ) A linearizer, wherein an arithmetic operation is performed by multiplying a reciprocal obtained by a recurrence formula for obtaining a reciprocal by the Newton method. 11. The method according to claim 3, wherein
In the linearizer, the input obtained by the first interpolation unit is used.
Typical force level p_iIntermediate data value at (x ^Two, Y^TwoXy
cosφ, -xy sinφ) to the inverse characteristic calculation unit,
In the inverse characteristic calculator, the input level representative value p_i(I = 0
~ N) inverse characteristic data a_I, A_QAnd a_I = (X_Iy_I + x_Qy_Q) / (Y_I ^Two + y_Q ^Two) = Xy cosφ / y^Two a_Q = (X_Qy_I -x_Iy_Q) / (Y_I ^Two + y_Q ^Two) = -Xy sinφ / y^Two (However, xy = ((x_I ^Two + x_Q ^Two) (Y_I ^Two + y_Q ^Two))^1/2 )
And storing it in the second memory.
The linearizer to be used. 12. The inverse characteristic calculation section of the linearizer according to claim 11, wherein a division operation by a sum of squares of the output signal amplitude (y _I ² + y _Q ² ) in the calculation for obtaining the inverse characteristic data a _I and a _Q. Is calculated by multiplying the reciprocal obtained by the recurrence formula for obtaining the reciprocal by the Newton's method. 13. The inverse characteristic calculator of the linearizer according to claim 11, wherein the calculation of the amplitude compensation coefficient is performed by calculating a square value of the input signal amplitude (x ² = x _I ² + x _Q ² ) and the output signal. The reciprocal square root (1 / xy) of the product of the square value of the amplitude (y ² = y _I ² + y _Q ² ) is obtained, and the reciprocal of the product of the input and output signal amplitudes is used to calculate the input signal amplitude square value xx ² . over, input and output signal amplitude ratio ^{_{(a n -1 = x / y}} = ((x I 2 + x Q 2) / (y I 2 +
y _Q ² )) ^1/2 ), and the input / output signal amplitude ratio is cumulatively multiplied by an accumulative multiplier comprising a multiplier and a delay register to obtain an amplitude compensation coefficient (A _n ^-1 = Π _n (a _n ^-1 ), Π _n represents a power product up to n terms), and the input level representative value p _i
The cosine value cosφ and the sine value -sinφ of the input / output signal phase difference are obtained by multiplying the data values xy cosφ and -xy sinφ by the reciprocal (1 / xy) of the product of the input / output signal amplitudes. The cosine value and sine value of the input / output signal phase difference are calculated by a cumulative adder composed of a multiplier, an adder, and a delay register. (Where φ _n is the n-th cumulative phase difference), and the cumulative addition is performed to obtain a cosine value and a sine value of the phase compensation value, and the cosine value and the sine value of the phase compensation value are used as the amplitude compensation value. is multiplied by the coefficient a _n ^-1, linearizer and obtaining the inverse characteristic data a _I and a _Q by calculating ^{_{a I = a n -1 cosφ n}} a Q = -A -1 sinφ n. 14. The inverse characteristic calculation unit of the linearizer according to claim 13, wherein the calculation for obtaining the reciprocal square root of the product of the square values of the input / output signal amplitudes is performed using a recurrence formula for obtaining the reciprocal square root by the Newton method. The intermediate result of the recurrence formula and the data of the accumulator and the delay register of the accumulator are stored in a third memory, and the calculation of the recurrence formula, the accumulator and the accumulator is performed. Linearizer characterized by performing asymptotically. 15. The linearizer according to claim 13, wherein the data stored in the second and third memories is saved in a nonvolatile memory when the operation of the linearizer ends, and the data is saved when the operation is restarted. A linearizer which operates after initializing the saved data in the second and third memories. 16. The linearizer according to claim 3, wherein M input level representative values sandwiching the input signal level p detected by said level detector.
Inverse characteristic data for p _i (i = 1 to M, p ₁ <p <p _i ) is read from the second memory, and inverse characteristic data (a _I + ja _Q ) for the input signal level p is calculated by interpolation. the second constitutes an interpolation unit, the linearizer and performs nonlinear compensation operation by complex multiplying the input signal (x _I + jx _Q) the inverse characteristic data by the complex multiplier as. 17. The linearizer according to claim 16, wherein:
In the interpolation section, the Lagrange interpolation M order interpolating polynomial _{f (p) = Σ j =} 0 M f j [Π k ≠ j (p - p k) / (p j - p k)] = Σ j = 0 ^M f _j c _j (p)) (where f is a _I , a _Q ) from the second memory
p _j and f _j (j = i−M / 2 to i + M / 2) are read to determine an interpolation coefficient c _j (p), and the inverse characteristic data value (a _I , a _Q ) is calculated. 18. The linearizer according to claim 17, wherein:
In the interpolation unit, the M-th order interpolation polynomial of the Lagrange, difference between the input signal level p and the input level representative value _{p K (p - p K)} ( where, K is M / 2 when M = even number, M = when an odd number (M - 1) / 2 f deformed to form a power series _{of) (p) = Σ j =} 0 M f j [Π k ≠ j (p - p k) / (p j - p k) ^{_{] = Σ l = 0 M d}} l (f j, p j) (p - p K) l ( where, f is a _I, a _Q) used to interpolate, p from said second memory _j and f _j (J = i
-M / 2 to i + M / 2) and read out the interpolation coefficient d _l (f _j ,
p _j )) and obtain the input signal level p by the interpolation polynomial.
A linearizer for calculating inverse characteristic data values (a _I , aa _Q ) with respect to.