JP2001257139A - Semiconductor substrate and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate and its manufacturing method in which the adhesion of particle is suppressed and marking is eased. SOLUTION: In a semiconductor substrate provided with a semiconductor layer 3 which is provided on the upper side with an insulation layer 2 interposed, a mark 4 is formed in an area other than the surface area of the semiconductor layer 3. Specifically, a first substrate is prepared, and a mark is formed in the peripheral part of a second substrate, and then the first and second substrates are adhered with each other in such a manner that the marked parts are not adhered, and the unnecessary part of the first substrate is removed, thereby moving a moving layer of the first substrate to form an SOI substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor memory,
The present invention relates to a semiconductor substrate used for manufacturing a microprocessor, a system LSI, and other semiconductor integrated circuit devices and a method of manufacturing the same, and particularly to a semiconductor substrate having a mark used for identification of a semiconductor substrate and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Semiconductor substrates include a mirror wafer obtained by polishing at least one surface of a disk-shaped substrate sliced from an ingot, and an epitaxial wafer having a single crystal semiconductor layer formed on the surface of the mirror wafer by epitaxial growth.

Another technique for forming a single crystal semiconductor layer on an insulator or a substrate having an insulating layer is called a silicon-on-insulator or a semiconductor-on-insulator, and is widely known as an SOI technique. The manufactured semiconductor substrate is called an SOI substrate or SOI wafer.

[0004] Recently, the following three are typical examples of SOI substrates. (1) SIMOX (Seperatio)
n by Ion Implanted Oxyge
This is a method referred to as n) for forming an SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate. (2) Microbubbles formed in an ion-implanted layer by performing ion implantation of hydrogen into a Si single crystal substrate by a method called a smart cut method, and then bonding the substrate to another substrate and performing heat treatment. Is grown to separate the Si single crystal substrate. The SOI substrate obtained by this method is known as Unibond. For details, see JP-A-5-211.
No. 128 and its corresponding US Pat. No. 5,374,564.

[0005] In a modification of this method, hydrogen ions are implanted into a Si single crystal substrate from hydrogen plasma, then bonded to another substrate, and a high-pressure nitrogen gas is applied to a side wall, thereby ionizing the silicon at room temperature. A method for separating a Si single crystal substrate in an implanted layer is also known. (3) The SOI substrate described last is a method of transferring a porous semiconductor layer formed on a porous body to another substrate.
Since a semiconductor layer can be formed on a porous body by epitaxial growth, it is known as a method for obtaining the highest quality SOI substrate. Specifically, Japanese Patent No. 2608
351 or the corresponding specification of US Pat. No. 5,371,037, JP-A-7-302889 and the corresponding specification of US Pat. No. 5,856,229, and Japanese Patent No. 287780.
No. 0 and its corresponding EP 0867917. The methods disclosed therein are excellent in uniformity of the film thickness of the SOI layer, easy to keep the crystal defect density of the SOI layer low, good in the surface flatness of the SOI layer, and expensive in manufacturing. This is very excellent in that no special equipment is required and that the same apparatus can be used for a wide SOI film thickness range from several hundred angstroms to about 10 microns.

Incidentally, it is desirable that each wafer can be individually identified when the wafer is subjected to a semiconductor integrated circuit device manufacturing process (device process). Such identification is a very effective means for managing the process history of each wafer, and is used for failure analysis, process optimization, manufacturing management, and the like. The mirror wafer is identified by a mark drawn by processing the surface of the wafer with a laser beam.

FIG. 18 shows a cross section of the wafer after such laser marking.

[0008] The laser irradiation area on the surface of the wafer is melted by the laser light to form a concave portion, and the constituent material of the wafer melted and repelled from the concave portion rises around the concave portion and solidifies again. That is, the outer ring mountain shown in FIG. 18 is obtained.

For example, when the laser power is set to 220 mW and the surface of the silicon wafer is irradiated in the form of dots, the maximum diameter X1 of the deformed region is 0.04 mm to 0.05 mm, and the diameter X2 of the central concave portion is 0.02 mm to 0 mm. .03m
m, the depth Y1 of the concave portion is 2 μm to 3 μm, and the height Y2 of the convex portion
Is 0.5 μm to 1.0 μm.

[0010] These values vary with the laser power. In practice, a laser is output in a pulsed form to connect or arrange a number of dots to draw a mark.

The mark on the mirror wafer usually consists of characters of about 10 alphanumeric characters, and is a unique ID number assigned to each wafer. This standard is SE
It is also defined in the international standard of MI and is a standard method.

By adjusting the output of the laser, the driving frequency, the number of shots, and the like, it is possible to skip most of the molten substrate material and prevent the formation of the outer ring ridge. For example, when the laser output is increased, the molten substrate material is blown off to easily form a deep mark without an outer ring peak, and when the laser output is reduced, a shallow mark with an outer ring peak is easily formed.

[0013] Such laser marking is usually performed using Si.
Mirror wafer is assumed, and the printing position is S
It is described in EMI standards.

FIG. 19 shows a mirror wafer 2 on which marks are drawn.
1 is a top view, and FIG. 20 is a cross-sectional view near the mark.

For example, in the case of an 8-inch wafer as shown in FIG.
Is the (0, 0) point of the xy coordinates, the print area 24
X: -9.25 to +9.25 mm Y: +93.7 to +96.5 mm Height L2 is 2.8 mm, Length L1 is 18.5 m
The standard defines the mark 4 to be printed in the rectangular area 24 of m.

[0016]

When this standard is applied to an SOI wafer, in the SOI wafer, the semiconductor layer on the insulating layer (SOI layer) is located within the surface region of the semiconductor layer where the semiconductor layer is present.

FIG. 21 is a top view of an SOI wafer on which a mark is drawn, and FIG. 22 is a cross-sectional view around the mark. Further, since the laser output conditions and the like are conditions that are designed and determined so that particles do not fly out on the Si mirror wafer, when marking is performed on the SOI wafer according to the SEMI standard, the multilayer structure and SiO Due to the function of the heat storage layer ₂ , particles may be generated, and the diameter of the dot may be changed. This problem is even more serious with deep marks.

FIG. 23 schematically shows this state. For example, under the same laser irradiation conditions as in the case of FIG.
When irradiating a laser to an SOI wafer having a layer thickness of 100 to 200 nm and a buried insulating layer of 100 to 200 nm, the diameter X1 of the inner convex portion is about 0.045 mm,
The diameter X2 of the concave portion is about 0.04 mm, the interval X3 between the inner and outer convex portions is 0.02 mm to 0.03 mm, and the depth Y1 of the concave portion.
Is 2.5 μm to 3.0 μm, and the height Y2 of the inner convex portion is 1.
0 μm to 1.5 μm, the height Y3 of the outer convex portion is 0.8 μm
m to 1.5 μm, and are approximate values of the depths Y1, Y2, and Y3 of the concave portions.

When a character is marked on the surface of the SOI layer, it can be seen that the thickness of the character formed of the concave portion is large and the particles 25 are scattered around the character as shown in FIG. Even if the condition under which particles do not scatter is dependent on the layer structure of the SOI and the thickness of each layer, the condition setting is very complicated and requires a great deal of labor.
Also, with a weak laser output that can suppress scattering of particles, the depth of the concave portion that can be dug by the laser becomes shallow, which makes it difficult to read the mark.

[0020]

SUMMARY OF THE INVENTION An object of the present invention is to make it easy to read a mark, to reduce the number of attached particles,
Another object of the present invention is to provide a semiconductor substrate which can be easily marked and a method for manufacturing the same.

According to the present invention, in a semiconductor substrate having a semiconductor layer provided above a supporting substrate via an insulating layer, a mark is formed in a region other than a surface region of the semiconductor layer. .

According to the present invention, in a method of manufacturing a semiconductor substrate having a semiconductor layer provided above a supporting substrate via an insulating layer, a step of forming a mark in a region other than a surface region of the semiconductor layer is provided. It is characterized by.

According to the present invention, in a semiconductor substrate having a semiconductor layer formed above at least one layer of a different material above a supporting substrate, a mark is formed in a region other than a surface region of the semiconductor layer. It is characterized by.

According to the present invention, there is provided a method of manufacturing a semiconductor substrate having a semiconductor layer provided above at least one layer of a different material over a supporting substrate, wherein a mark is formed in a region other than a surface region of the semiconductor layer. And a step of performing

[0025]

DETAILED DESCRIPTION OF THE INVENTION First, an embodiment of a semiconductor substrate according to the present invention will be described.

(Embodiment 1) FIG. 1 shows a partial upper surface of a semiconductor substrate according to the present invention, and FIG. 2 shows a cross section taken along line AA '.

Reference numeral 1 denotes a supporting substrate such as a single crystal silicon wafer, 2 denotes a buried insulating layer such as silicon oxide, 3
Is a semiconductor layer (SOI layer) such as single crystal silicon. These constitute an SOI substrate.

Reference numeral 5 denotes a surface region of the semiconductor layer 3, in which a semiconductor device such as an integrated circuit is manufactured. Reference numeral 6 denotes a substantially flat surface in the peripheral region 13 of the semiconductor substrate, and the mark 4 is drawn in this region 6. Reference numeral 12 is a notch.

The edge of the surface region 5 of the SOI layer 3 (the inner edge of the peripheral region) is indicated by a circle having a radius R2. The outer peripheral edge of the substrate (the outer edge of the peripheral area) is indicated by a circle having a radius R1. The peripheral region 13 is outside the circle having the radius R2 and inside the circle having the radius R1.

As will be described in detail below, a general SOI wafer that can be obtained at present has a region in which a device enters a few mm from the outer peripheral edge of the wafer usually has a region where a device is not formed. Edge Exclusion (Ed
ge Exclusion).

For example, in SIMOX, the outer peripheral edge and the SOI layer in the region from the outer peripheral edge to a position several mm inward are:
Due to the uniformity of the ion implantation, the region has a film thickness, a defect, and the like that are out of specification.

In the case of a bonded SOI wafer, several mm around the periphery of the original wafer serving as a starting material.
Are not bonded, so that the peripheral portion does not have the SOI structure. Further, the contour of the edge of the SOI layer is not smooth.
Therefore, the edge of the SOI layer is artificially removed by a method such as patterning so that the edge is inside from the beginning.

In order to provide a mark on such an SOI wafer, it is important to mark an area not having an SOI structure. Therefore, when there is no SOI layer in the peripheral region such as a bonded wafer, the peripheral region 13 is marked as shown in FIGS. This method is advantageous in that the number of steps is small and the number of chips manufactured in the SOI region is not reduced as compared with the case where the SOI layer is removed.

(Embodiment 2) FIG. 3 is a partial top view of a semiconductor substrate according to the present invention, and FIG. 4 is a cross-sectional view taken along the line BB '.

The exposed region 14 where the semiconductor layer (SOI layer) 3 and the insulating layer 2 are partially cut out and removed and a part of the support substrate 1 is exposed is seen from the edge of the semiconductor layer 3 when viewed from above. It is formed inside, that is, in a region (internal region) excluding the peripheral region 13 from the support substrate 1.

The mark 4 is drawn in the exposed area 14. Although the figure shows the case where the mark 4 is an alphabet as a character, the mark 4 may be a combination of a barcode and a number, a character or a symbol.

The edge of the surface region 5 of the SOI layer 3 (the inner edge of the peripheral region) is indicated by a circle having a radius R2. The outer peripheral edge of the substrate (the outer edge of the peripheral area) is indicated by a circle having a radius R1. In the present embodiment, a mark is formed inside a circle having a radius R2.

In the method of manufacturing a semiconductor substrate according to the present embodiment, a semiconductor substrate such as an SOI wafer is prepared, a portion other than a portion where an exposed region 14 is to be formed is covered with a mask, and a semiconductor layer 3 exposed from the mask is formed. A portion where the exposed region 14 is to be formed is removed by etching or the like.

Further, the insulating layer 2 thereunder is removed by etching or the like to expose the semiconductor surface of the support substrate 1.

The exposed area 14 is marked with a laser or the like.

Thus, an SOI substrate as shown in FIGS. 3 and 4 is obtained.

(Embodiment 3) In this embodiment, marking is performed on the back surface of the support substrate.

In the present embodiment, marks are provided on the back surface of the support substrate of the SOI substrate in the same manner as in FIGS. 19 and 20, which show the appearance of marking on the surface of the mirror wafer. Since the mark is formed on the back surface of the support substrate, the effective area of the SOI layer on the front surface side of the support substrate is not reduced.

(Embodiment 4) FIGS. 5A and 5B show a structure near a peripheral region where a mark is formed on a semiconductor substrate according to the present embodiment.
As shown in FIG.

FIG. 5 is a top view near the peripheral region, and FIG. 6 is a cross-sectional view near the peripheral region.

Reference numeral 34 denotes an edge of the buried insulating layer 2, 3
Reference numeral 5 denotes the edge of the SOI layer 3. In this embodiment,
By extending the edge 34 of the insulating layer 2 outward from the edge 35 of the SOI layer 3, the insulating layer 2 is under-etched by cleaning using an etchant cleaning solution, etc.
Although this prevents the layer from chipping, this is not essential. More preferably, the corner of the SOI layer 3 and the corner of the buried insulating layer 2 may be chamfered or processed so as to have an obtuse angle.

The mark 4 is unevenly distributed in the peripheral area 13 and is drawn outside a virtual line indicated by reference numeral 33 'in FIG.

Here, the line 33 'will be described with reference to FIG.

FIG. 7 shows two steps for making a bonded SOI substrate.
FIG. 3 is a cross-sectional view of a bonded substrate obtained by bonding two substrates.
In the figure, the mark 4 is drawn outside the position indicated by the reference numeral 33. The surface on which the mark 4 is drawn is a flat and smooth surface on the upper surface of the substrate, and is not a greatly inclined surface due to beveling.
Is the side not bonded. The marking is preferably formed on such a surface, but if the mark can be read, a part of the mark may be on an inclined surface by beveling.

The edge of the bonding interface in a state where the two substrates are brought into close contact with each other is located at the position indicated by reference numeral 32, and is called a contact edge. Thereafter, when heat treatment for increasing the bonding strength of the bonded substrate, that is, bonding annealing is performed, the edge of the bonding interface extends to the position indicated by reference numeral 33. That is, the area of the bonding interface increases.

Thereafter, unnecessary portions of the substrate 30 are removed, and the substrate 30 is thinned to produce an SOI substrate.
On the surface of the support substrate 1 of the SOI substrate thus obtained, the position where the bonding edge 33 once existed is indicated by a virtual line 33 ', and the position where the contact edge 32 once existed is indicated by a virtual line 32'. I have.

Reference numeral 31 denotes an edge 3 of the completed SOI layer 3
The position which should be 5 is shown. The distance L31 from the outer peripheral edge of the support substrate 1 is preferably 3 mm or less, more preferably, a value as small as possible even less than 3 mm.

The position of the contact edge 32 is determined depending on the shape obtained by beveling the outer peripheral portions of the substrates 1 and 30 to be used. That is, the distance L32 from the outer peripheral edge of the support substrate 1 to the contact edge 32 changes depending on the shape of the outer peripheral portion by beveling. Similarly, if the bonding edge 33 moves slightly, and if there are irregularities or foreign particles near the contact edge 32 on the bonding surface of each substrate, it becomes difficult to bond there. May also move slightly inward. Then, the position where a sufficient bonding strength can be obtained moves inward, and the edge 35 of the SOI layer 3 must necessarily be retracted inward to a position where a sufficient bonding strength can be secured. In this,
The distance L31 cannot be shortened.

The mark according to the present invention can be formed at the portion from the outer peripheral edge of the support substrate to the edge of the SOI layer.
It is good to form outside 2 '. Further, as in the present embodiment, the position 3 where the bonding edge 33 was
It is also preferable to form it outside 3 '.

Further, at least one of the bonding edge 33 and the contact edge 32 is locally retreated inward only in the vicinity of the portion where the mark is to be formed, and the mark is formed there. This is preferable because there is no possibility of reducing the effective area.

The embodiments of the semiconductor substrate of the present invention have been described above. However, the present invention is not limited to these embodiments, and each constituent element is required within a range that can achieve the object of the present invention. And the equivalents thereof are also included.

As the support substrate used in the present invention, S
i, Ge, SiC, GaAs, GaAlAs, GaN,
Although a semiconductor substrate such as InP is preferably used, the material is not limited to these as long as a mark can be formed on the surface.

As the insulating layer used in the present invention, in addition to silicon oxide, at least one selected from silicon nitride, silicon oxynitride, and the like can be used. The insulating layer may be a single layer or a plurality of laminates. Its thickness can be, for example, 1 nm to 10 μm.

As the semiconductor layer used in the present invention, S
i, Ge, SiC, GaAs, GaAlAs, GaN,
At least one semiconductor selected from InP or the like is used. The semiconductor layer may be a single layer or a plurality of laminates. Its thickness is, for example, 1 nm to
It can be 10 μm.

The shape of the semiconductor substrate of the present invention is shown in FIG.
The wafer is not limited to the notch wafer as shown in FIG. 1, but may be another wafer such as a wafer with an orientation flat. When an SOI substrate is used as the semiconductor substrate of the present invention, a non-bonded substrate such as a SIMOX wafer may be used, but a bonded SOI substrate is more preferable.

The area where the mark is drawn may be near the notch or the orientation flat, at a position facing the notch or the orientation flat, or at any other position.

The marking may be made in the peripheral area as described above, and more preferably, may be made in a substantially flat area or a slightly inclined area by beveling. Alternatively, marking may be performed on an exposed area exposed by partially removing the semiconductor layer.

The marking is performed using Nd: YAG laser or C
It is preferable to use an O2 laser or the like. Alternatively, a diamond pen can be used.

The depth of the concave portion of the mark is, for example, 1 μm to several hundred μm, and this depth can be adjusted by a laser output or the like.

The mark may be at least one selected from the group consisting of numbers, letters, symbols, bar codes, and the like, and may be a mixture of these. The characters are alphabets, kana, Greek letters, and the like.

For specific applications, the SEMI standard need not be applied. The numbers, characters, and symbols serving as marks may be arranged in a straight line or may be curved along the outer peripheral edge of the wafer. When the peripheral removal area formed by removing the semiconductor layer is narrow, or when the number of digits of the mark is large,
Curving along the outer peripheral edge reduces the possibility of interference with the SOI layer.

Thereafter, the marked wafer is packed and shipped as it is. Alternatively, the package is shipped after performing at least one of cleaning and inspection.

Alternatively, the marked wafer may then be put into the device manufacturing process as it is, or may be put into the device manufacturing process after at least one of cleaning and inspection.

II. Next, an embodiment of a method for manufacturing a semiconductor substrate according to the present invention for manufacturing the above-described semiconductor substrate will be described.

According to the method for manufacturing a semiconductor substrate of the present invention, a semiconductor substrate having a semiconductor layer provided above a supporting substrate via an insulating layer is prepared, and a mark is formed in a region other than the surface region of the semiconductor layer. Process.

As the semiconductor substrate used in the present invention,
Although the above-described ones are used, more preferably, a non-bonded SOI substrate having an insulating layer formed by ion implantation of oxygen and / or nitrogen and heat treatment, or a hydrogen and / or inert gas A bonded SOI substrate or a porous body formed by a method including a step of performing ion implantation, bonding a first substrate to a second substrate serving as a support substrate, and separating at a separation layer formed by the ion implantation. It is preferable to use a bonded SOI substrate having a semiconductor layer formed by transferring the non-porous semiconductor layer formed thereon to a supporting substrate.

Further, another method of manufacturing a semiconductor substrate according to the present invention includes a step of marking a support substrate such as a handle wafer before forming an SOI structure.

(Embodiment 5) A method of manufacturing a semiconductor substrate will be described with reference to FIGS.

Anodizing treatment is performed on the surface of the first substrate 30 such as a single crystal silicon wafer to form a porous layer 37 such as porous silicon. If necessary, the inner wall of the hole of the porous silicon layer is thermally oxidized to form a protective film of silicon oxide, and then heat treatment is performed in a hydrogen atmosphere to form the porous layer 37.
The surface opening on the surface of the layer is sealed.

A non-porous semiconductor layer 38 such as single crystal silicon is formed on the porous layer 37 by epitaxial growth such as CVD. This semiconductor layer 38 becomes a transfer layer.

Further, if necessary, the first substrate 30 is thermally oxidized to form an insulating layer 39.

As described above, through steps S11 and S12 in FIG. 9, a structure as shown in FIG. 8A is obtained.

Next, in step S21, a second substrate such as a single-crystal silicon wafer is prepared, and in step S22, marking is performed on the peripheral portion of the surface. Second if necessary
The surface of the substrate may be thermally oxidized to form an insulating film. Alternatively, an arbitrary portion on the back surface of the second substrate may be marked.

The method of manufacturing a single crystal silicon wafer generally includes a step of slicing a single crystal silicon ingot, a step of lapping a sliced wafer, a step of etching a surface of a wrapped wafer, and a step of polishing the etched wafer. In the case of deep marking, marking is performed before or after the lapping step, and in the case of shallow marking, it is performed after the polishing step.

In step S13, the substrates are bonded as shown in FIG. Furthermore, if necessary, heat treatment is performed in an oxidizing atmosphere or the like to increase the bonding strength. When the marking is applied to the front side, as described above, step S13
It is preferable to form it outside the contact edge or outside the bonding edge.

In step S14, unnecessary portions of the first substrate are removed. More specifically, as shown in FIG. 8C, the non-porous portion 36 on the back side of the first substrate is separated from the bonded substrate by at least one method selected from grinding, polishing, etching, separation, and the like. remove.

Further, the porous layer 37 remaining on the front surface (former back surface) of the semiconductor layer 38 bonded to the second substrate is removed by polishing, etching, hydrogen annealing, or made nonporous. Or Thus, the transfer of the semiconductor layer 38 is completed.

In step S15, the periphery of the SOI substrate is formed. Specifically, as shown in FIG. 8E, a sealing material, an etching mask such as a photoresist is applied to the exposed surface of the semiconductor layer 38, and the edge of the semiconductor layer 38 to be the SOI layer is etched as shown in FIGS. The peripheral portion of the semiconductor layer 38 is removed by etching so as to be at the position 31 described above. Further, the peripheral portion of the insulating layer 39 is also removed by etching to be formed. Instead of etching at this time, it may be formed by polishing.

Thus, the SO shown in FIG.
An I substrate is obtained.

The marks on this SOI substrate are shown in FIGS.
It is drawn at the position shown in FIG.

(Embodiment 6) A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

The difference from Embodiment 5 described above is that the step of forming the mark is in the middle of the step of removing the unnecessary portion of the first substrate.

As in the embodiment, the first through the steps S11 and S12
Is bonded to a second substrate not to be marked. (Step S13) Then, in step S14, a part of the unnecessary portion of the first substrate is removed. Specifically, as shown in FIG. 8C, the non-porous portion 36 on the back surface side of the first substrate is ground.
It is removed from the bonded substrate by at least one method selected from polishing, etching, separation and the like.

Thereafter, in step S15, the marking is
To the peripheral portion of the front side of the substrate. At this time, even if foreign matter scattered by marking adheres to the surface side of the second substrate,
Since the porous layer 37 on the surface side is removed in the next step, the surface region of the semiconductor layer to be the SOI layer is less likely to be contaminated by the foreign matter. Alternatively, marking may be provided on the back surface of the second substrate.

Further, in step S16, the porous layer 37 remaining on the front surface (former back surface) of the semiconductor layer 38 bonded to the second substrate is removed by polishing, etching, and hydrogen annealing. Thus, the transfer of the semiconductor layer 38 is completed.

Thereafter, in step S17, the periphery of the SOI substrate is formed.

In this way, the SO shown in FIG.
An I substrate is obtained. The marks on this SOI substrate are shown in FIGS.
It is drawn at the positions as shown in FIGS.

(Embodiment 7) A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

The difference from Embodiment 5 described above is that the step of forming the mark is performed after the step of removing the unnecessary portion of the first substrate and before the step of forming the peripheral portion.

As in the embodiment, the first through the steps S11 and S12
Is bonded to a second substrate not to be marked. (Step S13) Then, in a step S14, an unnecessary portion of the first substrate is removed. More specifically, as shown in FIG. 8C, the non-porous portion 36 on the back side of the first substrate is separated from the bonded substrate by at least one method selected from grinding, polishing, etching, separation, and the like. remove. Further, FIG.
As shown in FIG. 7, the porous layer 3 remaining on the surface (former back surface) of the semiconductor layer 38 bonded on the second substrate
7 is removed by polishing, etching, hydrogen annealing, or made nonporous. Thus, the semiconductor layer 38
Relocation is completed.

When the non-porous portion is separated, a crack is formed in the interface of the porous layer on the semiconductor layer 38 side.
The porous layer may not remain on the top.

Then, FIG. 8 is formed on the surface region of the semiconductor layer 38.
In the state where the mask MK is applied as shown in FIG.
In S15, marking is performed on the peripheral portion on the front surface side of the second substrate. At this time, even if foreign matter scattered by the marking adheres to the surface side of the second substrate, the mask MK on the surface side is removed in the next step, so the surface area of the semiconductor layer to be the SOI layer is Is less likely to be contaminated. Or the second
May be marked on the back surface of the substrate.

Further, in step S16, the peripheral portion of the SOI substrate is formed using the mask MK.

In this way, the SO as shown in FIG.
An I substrate is obtained. The marks on this SOI substrate are shown in FIGS.
It is drawn at the positions as shown in FIGS.

Embodiment 8 A method for manufacturing a semiconductor substrate will be described with reference to FIG.

The difference from the above-described seventh embodiment is that the step of forming a mark performs the same marking as that of the seventh embodiment without peeling off the mask MK used for the molding after forming the peripheral portion. is there.

In this embodiment as well, in this way, FIG.
An SOI substrate as shown in FIG.

The marks on this SOI substrate are shown in FIGS.
It is drawn at the position shown in FIG.

(Embodiment 9) A method of manufacturing a bonded semiconductor substrate using an ion-implanted layer as a separation layer will be described with reference to FIG.

The surface of the first substrate 30 such as a single crystal silicon wafer is thermally oxidized to form an insulating layer 39 such as silicon oxide. Hydrogen ion or helium ion,
Ions of an inert gas such as neon ions are implanted at a predetermined depth, and the ion implantation layer 40 in which the concentration of the ion species implanted near the depth is locally increased is formed. The portion of the semiconductor layer 38 above the ion implantation layer 40 becomes a transfer layer. The structure of the first substrate 30 thus obtained is shown in FIG.

On the other hand, the second such as a single crystal silicon wafer
Is prepared and marking is performed on the peripheral portion on the front surface side. Alternatively, marking may be performed on the back side of the second substrate.

The first substrate and the second substrate are connected to the semiconductor layer 3
Glue so that 8 is inside. Thus, a structure as shown in FIG. 13B is obtained.

Next, when heat treatment is performed at a temperature of 400 ° C. to 600 ° C. or higher, the bonding strength is increased, and a crack is generated in the ion-implanted layer 40, and the first substrate portion 36 is removed from the bonded substrate. After separation, the semiconductor layer 38 is transferred to the second substrate as shown in FIG.

The exposed separation surface of the semiconductor layer 38 is polished. At this time, the layer 3 is formed so as to have the structure shown in FIG.
The peripheral portions 8 and 39 may be removed at the same time. Alternatively, hydrogen annealing may be performed instead of polishing, or hydrogen annealing may be performed after polishing.

Then, the peripheral portion of the SOI substrate is formed. More specifically, as shown in FIG.
An etching mask MK such as a sealing material or a photoresist is applied on the exposed surface of the semiconductor layer 3 so that the edge of the semiconductor layer 38 to be the SOI layer is at the position 31 described with reference to FIGS.
8 is removed by etching. Further, the peripheral portion of the insulating layer 39 is also removed by etching to be formed. Instead of etching at this time, it may be formed by polishing.

Thus, as shown in FIG.
An SOI substrate is obtained. The mark of this SOI substrate is shown in FIG.
It is drawn at the positions as shown in 2, 5, and 6.

The process of FIG. 13C may be shifted to the process of FIG. 13E without going through the process of FIG.

(Embodiment 10) This embodiment is different from Embodiment 9 described above in the timing at which marking is performed. Other than that, the embodiment is the same as the ninth embodiment. In a state covered with the mask MK as shown in FIG. Is marked on.

Thus, as shown in FIG.
An SOI substrate is obtained. The mark of this SOI substrate is shown in FIG.
It is drawn at the positions as shown in 2, 5, and 6.

Alternatively, marking may be provided on the back surface of the support substrate.

(Embodiment 11) This embodiment is different from Embodiment 9 described above in the timing at which marking is performed. Other than that is the same as Example 9, and FIG.
After the peripheral portion of the semiconductor layer 38 is removed in a state of being covered with the mask MK as shown in (1), marking is performed on the peripheral region on the front surface side of the support substrate 1 before removing the mask MK.

Thus, as shown in FIG.
An SOI substrate is obtained. The mark of this SOI substrate is shown in FIG.
It is drawn at the positions as shown in 2, 5, and 6. Alternatively, the back surface of the support substrate may be marked.

(Embodiment 12) A method of manufacturing a semiconductor substrate by a non-bonding method will be described with reference to FIGS.

In step S11 of FIG. 15, a semiconductor substrate 1 such as a single crystal silicon wafer is prepared as shown in FIG.

Then, in step S12 in FIG. 15, marking is performed on the peripheral region on the front side of the semiconductor substrate. Alternatively, marking can be performed on the back surface side of the semiconductor substrate.

As shown in FIG. 14B, the surface of the semiconductor substrate 1 is thermally oxidized to form an insulating layer 41 such as silicon oxide.

In step S13 of FIG. 15, an insulator-forming ion species such as oxygen ion is implanted at a predetermined depth.
An ion implantation layer in which the concentration of the ion species implanted near the depth is locally increased is formed. Here, heat treatment is performed to form the buried insulating layer 2 made of the implanted compound of oxygen and silicon. The portion of the semiconductor layer 3 above the insulating layer 2 becomes the SOI layer. The structure of the SOI substrate thus obtained is shown in FIG.

Then, in step S14 of FIG. 15, the insulating layer 4 which is unnecessary and is at least on the surface side of the SOI layer
If 1 is peeled off, the SOI substrate will be marked.
When the marking is performed on the front side, the ion implantation and the heat treatment after the marking result in an SOI structure in which the mark portion also has irregularities, and the mark can be recognized from the front side.

In this case, the step shown in FIG. 14D is unnecessary.

As a modification, ion implantation is performed to avoid the marked portion, so that the SO
Marks that do not have an I structure can also be formed.

(Embodiment 13) A method of manufacturing a semiconductor substrate will be described with reference to FIGS. The present embodiment is different from the above-described embodiment in the timing at which marking is performed, and the other points are the same as those in the twelfth embodiment.

In step S11 of FIG. 16, a semiconductor substrate 1 such as a single crystal silicon wafer is prepared as shown in FIG.

As shown in FIG. 14B, the surface of the semiconductor substrate 1 is thermally oxidized to form an insulating layer 41 such as silicon oxide.

Then, in step S12 of FIG. 16, an insulator-forming ion species such as oxygen ion is implanted at a predetermined depth, and the concentration of the ion species implanted near the depth is locally increased. An ion implantation layer is formed. Here, heat treatment is performed to form the buried insulating layer 2 made of the implanted compound of oxygen and silicon. The portion of the semiconductor layer 3 above the insulating layer 2 becomes the SOI layer. S thus obtained
The structure of the OI substrate is shown in FIG.

Then, in step 13 of FIG.
As shown in FIG. 4D, a mask MK is applied, the insulating layer 41 is removed if necessary, and marking is performed. At this time, the concave portion of the mark is made to reach below the insulating layer 2 through the semiconductor layer 3.

In step S14 of FIG. 16, as shown in FIG. 14E, the mask MK and the unnecessary insulating layer 41 are removed to obtain an SOI substrate.

In this case, even if particles are scattered by the laser mark, the surface of the SOI layer is protected by the mask, so that particle contamination can be prevented.

(Embodiment 14) A method for manufacturing a semiconductor substrate will be described with reference to FIGS. The present embodiment is different from the above-described embodiment in the timing at which marking is performed, and the other points are the same as in the thirteenth embodiment.

Steps S11 and S12 in FIG. 17 are the same as in the thirteenth embodiment.

In step 13 of FIG. 17, the unnecessary insulating layer 41 is removed from the SOI substrate thus obtained, as shown in FIG. 14E, to obtain an SOI substrate.

In step S14 of FIG. 17, the surface region of the semiconductor layer is covered with a mask, and marking is performed on the peripheral region on the front side of the SOI substrate. At this time, the concave portion of the mark is made to reach below the insulating layer 2 through the semiconductor layer 3.

In this case, even if particles are scattered by the laser mark, the surface of the SOI layer is protected by the mask, so that particle contamination can be prevented.

(Embodiment 15) Referring to FIG. 8 again, a method of manufacturing a bonded semiconductor substrate will be described.

A P-type or N-type first single-crystal Si substrate having a specific resistance of 0.01 Ω · cm is prepared as a first substrate.
Anodization is performed in a HF-containing solution to form a porous layer 37 serving as a separation layer.

A porous layer 3 made of a single porous silicon
Anodizing conditions for forming 7 are, for example, as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 11 (min) Thickness of porous layer: 12 (μm) The thickness is not limited to this, and can be changed from several hundred μm to about 0.1 μm by adjusting the formation time.

Alternatively, in the case of forming a porous layer composed of a plurality of porous silicon layers, a second stage anodization may be performed following the first stage anodization as described below. First stage Current density: 7 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 5 (min) Thickness of first porous Si layer: 5.5 ( μm) Second stage Current density: 30 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 10 (sec) Thickness of second porous Si layer: 0.1 μm 2 (μm) The surface porous Si layer previously anodized at low current was used to form a high quality epitaxial Si layer, and the lower porous Si layer anodized later at high current was used for separation. Separation of functions used as a layer to facilitate the separation is performed. Therefore, the thickness of the porous Si layer is not limited to this, but is several hundred μm.
m to about 0.1 μm.

There is no problem if the third and subsequent porous layers are formed after the formation of the second porous Si layer.

The substrate is placed in an oxygen atmosphere at 300 ° C.
Oxidize at 600 ° C. Due to this oxidation, the inner wall of the porous silicon hole is covered with a protective film made of a thermal oxide film. The surface of the porous layer 37 is treated with hydrofluoric acid to remove only the oxide film on the surface of the porous layer 37 while leaving the oxide film on the inner wall of the hole.
An epitaxial growth layer 38 is formed thereon by a CVD method. The conditions of the CVD at this time are as follows, for example.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr) Temperature: 950 ° C. Growth rate: 0.3 μm / min Prior to the epitaxial growth, a heat treatment (pre-bake is performed on the porous layer 37 in an H ₂ atmosphere in an epitaxial apparatus. This is necessary to improve the crystal quality of the epitaxial growth layer 38. In practice, this treatment allows the epitaxial growth layer 38 crystal defects are 10 ⁴ cm
^-2 or less. The epitaxial growth layer 38 obtained in this manner becomes a transfer layer.

Further, as an insulating layer 39, a 20 nm to 2 μm S
An iO ₂ layer is formed. Thus, the structure shown in FIG. 8A is obtained.

The second S prepared separately from the surface of the insulating layer 39
After overlapping and contacting the surface of the i-substrate 1, 110
A heat treatment is performed at a temperature of 0 ° C. for 2 hours to perform bonding. Thus, the structure shown in FIG. 8B is obtained.

The porous layer 37 is removed from the multilayer structure thus obtained to obtain an SOI substrate in which the epitaxial growth layer 38 has been transferred to the second substrate 1. For that, the first
After the portion 36 of the Si substrate is removed by grinding, polishing, etching or the like to expose the porous layer 37, the porous layer 37 is removed by etching. Alternatively, when the multilayer structure is separated at the porous layer 37 and the porous body remains on the separation surface of the epitaxial growth layer 38 transferred to the second substrate 1, it is removed by etching or hydrogen annealing. I do.

As a separation method, a method of inserting a wedge between substrates A method of pulling wafers together A method of applying a shear force A method of using a fluid wedge effect by a water jet, a gas jet, a static pressure fluid, or the like A method of applying ultrasonic waves There is a method based on thermal stress for heating and cooling.

Thus, the structure shown in FIG. 8C is obtained.

Thereafter, the porous Si layer 37 remaining on the second substrate 1 is selectively etched with a mixed solution of hydrofluoric acid, hydrogen peroxide and water. The semiconductor layer 38 made of non-porous single-crystal Si remains without being etched.
As a stop material, the porous Si is selectively etched and completely removed. Thus, the structure shown in FIG. 8D is obtained.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the selectivity with respect to the etching rate of the porous layer reaches more than the tenth power, and the etching amount (number) About 10 angstroms)
Is a practically negligible decrease in film thickness.

That is, a semiconductor layer 38 of single-crystal Si having a thickness of 0.2 μm was formed on the insulating layer 39. Single-crystal Si by selective etching of porous Si
There was no change in the layers. When the thickness of the formed semiconductor layer 38 is measured at 100 points over the entire surface, the uniformity of the thickness is about 201 nm ± 4 nm.

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects are introduced into the i-layer, and it can be confirmed that good crystallinity is maintained.

When heat treatment is further performed in hydrogen at 1100 ° C., the surface becomes smooth.

The oxide film is not formed on the surface of the epitaxial layer.
The same result can be obtained by forming it on the surface of the second substrate or both.

As shown in FIG. 8E, a mask MK is applied to cover the surface region of the semiconductor layer 38, and thereafter, in order to adjust the shape of the peripheral portion, a width of 1 mm to 3 mm from the outer peripheral edge is set. The semiconductor layer 38 and the insulating layer 39 in the peripheral region are removed by patterning. This peripheral patterning may not be necessary.

A predetermined number of alphanumeric characters are printed by a laser marking device near the notch or orientation flat in the peripheral area. As described above, it may be a symbol or a barcode.

The characters do not need to conform to the SEMI standard. The size of the characters can be adjusted in steps of about 0.8 mm in the case of a general laser mark device, so that the characters may be small or easy to read. Can be large.

The heat treatment (hydrogen annealing) in a hydrogen atmosphere for surface smoothing may be performed after the laser mark is formed.

Thereafter, the mask MK is peeled off, the SOI substrate is cleaned and inspected, and the package is shipped.

Further, the porous Si remaining on the substrate portion 36 side of the first substrate is also selectively etched while being stirred with a mixed solution of hydrofluoric acid, hydrogen peroxide and water. After that, surface treatment such as hydrogen annealing or surface polishing is performed, and the substrate can be used again as the first substrate 30 or the second substrate 1.

(Embodiment 16) A method of manufacturing a bonded semiconductor substrate using an ion-implanted layer as a separation layer will be described with reference to FIG. 13 again.

On a first substrate 30 such as a single crystal Si wafer, an insulating layer 39 made of SiO ₂ having a thickness of 200 nm is formed by thermal oxidation.

5 × 10 ¹⁶ cm ⁻² positive ions of hydrogen are implanted at 50 keV through the insulating layer 39 on the surface. Instead of hydrogen ions, ions of an inert gas such as helium may be used. Thus, a structure as shown in FIG. 13A is obtained.

The surface of the insulating layer and the surface of the second substrate 1 such as a separately prepared single crystal Si wafer are overlapped and brought into contact. Thus, a structure as shown in FIG. 13B is obtained.

After that, when annealing is performed at 600 ° C., the wafer is separated into two pieces near the projected range of ion implantation (ion implantation layer 40). Since the ion-implanted layer 40 when separated by heat treatment is porous, the separated surface is rough. The surface on the second substrate 1 side can be smoothed by at least one of polishing and hydrogen annealing. Thus, a structure as shown in FIG. 13 (c) or (d) is obtained.

Further, if necessary, before or after smoothing,
It is also preferable to perform heat treatment (bonding annealing) for increasing the bonding strength.

That is, a semiconductor layer 38 of non-porous single-crystal Si having a thickness of 0.2 μm can be formed on the insulating layer 39. When the film thickness of the formed semiconductor layer 38 is measured at 100 points over the entire surface, the uniformity of the film thickness is about 201 nm ± 6 nm.

Further, a heat treatment was carried out at 1100 ° C. for 1 hour in hydrogen, and the surface roughness was evaluated with an atomic force microscope.
The mean square roughness in the m-square region is about 0.2 nm, which is equivalent to that of a commercially available single crystal Si mirror wafer.

As a result of a cross-sectional observation with a transmission electron microscope, it can be confirmed that no new crystal defects have been introduced into the semiconductor layer 38 and good crystallinity is maintained.

Thereafter, in order to adjust the shape of the peripheral portion, as shown in FIG. 13E, a mask exposing the semiconductor layer 38 and the insulating layer 39 in the peripheral region having a width of 3 mm from the outer peripheral end.
MK is applied, and the exposed portion is patterned and removed.

A 12-digit alphanumeric character is printed by a laser marking device near a notch or an orientation flat in a 3 mm area on the outer periphery. As described above, it may be a symbol or a barcode. At that time, there is no increase in particles on the SOI wafer.

At this time, the laser power is set to about 220 mW. Of course, the power should be adjusted according to the depth and shape of the mark.

The size of the alphanumeric characters conforms to the SEMI standard described above. In the case of a general laser marking device, the size of the character can be adjusted in steps of about 0.8 mm, so that it can be small or large so that it can be easily read.

Thereafter, the mask MK is removed, cleaning and inspection are performed, and the SOI substrate having the structure shown in FIG.

At the same time, the ion-implanted layer remaining on the substrate portion 36 side of the first substrate was flattened by at least one of etching, polishing and annealing, and the ion-implanted layer was also removed. It can be loaded again as the first substrate 30 or as the second substrate 1.

As a modified example, in the present embodiment, the single-crystal Si is deposited on the first substrate by 0.50% by CVD in advance.
μm epitaxial growth may be performed.

The growth conditions at that time are as follows, for example.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr) Temperature: 950 ° C. Growth rate: 0.30 μm / min In this case, when the wafer is put again as the first substrate, the wafer thickness can be semi-permanently reused by supplementing the wafer thickness reduction with the epitaxial layer. That is, in the second and subsequent repetitions, the epitaxial film thickness is not 0.50 μm but the wafer thickness reduction, and the ion-implanted layer is formed inside the epitaxial layer.

Further, after the ion implantation is performed, an external force for separation is applied as in Embodiment 16 to grow a crack from the end of the bonded substrate without separation by heat treatment. May go.

Further, the smoothing step may be performed after the marking.

(Embodiment 17) Referring again to FIG.
With reference to (b), (c), and (e), a method of manufacturing a semiconductor substrate by a non-bonding method will be described.

As shown in FIGS. 14A and 14B,
A substrate 1 made of one single crystal CZ-Si wafer is prepared, and an oxide film 41 made of 50 nm SiO2 is formed thereon by thermal oxidation. The purpose of this oxide film is to prevent surface roughness at the time of ion implantation, and may be omitted.

O ⁺ is supplied at 180 keV through the oxide film 41 on the surface.
× 10 ¹⁷ cm ^-2 ions are implanted. The temperature during the injection was 550 ° C. As a result, an oxygen ion implanted layer having a concentration peak near the interface between the epitaxial layer and the original substrate is formed. Nitrogen ions may be implanted in addition to or instead of oxygen ions.

After that, the substrate was placed in an O ₂ (10%) / Ar atmosphere for 1350 minutes.
Heat treatment at 4 ° C. for 4 hours.

Thereafter, the temperature is further increased to 1350 ° C. in an O ₂ (70%) / Ar atmosphere.
Then, a heat treatment is performed for 4 hours to complete an SOI substrate having an SOI layer of 300 nm and a buried oxide film of 90 nm as shown in FIG.

As shown in FIG. 14D, when the mask MK is applied to the surface region of the semiconductor layer 3 and the center of the wafer is (0, 0) with the notch of the substrate facing upward, X: -9. 25 to +9.25 mm Y: +93.7 to +96.5 mm Height 2.8 mm Length 18.5 mm Exposed from the mask, the semiconductor layer 3 and the insulating layer 2 are patterned and removed by etching, and the base is supported. The substrate is exposed.

While the surface area of the semiconductor layer 3 is covered with the mask, a 10-digit ID code is printed on the print area by a laser mark device.

The laser power at that time was 220 mW,
The size of the alphanumeric characters is based on the SEMI standard. Since the size of the character can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read.
In that case, the size of the region from which the SOI structure is removed by patterning may be changed. In particular, when the size of the character is reduced, the area that is unnecessarily removed by patterning increases. Therefore, the area is reduced to increase the number of chips that can be obtained.

For a specific application, it does not have to be SEMI standard.

After removing the mask MK and removing the surface oxide film 41, the SOI layer 200 nm / buried oxide film 120 nm
SOI wafer is completed. Thereafter, hydrogen annealing may be further performed. ((E) of FIG. 14) Thereafter, cleaning and inspection are performed, and the package is shipped.

As described above, the marking method used in the present invention described by taking each embodiment as an example includes, as described above, a marking using a laser such as an Nd: YAG laser or a CO2 laser, or a diamond pen. . Further, after forming the mark, the convex portion of the mark may be removed by polishing or the like at an appropriate timing.

The mask used in each embodiment is SOI
Although very effective in preventing particles on the layer surface, it is also possible to perform marking without using a mask and then perform a particle removal step. The particle removing step includes wet cleaning, brush cleaning, scrub cleaning, ultrasonic cleaning, polishing, etching and the like.

In the case of the bonding method, before bonding, the bonding surface is subjected to plasma treatment and rinsed with pure water, and then bonded, or after bonding, at least one of oxygen and nitrogen is bonded. 400 ° C ~ 110 in atmosphere containing
It is also preferable to perform a 0 ° C. bonding annealing.

Heat treatment in a hydrogen atmosphere is performed at 800 ° C. to 11 ° C.
It may be performed at 50 ° C. or higher.

[0197]

(Example 1) As shown in FIGS.
100 inch center of inch SOI wafer with notch up
Is set to (0, 0), X: −9.25 to +9.25 mm Y: +93.7 to +96.5 mm The width L2 is 2.8 mm and the length L1 is 18.5 m.
The portions of the semiconductor layer 3 and the insulating layer 2 (the portions other than the edge exclusion) were removed by etching to expose the underlying support substrate.

A 10-digit ID code was printed on the exposed area 14 using an NEC laser marker SL473F.

The laser power at that time was 220 mW.

The size of the alphanumeric characters is: height: 1.624 ± 0.025 mm width: 0.812 ± 0.025 mm line thickness: 0.200 + 0.050 mm to 0.200−
0.150 mm Character spacing: 1.420 ± 0.025 mm SEMI standard.

Since the size of the character can be adjusted in steps of about 0.8 mm, the size of the character may be small or it may be large for easy reading. In that case, the size of the region from which the SOI layer and the insulating layer are removed by patterning may be changed. In particular, when the size of the character is reduced, the area that is unnecessarily removed by patterning increases, so that the print area can be reduced and the number of chips that can be obtained can be increased.

Example 2 As shown in FIGS. 1 and 2, a 12-digit ID code is printed by a laser marking device in a peripheral area 13 where a supporting substrate under a commercially available bonded SOI wafer is exposed. did. At that time, the 12-digit characters were printed in a straight line.

The laser power was set to 220 mW.

The size of the alphanumeric characters is as follows: height: 1.624 ± 0.025 mm width: 0.812 ± 0.025 mm line thickness: 0.200 + 0.050 mm to 0.200−
0.150 mm Character spacing: 1.420 ± 0.025 mm SEMI standard.

Since the size of the character can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read. Also, when the width of the peripheral removal area becomes smaller, a smaller character is more preferable.

(Example 3) A 12-digit ID code was printed by a laser marking device in a peripheral region of a commercially available SOI wafer in which the underlying support substrate was covered only with an oxide film.

The laser power at that time was 300 mW. The concave portion formed by the laser penetrated the oxide film and reached the supporting substrate.

The size of the alphanumeric characters is as follows: height: 1.624 ± 0.025 mm width: 0.812 ± 0.025 mm line thickness: 0.200 + 0.050 mm to 0.200−
0.150 mm Character spacing: 1.420 ± 0.025 mm SEMI standard.

Since the size of the character can be adjusted in steps of about 0.8 mm, the size of the character may be small or it may be large for easy reading. In this case, too, small characters are preferable when the margin removal becomes narrow.

For a specific application, it does not have to be SEMI standard.

(Example 4) P having a specific resistance of 0.01 Ω · cm
The first single-crystal Si substrate of the mold was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 11 (min) Thickness of porous Si layer: 12 (μm) Porous Si The thickness of the layer is not limited to this, and can be selected from a range of several hundred μm to about 0.1 μm.

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. The surface of the porous Si layer is treated with hydrofluoric acid, and only the oxide film on the surface of the porous Si layer is removed, leaving the oxide film on the inner wall of the hole. The epitaxial growth was performed by 0.3 μm. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr) Temperature: 950 ° C. Growth rate: 0.3 μm / min Prior to epitaxial growth by introducing source gas,
Heat treatment (prebaking) was performed in an H2 atmosphere in an epitaxial apparatus.

Further, as an insulating layer, a 200 nm oxide film (Si) was formed on the surface of the epitaxial Si layer by thermal oxidation.
O ₂ layer).

A second S prepared separately from the surface of the SiO ₂ layer
After overlapping and contacting the surface of the i-substrate, a heat treatment was performed for 2 hours at a temperature of 1100 ° C. in an oxygen-containing atmosphere, and bonding was performed.

Most of the bonded substrate formed as described above on the first substrate side is ground, and then the remaining portion is removed by reactive ion etching to expose the porous Si layer. Was.

Thereafter, the porous Si layer transferred on the second substrate was treated with hydrofluoric acid having a HF concentration of 49 wt% and H ₂ O ₂ concentration of 30 watts.
Etching was performed while stirring with a mixed solution of t% hydrogen peroxide and water. Single crystal Si remained without being etched.
The porous Si was selectively etched and completely removed.

Thus, a single-crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of the porous Si. When the thickness of the formed single crystal Si layer was measured at 100 points over the entire surface in the plane, the uniformity of the film thickness was 201.
nm ± 4 nm.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Further, hydrogen annealing was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope. As a result, the mean square roughness in a 50 μm square region was about 0.1 μm.
At 2 nm, it was equivalent to a commercially available Si wafer.

Thereafter, in order to adjust the shape of the peripheral portion, the Si layer and the SiO ₂ layer in the peripheral region having a width of 3 mm from the outer peripheral edge were removed by patterning.

A 12-digit alphanumeric character was printed near the notch in the peripheral area having a width of 3 mm by a laser mark device. At that time, there was no increase in particles on the SOI wafer.

(Example 5) P having a specific resistance of 0.01 Ω · cm
The first single-crystal Si substrate of the mold was anodized in an HF solution.

Anodizing conditions were as follows. First stage Current density: 7 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 5 (min) Thickness of first porous Si layer on the surface side: 5 0.5 (μm) 2nd stage Current density: 30 (mA · cm−2) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 10 (sec) Below the first porous Si layer Thickness of second porous Si layer: 0.2 (μm) This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner walls of the holes of the first and second porous Si layers were covered with the thermal oxide film. The surface of the porous Si layer is treated with hydrofluoric acid, and only the oxide film on the surface of the porous Si layer is removed, leaving the oxide film on the inner wall of the hole. The epitaxial growth was performed by 0.3 μm.
The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr) Temperature: 950 ° C. Growth rate: 0.3 μm / min Prior to the epitaxial growth, heat treatment was performed in an H ₂ atmosphere in an epitaxial apparatus. Actually, the crystal defects of the epi layer could be reduced to 10 ⁴ cm ⁻² or less by this treatment.

Further, as an insulating layer, a 200 nm oxide film (Si) was formed on the surface of the epitaxial Si layer by thermal oxidation.
O ₂ layer).

The second S prepared separately from the surface of the SiO ₂ layer
After overlapping and contacting the surface of the i-substrate, 1100
A heat treatment was performed at a temperature of 2 ° C. for 2 hours to perform bonding.

[0230] The bonded substrate formed as described above is placed along the interface between the first and second porous Si layers in the second direction.
Was separated in the porous Si layer. As a separation method, a method of inserting a solid wedge and a method of inserting a water wedge by a water jet were used.

Thereafter, the porous Si layer transferred onto the second substrate was treated with hydrofluoric acid having an HF concentration of 49 wt% and H ₂ O ₂ concentration of 30 w
Selective etching was performed while stirring with a mixture of t% hydrogen peroxide and water.

Thus, a single-crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of the porous Si. When the thickness of the formed single crystal Si layer was measured at 100 points over the entire surface in the plane, the uniformity of the film thickness was 201.
nm ± 4 nm.

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Further, a heat treatment was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope.
Mean square roughness in the area of 50 μm square is about 0.2 nm
Was equivalent to a commercially available Si wafer.

Thereafter, in order to adjust the shape of the peripheral portion, the Si layer and the SiO ₂ layer in the peripheral region having a width of 2.5 mm from the outer peripheral end were removed by patterning.

A 12-digit alphanumeric character was printed by a laser marking device near the notch in the peripheral area. At that time, there was no increase in particles on the SOI wafer.

At this time, the laser power was 220 mW.

The size of the alphanumeric characters is: height: 1.624 ± 0.025 mm width: 0.812 ± 0.025 mm line thickness: 0.200 + 0.050 mm to 0.200−
0.150 mm Character spacing: 1.420 ± 0.025 mm SEMI standard.

Further, the porous Si remaining on the first substrate is also selectively etched while being stirred with the above-mentioned mixed solution of hydrofluoric acid, hydrogen peroxide and water. After that, hydrogen annealing was performed to return the substrate to a state where it can be used again as the first substrate or the second substrate.

(Example 6) P having a specific resistance of 0.01 Ω · cm
The first single-crystal Si substrate of the mold was anodized in an HF solution.

The anodizing conditions were as follows. First stage Current density: 7 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 5 (min) Thickness of first porous Si layer on the surface side: 5 0.5 (μm) 2nd stage Current density: 30 (mA · cm ⁻² ) Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1 time: 10 (sec) Below the first porous Si layer Thickness of second porous Si layer: 0.2 (μm) This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner walls of the holes of the first and second porous Si layers were covered with the thermal oxide film. The surface of the porous Si layer is treated with hydrofluoric acid, and only the oxide film on the surface of the porous Si layer is removed, leaving the oxide film on the inner wall of the hole. The epitaxial growth was performed by 0.3 μm.
The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr) Temperature: 950 ° C. Growth rate: 0.3 μm / min Prior to the epitaxial growth, heat treatment was performed in an H ₂ atmosphere in an epitaxial apparatus. Actually, the crystal defects of the epi layer could be reduced to 10 ⁴ cm ⁻² or less by this treatment.

Further, as an insulating layer, a 200 nm oxide film (Si) was formed on the surface of the epitaxial Si layer by thermal oxidation.
O ₂ layer).

Another Si substrate was prepared, and a portion that would be outside the contact edge in the peripheral region of the substrate near the notch, that is, slightly inclined by beveling processing
12-digit alphanumeric characters were printed on the peripheral surface of the Si substrate using a laser marking device.

At this time, the laser power was 220 mW.

The size of the alphanumeric characters is as follows: height: 1.624 ± 0.025 mm width: 0.812 ± 0.025 mm line thickness: 0.200 + 0.050 mm to 0.200−
0.150 mm Character spacing: 1.420 ± 0.025 mm SEMI standard was followed by washing.

The surface of the SiO ₂ layer on the first Si substrate and the surface of the marked second Si substrate were overlapped and brought into contact with each other, and then heat-treated at a temperature of 1100 ° C. for 2 hours, followed by bonding. Was done. Later analysis showed that at this time,
It turned out that it was not stuck in the marked part.

The bonded substrate formed as described above was separated inside the second porous Si layer along the interface between the first porous layer and the second porous layer. As a separation method, a method of inserting a solid wedge and a method of inserting a water wedge by a water jet were used.

Thereafter, the first and second porous Si layers transferred onto the second substrate were treated with hydrofluoric acid having a HF concentration of 49 wt% and H
Selective etching was carried out while stirring with a mixed solution of hydrogen peroxide and water having a concentration of ₂ O _{2 of} 30 wt%.

Thus, a single-crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of the porous Si. When the thickness of the formed single crystal Si layer was measured at 100 points over the entire surface in the plane, the uniformity of the film thickness was 201.
nm ± 4 nm.

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Further, a heat treatment was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope.
Mean square roughness in the area of 50 μm square is about 0.2 nm
Was equivalent to a commercially available Si wafer.

Thereafter, in order to adjust the shape of the peripheral portion, the SOI layer in the peripheral region having a width of 2.5 mm was removed by patterning from the outer peripheral end, and the SiO ₂ layer having a width of 2.3 mm was removed by patterning from the peripheral end. .

Since the mark portions were not pasted together from the beginning, they hardly deformed even after steps such as separation and etching.

As described in detail above, according to each embodiment,
Since laser marking is performed on an area not having the SOI multilayer structure, generation of particles is suppressed. Also, there is no need to adjust and optimize the laser power depending on the combination of SOI layer thicknesses. Any SOI structure can be marked under uniform conditions.

The generation of particles is a major cause of lower device yield. In particular, recent 0.
Under the rule of 1 micron or less, no particles or small particles are allowed. In such a situation, optimizing the laser power or the like according to the SOI film thickness configuration can somewhat suppress the generation of particles. However, this has the effect of reducing yield during mass production. Therefore,
As long as marking can be performed under uniform conditions even if the SOI film thickness configuration is slightly different, it is possible to suppress the increase in particles to the minimum possible.

[0257]

According to the present invention, it is possible to provide a semiconductor substrate in which the reading of the ID mark is easy, the number of attached particles is small, and the marking is easy.

[Brief description of the drawings]

FIG. 1 is a top view of a part of a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a part of a semiconductor substrate according to one embodiment of the present invention.

FIG. 3 is a top view of a part of another semiconductor substrate according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view of a part of another semiconductor substrate according to one embodiment of the present invention;

FIG. 5 is a top view of a part of the semiconductor substrate according to one embodiment of the present invention;

FIG. 6 is a cross-sectional view of a part of a semiconductor substrate according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view of a part of a bonded substrate according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing step of the semiconductor substrate according to the embodiment of the present invention.

FIG. 9 is a view showing a flowchart of a semiconductor substrate manufacturing process according to one embodiment of the present invention;

FIG. 10 is a view showing a flowchart of a manufacturing process of the semiconductor substrate according to one embodiment of the present invention;

FIG. 11 is a view showing a flowchart of a manufacturing process of a semiconductor substrate according to one embodiment of the present invention;

FIG. 12 is a view showing a flowchart of a semiconductor substrate manufacturing process according to one embodiment of the present invention;

FIG. 13 is a cross-sectional view for explaining a manufacturing step of the semiconductor substrate according to the embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining a manufacturing step of the semiconductor substrate according to one embodiment of the present invention;

FIG. 15 is a view showing a flowchart of a manufacturing process of the semiconductor substrate according to one embodiment of the present invention;

FIG. 16 is a view showing a flowchart of a manufacturing process of the semiconductor substrate according to one embodiment of the present invention;

FIG. 17 is a view showing a flowchart of a manufacturing process of a semiconductor substrate according to one embodiment of the present invention;

FIG. 18 is a diagram showing a cross-sectional shape of a laser mark.

FIG. 19 is a top view of a part of a semiconductor substrate.

FIG. 20 is a cross-sectional view of a part of a semiconductor substrate.

FIG. 21 is a top view of a part of an SOI substrate.

FIG. 22 is a cross-sectional view of a part of an SOI substrate.

FIG. 23 is a diagram showing a cross-sectional shape of a laser mark.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating layer 3 Semiconductor layer (SOI layer) 4 Mark

Claims (54)

[Claims] 1. A semiconductor substrate having a semiconductor layer provided above a support substrate with an insulating layer interposed therebetween, wherein a mark is formed in a region other than a surface region of the semiconductor layer. . 2. The semiconductor substrate according to claim 1, wherein said mark is at least one selected from the group consisting of numbers, letters, symbols, and bar codes. 3. The semiconductor substrate according to claim 1, wherein the region is a peripheral region of the support substrate where the semiconductor layer does not exist. 4. The semiconductor substrate according to claim 3, wherein an outer edge of said peripheral region is an outer peripheral edge of said support substrate, and an inner edge of said peripheral region is a portion at least 1 mm inward from said outer peripheral edge. 5. The semiconductor substrate according to claim 1, wherein the region is an internal region of the support substrate where the semiconductor layer does not exist locally. 6. The semiconductor substrate according to claim 1, wherein said region is a back surface of said support substrate. 7. The semiconductor substrate according to claim 1, wherein the mark is near a notch or an orientation flat. 8. The semiconductor substrate according to claim 1, wherein said mark is formed from a concave portion and / or a convex portion formed on a surface of said region. 9. The semiconductor substrate according to claim 1, wherein said mark is formed by a laser beam. 10. The semiconductor substrate according to claim 1, wherein the mark is formed by damaging a surface. 11. The semiconductor substrate according to claim 1, wherein said semiconductor substrate is an SOI substrate. 12. The semiconductor substrate according to claim 11, wherein said SOI substrate is a bonded SOI substrate. 13. The bonded SOI substrate comprises hydrogen and / or
The semiconductor substrate according to claim 12, further comprising the semiconductor layer separated by an inert gas ion implantation layer. 14. The semiconductor substrate according to claim 12, wherein the bonded SOI substrate has the semiconductor layer formed by transferring a non-porous semiconductor layer formed on a porous body to the support substrate. 15. The semiconductor substrate according to claim 11, wherein said SOI substrate is an SOI substrate having said insulating layer formed by ion implantation of oxygen and / or nitrogen and heat treatment. 16. A method for manufacturing a semiconductor substrate having a semiconductor layer provided over a supporting substrate with an insulating layer interposed therebetween, comprising a step of forming a mark in a region other than a surface region of the semiconductor layer. Of manufacturing a semiconductor substrate. 17. A mark, a character, a symbol,
2. The method for manufacturing a semiconductor substrate according to claim 1, wherein at least one kind selected from the group consisting of barcodes is drawn. 18. The method according to claim 16, wherein the region is a peripheral region of the support substrate where the semiconductor layer does not exist. 19. An outer edge of the peripheral region is an outer peripheral edge of the support substrate, and an inner edge of the peripheral region is 1 mm from the outer peripheral edge.
19. The method for manufacturing a semiconductor substrate according to claim 18, wherein the portion is located inside the inside. 20. The method according to claim 16, wherein the region is an internal region of the support substrate where the semiconductor layer does not locally exist. 21. The method according to claim 16, wherein the region is a back surface of the support substrate. 22. The method according to claim 16, wherein the mark is drawn near a notch or an orientation flat. 23. The method according to claim 16, wherein the mark is drawn by forming irregularities on the surface of the region. 24. The method for manufacturing a semiconductor substrate according to claim 16, wherein said mark is drawn by a laser beam. 25. The method of manufacturing a semiconductor substrate according to claim 16, wherein the mark is drawn by damaging a surface. 26. The method according to claim 16, wherein the semiconductor substrate is an SOI substrate. 27. The method according to claim 26, wherein the SOI substrate is a bonded SOI substrate. 28. The bonded SOI substrate is formed by implanting ions of hydrogen and / or an inert gas into a first substrate, bonding the first substrate to a second substrate serving as the supporting substrate, 28. The method for manufacturing a semiconductor substrate according to claim 27, wherein the semiconductor substrate is formed by a method including a step of separating at a separation layer formed by implantation. 29. The method according to claim 28, wherein the first substrate has a semiconductor layer formed by epitaxial growth. 30. The method of manufacturing a semiconductor substrate according to claim 28, comprising a step of smoothing the separated surface by hydrogen annealing and / or polishing. 31. The fabrication of a semiconductor substrate according to claim 27, wherein the bonded SOI substrate has the semiconductor layer formed by transferring a non-porous semiconductor layer formed on a porous body to the support substrate. Method. 32. The method according to claim 31, wherein the surface of the semiconductor layer is smoothed by hydrogen annealing and / or polishing after removing the porous body. 33. The method according to claim 31, further comprising a step of removing a peripheral portion of the transferred semiconductor layer. 34. The method according to claim 34, wherein the step of removing the porous body includes the step of bonding.
32. The method for manufacturing a semiconductor substrate according to claim 31, comprising a step of separating an SOI substrate in a layer of a porous body and a step of etching the porous body remaining on a separation surface side of the non-porous semiconductor layer. 35. A first substrate having a non-porous semiconductor layer formed on a non-porous substrate via a layer of the porous body as the bonded SOI substrate, and is used as the support substrate. 28. The method for manufacturing a semiconductor substrate according to claim 27, further comprising the semiconductor layer formed by transferring the non-porous semiconductor layer by bonding to a second substrate and separating the porous body layer. 36. The bonded SOI substrate, comprising: forming a layer of the porous body by anodization on a non-porous substrate; forming a protective film on the inner wall surface of the hole of the porous body; and performing hydrogen baking. ,
A non-porous semiconductor layer is epitaxially grown on the porous body layer, an insulating layer is formed on the surface thereof, a first substrate is prepared, and the first substrate is bonded to the second substrate.
36. The semiconductor layer formed by separating the porous body layer, removing the porous body remaining on the separation surface, and smoothing the exposed surface of the non-porous semiconductor layer. Of manufacturing a semiconductor substrate. 37. The method of manufacturing a semiconductor substrate according to claim 35, wherein a solid and / or fluid wedge is inserted into the bonded substrates to separate them. 38. The method for manufacturing a semiconductor substrate according to claim 35, wherein the bonded substrates are separated by applying at least one of a pressing force, a tensile force, a shearing force, and an ultrasonic vibration. 39. The bonded SOI substrate prepares a first substrate having a non-porous semiconductor layer formed on a non-porous substrate via a layer of the porous body, and serves as the support substrate. The non-porous semiconductor layer is transferred and formed by removing the non-porous substrate and the layer of the porous body by at least one of grinding, polishing, and etching by bonding to the second substrate. The method for manufacturing a semiconductor substrate according to claim 27, comprising the semiconductor layer formed. 40. The method according to claim 26, wherein the SOI substrate is an SOI substrate having the insulating layer formed by ion implantation of oxygen and / or nitrogen and heat treatment. 41. The method for manufacturing a semiconductor substrate according to claim 40, further comprising a step of partially removing said semiconductor layer. 42. In a method for manufacturing a semiconductor substrate having a semiconductor layer provided over at least one layer of a different material above a supporting substrate, a step of forming a mark in a region other than a surface region of the semiconductor layer A method for manufacturing a semiconductor substrate, comprising: 43. A semiconductor substrate in which a semiconductor layer is formed above a supporting substrate via at least one layer made of a different material, wherein a mark is formed in a region other than a surface region of the semiconductor layer. Semiconductor substrate. 44. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a bonded SOI substrate, and the mark is formed on a surface of the support substrate that has not been bonded. 45. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a bonded SOI substrate, and the mark is formed on a surface of the support substrate outside a position where a contact edge exists. 46. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a bonded SOI substrate, and the mark is formed on a surface of the support substrate outside a position where a bonding edge is present. 47. The semiconductor device according to claim 1, wherein the semiconductor substrate is a bonded SOI substrate, and the mark is formed on a surface of the support substrate formed by locally retreating a bonding edge inward. Semiconductor substrate. 48. The method according to claim 16, wherein the mark is formed in a state where a surface region of the semiconductor layer is covered with a film other than the semiconductor layer. 49. The mark is formed in a state where a surface region of the semiconductor layer is covered with a porous layer.
A method for manufacturing a semiconductor substrate as described above. 50. The method of manufacturing a semiconductor substrate according to claim 16, wherein the mark is formed in a state where a surface region of the semiconductor layer is covered with a mask for forming a peripheral portion. 51. A step of preparing a first substrate and a second substrate on which the mark is formed, bonding the first and second substrates together, and removing unnecessary portions of the first substrate. By that
17. The method for manufacturing a semiconductor substrate according to claim 16, comprising a step of transferring a transfer layer of the first substrate. 52. A step of preparing a first substrate, a step of forming the mark on the periphery of the second substrate, and bonding the first and second substrates so that they are not bonded at a portion where the mark is present. By bonding and removing unnecessary portions of the first substrate,
Transferring a transfer layer of the first substrate.
7. The method for manufacturing a semiconductor substrate according to item 6. 53. A step of preparing a first substrate, a step of forming the mark on a peripheral portion of the second substrate, and a step of forming a contact edge or a bonding edge inside a portion having the mark. 17. The method for manufacturing a semiconductor substrate according to claim 16, further comprising: transferring a transfer layer of the first substrate by bonding the first and second substrates and removing an unnecessary portion of the first substrate. . 54. A step of preparing a first substrate, a step of forming the mark on a peripheral portion of a second substrate, and a step of localizing a bonding edge so that the bonding edge exists inside a portion having the mark. To retreat inward,
17. The method of manufacturing a semiconductor substrate according to claim 16, further comprising: transferring the transfer layer of the first substrate by bonding the first and second substrates and removing unnecessary portions of the first substrate. Method.