JP2001237842A - Fault diagnosis method for multiplex communication equipment and multiplex communication equipment adopting the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplex communication technology by which a discrimination time of a communication error due to a broken line can be decreased and the production of reset processing can accurately be discriminated. SOLUTION: The multiplex communication equipment repeats an access to slaves 801, 802 from a master 800 with a 1st communication format including data and a return access to the master from the slaves with the 1st communication format including data or an access to the slaves from the slaves during reset processing with a 2nd communication format not including data after the reduction of a voltage in a prescribed cycle. Then the master discriminates that a communication line to the specific slave 801 is broken when the slave 801 cannot receive the access by the 1st communication format and the access by the 2nd communication format consecutively for a prescribed number of times from the slave 801.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality diagnosis method for a multiplex communication device and a multiplex communication device using the same.

[0002]

2. Description of the Related Art A conventional multiplex communication device mounted on a vehicle, for example, has a configuration as shown in FIG. This conventional multiplex communication apparatus includes a master (master station) 100 and one or a plurality of slaves (slave stations), here, a slave (1) 101, a slave (2) 102, and a communication line 115. , The slaves 101 and 102 each have a communication IC 113 having a voltage monitoring circuit 111 and a communication control circuit 112, and a 5V inputting a battery power supply VB.
Regulator circuit (5V REG) 104 and communication IC
And a CPU 110 connected to the CPU 113. The multiplex communication is performed between the master 100 and the slaves 101 and 102 according to the multiplex communication format shown in FIG.

In the conventional multiplex communication format shown in FIG. 6, in the case of a normal data transmission format 300 from the master 100 to each slave, a start-of-message (SOM) 302, an address (ADR) 303, It is composed of a normal data transmission command (COM1) 304, data (DATA) 305, parity (PRTY) 306, and end of message (EOM) 307.

In the case of the normal data transmission format 301 from the slaves 101 and 102 to the master 100, the same SOM 302 and ADR 303 as described above, and a normal data transmission command (COM 2) 308 from each slave 101 or 102 to the master 100, DATA305, PRTY306, and EOM similar to
307.

The voltage monitoring circuit 111 in the conventional communication IC 113 has the configuration shown in FIG. 5V REG
A resistor R1 is connected between the output VDD of the output terminal 104 and the ground GND.
And the resistor R2 are connected in series. In parallel with this, a resistor R3 and a diode D1 are connected between VDD and GND.
Are connected in series. Further, a comparator COMP is inserted between VDD and GND in parallel with them. Resistors R1 and R2 are connected to the inverting input terminal of this COMPM.
A potential V1 between the resistor R3 and the diode D1 is connected to a non-inverting input terminal of the COPM. Further, a transistor TR1 is connected between VDD and GND.

The base of this transistor TR1 has CO
The output potential V3 of PM is connected. A resistor R4 is inserted between VDD and the base of the transistor TR1, and a resistor R5 is inserted between VDD and the collector of the transistor TR1. A capacitor C1 is inserted between the collector of the transistor TR1 and GND. The collector voltage V4 of the transistor TR1 is output as the output RES of the voltage monitoring circuit 111 via the Schmitt inverter SINV.

The operation of the voltage monitoring circuit 111 will be described as follows. As shown in FIG. 8, when the output VDD of the 5V regulator 5V REG changes, the voltage V
1 changes, and the output V3 of the COMP changes depending on the magnitude relationship between the voltages V1 and V2. Thereby, the collector voltage V4 of the transistor TR1 also changes.

Here, when the output V4 of the transistor TR1 becomes lower than the threshold value Vth- of the low level input voltage of SINV, the output RES of the voltage monitoring circuit 111 becomes high level (timing 401). Then, V4 becomes S
When the voltage becomes higher than the threshold value Vth + of the high-level input voltage of INV, the output RES becomes low level (timing 402). When the output RES of the voltage monitoring circuit 111 is at a high level, the CPU 110 and the communication IC 113 connected to the RES are reset.

Next, the processing contents of the CPU 110 after reset of the conventional multiplex communication apparatus will be described. As shown in FIG. 9, when a reset signal 500 is input from the output RES of the voltage monitoring circuit 111 to the CPU 110 and then the reset signal 500 is released, the reset sequence 501 and the communication program execution 5
02 is performed.

In the reset sequence 501, first, the CP
The registers of the internal and peripheral modules of the U are initialized, the vector address read and the start address read are sequentially performed, and thereafter, the process proceeds to a communication program execution process 502. In the execution process 502 of the communication program, first, the process is set, and data reading from the CPU 110 to the communication IC 113, data writing from the CPU 110 to the communication IC 113, a communication start command from the CPU 110 to the communication IC 113, and interrupt standby are sequentially executed. Thus, in the reset sequence 501 in the conventional multiplex communication device,
When the reset signal 500 is output from the voltage monitoring circuit 111, the communication is started after the elapse of the CPU processing time t.

[0011]

However, such a conventional multiplex communication device has the following problems. That is, the master 100, the slave (1) 101,
The slave (2) 102 is placed under different environments.
Therefore, the resistors R1, R2, and R constituting the voltage monitoring circuit 111 of each of the master 100 and the slaves 101 and 102
3. The ambient temperature of the diode D1 is different. Further, the resistors R1, R2, R3, and the diode D1 may have input voltages V1, V2 to the comparator COMP due to manufacturing variations.
Causes variation from the design value. Due to these variations, the low voltage determination level of the voltage monitoring circuit 111 also varies. As a result, the master 100 and the slave 10
The state of the output RES in each of the terminals 1 and 102 is different.

FIG. 10 shows a simulation result of the variation of the low voltage determination threshold value Vth- of the voltage monitoring circuit 111. The low voltage determination threshold value under the simulation conditions shown in the right box in the figure is a design value of 2.63 V (T
YP), 3.26V at MAX, 2.0 at MIN
It was found to vary until the voltage reached 5V.

When the low-voltage determination threshold value Vth- varies, the master 100 and the slave 101,
FIG. 11 is a timing chart showing how communication between the communication systems 102 is affected. According to this timing chart, when the battery voltage VB changes, each of the 5V REGs of the master 100 and the slaves 101 and 102 is changed.
Output VDD also changes. Here, it is assumed that the low voltage determination thresholds Vth− of the voltage monitoring circuits 111 of the master 100 and the slaves 101 and 102 vary as shown in 713, 714 and 715 in the figure.

In this case, the RES of the slave (1) 101
Only the reset signal 702 is output. Therefore, since only the CPU 110 of the slave (1) 101 performs the process 703 after the reset, it is impossible to output a reply signal to the transmission signals M TX2 and M TX4 from the master 100 (timings 704 and 705).
For this reason, since the master 100 does not receive a reply from the slave (1) 101, it counts as a communication error and stores it. However, the variation in the low-voltage determination threshold value Vth− of the voltage monitoring circuit 111 calms down when the circuit article warms up, and thereafter, communication is recovered, communication errors are no longer counted, and the warning lamp is turned on temporarily. But disappears immediately.

On the other hand, the master 100 and the slave (1) 1
01 is disconnected, communication between the master 100 and the slave (1) 101 cannot be performed at all. (1) No return signal is returned from 101, communication errors continue to be counted, and recovery is unlikely. Therefore, when four counts of communication errors are counted consecutively (timing 712), it is determined that the communication line 115 is broken, and the process shifts to the fail-safe mode and turns on the warning lamp.

In general, in a multiplex communication apparatus, it is desirable to shorten the determination time of a communication error due to a disconnection of a communication line so as to minimize communication in a disconnected state. On the other hand, the communication error due to the reset then returns to normal, but the communication error due to the disconnection hardly recovers to normal thereafter. Therefore, in order to detect a communication error due to disconnection and perform appropriate processing, it is necessary to distinguish and detect a communication error due to both of these different causes.

For this reason, conventionally, as described above, in order to distinguish a communication error due to a disconnection of a communication line from a communication error caused by a process after reset, the communication is continuously performed for a longer time than a time required for the process after reset. When an error has occurred (that is, when a continuous 4-count communication error has been counted), it is determined that the communication error has occurred due to the disconnection of the communication line.

However, when such a determination method is employed, in order to shorten the determination time of the communication error due to the disconnection of the communication line and to shorten the communication in the disconnected state as much as possible, high-speed processing can be performed. A high-performance CPU is required, and the cost is greatly increased.

Therefore, conventionally, it has been difficult to shorten the determination time of a communication error due to disconnection and to be able to distinguish between a communication error due to disconnection and a communication error due to resetting.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has as its object to provide a multiplex communication technique capable of shortening the determination time of a communication error due to disconnection and accurately determining the occurrence of reset processing. Aim.

[0021]

According to the first aspect of the present invention, there is provided a method for advancing an abnormal state of a multiplex communication apparatus, comprising: a multiplex communication apparatus having a matus and a slave and a communication line connecting between the master and the slave; Access performed by a first communication format including data, return access from the slave in a first communication format including data performed for the access of the master, or reset processing after a voltage drop from the slave. And the access in the second communication format during the reset process that does not include data when the access is made by the master during a predetermined cycle, and the master accesses from the specific slave in the first communication format. And access using the second communication format It is to determine the disconnection of the communication line with respect to the particular slave when it is unable to receive continuously a predetermined number of times.

According to a second aspect of the present invention, there is provided a multiplex communication apparatus including a mata-soo and a slave and a communication line connecting the master and the slave, wherein the master and the slave monitor a reference voltage,
A communication IC having a voltage monitoring unit and a communication control unit for outputting a reset signal when the voltage is lower than a predetermined value; a CPU connected to the communication IC; and a regulator for generating the reference voltage from a power supply and supplying the reference voltage to the communication IC The communication control unit of each of the communication ICs selects and outputs one of a normal transmission data register, a dummy data register, and an output signal of the normal transmission data register and an output signal of the dummy data register. A selector circuit, and a dummy data output permission circuit for outputting a select signal to the selector circuit, wherein the dummy data output permission circuit in the slave stores a reset signal output from the voltage monitoring unit, Is stored before writing the normal transmission data from the CPU. When receiving an access from the,
A dummy data output permission signal is output to the selector circuit, and when an access from the master is received after the writing of the normal transmission data from the CPU is completed, a normal transmission data output permission signal is output to the selector circuit, and a signal of the master is output. When the CPU receives an output signal of the dummy data register from a specific slave, it determines that reset processing is being performed. When the CPU does not receive an output signal of the normal transmission data register or an output signal of the dummy data register from a specific slave, communication is performed. This is to determine the disconnection of the line.

[0023]

According to the method for diagnosing an error in a multiplex communication apparatus according to the first aspect of the present invention, in the multiplex communication apparatus, access from a master to a slave in a first communication format including data and access from a slave to a master in the slave are performed. Reply access in the first communication format including data to be performed, or access in the second communication format during reset processing that does not include data to be performed when access is made from the master during reset processing after a voltage drop from the slave. Are repeated in a predetermined cycle, the master determines that the specific slave is in the process of being reset when it receives access from the specific slave in the second communication format, and also determines from the specific slave that the access is in the first communication format. Access also depends on the second communication format Access when not be received continues a predetermined number of times it is determined that the disconnection of the communication line for that particular slave.

Thus, the master distinguishes between the occurrence of the reset processing and the occurrence of the communication error due to the disconnection of the communication line,
In addition, a communication error due to the disconnection of the communication line can be determined within a short time.

In the multiplex communication apparatus according to the second aspect of the present invention, the dummy data output permission circuit in each slave stores a reset signal output from the voltage monitoring unit. When the access from the master is received before the end of the writing of the data, a dummy data output enable signal is output to the selector circuit. When the access from the master is received after the writing of the normal transmission data from the CPU, the normal transmission data is sent to the selector circuit. Outputs an output enable signal. The master CPU determines that the reset processing is being performed when the output signal of the dummy data register is received from the specific slave, and performs communication when neither the output signal of the normal transmission data register nor the output signal of the dummy data register is received from the specific slave. Determine the break in the line.

Thus, the master distinguishes between the occurrence of the reset processing and the occurrence of a communication error due to the disconnection of the communication line.
In addition, a communication error due to the disconnection of the communication line can be determined within a short time.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a system configuration of a multiplex communication apparatus according to one embodiment of the present invention. This multiplex communication apparatus includes a master (master station) 800, one or a plurality of slaves (slave stations), in this case, a slave (1) 801 and a slave (2) 802, and a communication line 115.

Master 800, slaves 801 and 802
Each includes a communication IC 804 having the same voltage monitoring circuit 111 and communication control circuit 803 as the conventional example, and a battery VB
, 5V regulator circuit, 5V REG, and communication IC8
The CPU 110 is connected to the CPU 110.

Voltage monitoring circuit 11 in communication IC 804
Reference numeral 1 denotes the configuration shown in FIG. 7 as in the conventional example, and its operation is as shown in FIG. CPU 110
Are the same as those shown in FIG. 9, and it takes time t.

The multiplex communication format employed in the present embodiment has the configuration shown in FIG. 2 and is the same as the conventional example in the normal data transmission format 300 from the master to each slave and the normal data transmission format from each slave to the master. In addition to the data transmission format 301, a dummy data transmission format 350 from each slave to the master is newly added.

This dummy data transmission format 350
Is the start of message SOM, address ADR,
Dummy data transmission command C from slave to master
OM3, parity PRTY, and end of message EOM.

Communication control circuit 80 in communication IC 804
3 is a configuration shown in FIG. 3 and includes a CPU I / F circuit 813 connected to the CPU 110 and a CPU I / F circuit 81.
A normal transmission data register 805, a dummy data register 806 for inputting a normal transmission data signal and a normal transmission data write signal which are the outputs of
A serial-parallel conversion circuit 808 connected to the communication line 115.

The communication control circuit 803 also inputs the normal transmission data signal which is the output signal of the normal transmission data register 805 and the dummy data signal which is the output signal of the dummy data register 806, and selects the dummy data signal for the serial-parallel conversion circuit 808. Selector 807 for outputting the output signal
And the received data from the communication line 115 is passed through the serial-parallel conversion circuit 808 to determine the received data,
A selection signal is output to the reception determination circuit 814 that outputs a reception end signal and the selector circuit 807, and the voltage monitoring circuit 1
11, a reception end signal output from the reception determination circuit 814, a normal data write end signal output from the CPU I / F circuit, and a CPU I / F circuit 813.
And a dummy data output permitting circuit 815 for receiving a master or slave set signal output from the controller and determining whether to output dummy data and outputting a select signal to the selector circuit 807.

Next, the operation of the multiplex communication apparatus having the above configuration will be described. First, in the communication control circuit 803, when VDD drops, if the master or slave set signal is a slave set signal, the reset signal RES output from the voltage monitoring circuit 111 is output to the dummy data output permission circuit 815.
To memorize. And if this reset is remembered,
When the access from the master 800 is received before the end of the writing of the normal transmission data from the CPU 110, that is, when the reception end signal is output, the selector 807
And outputs a dummy data signal to the communication line 115 from the dummy data register 806 via the selector 807 and the serial-parallel conversion circuit 808.

On the other hand, when the access from the master 800 is received after the writing of the normal transmission data from the CPU 110, that is, when the reception end signal is output,
A normal data output selector signal is output to the selector 807. That is, normal transmission data output is permitted, and the normal transmission data signal is output from the normal transmission data register 805 to the communication line 115 via the selector 807 and the serial-parallel conversion circuit 808.

When the master or slave set signal is a master set signal, a normal data output select signal is output to the selector 807 irrespective of the normal transmission data write end signal, the reception end signal, and the output RES. The transmission data signal is output to the communication line 115 via the selector 807 and the serial-parallel conversion circuit 808.

Next, the communication operation between the master and the slave according to the present embodiment when the low voltage judgment threshold value Vth- of the voltage monitoring circuit 111 fluctuates similarly to the conventional example will be described with reference to the timing chart of FIG. explain.

When the battery voltage VB changes, the master 100, the slave (1) 801 and the slave (2) 802
Output VDD of each regulator circuit 5V REG
Also changes. Here, the master 100 and the slave (1)
It is assumed that the low voltage determination thresholds Vth- of the voltage monitoring circuit 111 of the slave 801 and the slave (2) 802 are varied to 713, 714, and 715 in the same manner as in the conventional example.

As a result, only the output RES of the voltage monitoring circuit 111 of the slave (1) 801 becomes the reset signal 702
Is output. Therefore, the CPU 1 of the slave (1) 801
10 receives the transmission signals M TX2, MTX 4 from the master 100 during the processing 703 after the reset, and sets the dummy data S1 TX1 (81
1), S1 TX2 (812) is output as a reply signal.

In this case, since there is no communication error, the number of communication errors is not counted.
The CPU 110 of 00 determines that the reset processing is performed by receiving the dummy data.

Now, it is assumed that the communication line 115 between the master 100 and the slave (1) 801 is disconnected at the timing 820. In this case, transmission signals M TX6, M TX from master 100 to slave (1) 801
A reply signal cannot be output from the slave (1) 801 to the TX 8 (timings 821 and 822).
Therefore, the CPU 110 of the master 100 counts as a communication error because there is no reply from the slave (1) 801. Then, at timing 823 at which the number of communication errors occurs twice consecutively, the master 100 determines that the communication line is disconnected.

As described above, in the case of the present embodiment, when the reset processing due to the variation of the set value occurs, the dummy data is transmitted from the slave to the master, so that the reset processing is performed without counting the communication error. If it is determined that the communication line is actually disconnected and communication becomes impossible, a predetermined number of communication errors (here, two consecutive times) occur, and the communication line is immediately determined to be disconnected. Thus, the master can distinguish the occurrence of the reset process from the occurrence of the communication error due to the disconnection of the communication line, and can determine the communication error due to the disconnection of the communication line within a short time.

[Brief description of the drawings]

FIG. 1 is a system block diagram of a multiplex communication device according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a data format used in the embodiment.

FIG. 3 is a block diagram showing a configuration of a communication control circuit in the communication IC according to the embodiment.

FIG. 4 is a timing chart illustrating a communication error determination operation in the embodiment.

FIG. 5 is a system block diagram of a conventional multiplex communication device.

FIG. 6 is an explanatory diagram of a data format used in a conventional example.

FIG. 7 is a block diagram showing a configuration of a voltage monitoring circuit in a communication IC in a conventional example.

FIG. 8 is a timing chart illustrating an operation of a voltage monitoring circuit in a conventional example.

FIG. 9 is a timing chart illustrating processing after reset of a CPU in a conventional example.

FIG. 10 is an explanatory diagram showing a simulation result of a variation in a low voltage determination threshold value of a conventional voltage monitoring circuit.

FIG. 11 is a timing chart illustrating a communication error determination operation in a conventional example.

[Explanation of symbols]

 110 CPU 111 Voltage monitoring circuit 115 Communication line 800 Master 801 Slave (1) 802 Slave (2) 803 Communication control circuit 804 Communication IC 805 Normal transmission data register 806 Dummy data register 807 Selector 808 Serial-parallel conversion circuit 813 CPU I / F circuit 814 reception determination circuit 815 dummy data output permission circuit 5V REG 5V regulator circuit VB battery voltage VDD voltage RES output

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B042 GA12 JJ03 5K033 AA06 BA08 CB03 DA01 DA13 DB17 DB20 DB25 EA02 EA04 EA06 EA07 EC01 5K035 AA03 BB02 CC01 DD01 EE02 EE27 JJ05 KK01 MM03

Claims (2)

[Claims] 1. A multiplex communication apparatus comprising a Matasuo, a slave, and a communication line connecting between the master and the slave, comprising: an access performed by the master to the slave in a first communication format including data; A return access in a first communication format including data to be performed for the access, or a reset access during a reset process that does not include data to be performed when there is an access from the master during a reset process after a voltage drop from the slave. When the master cannot receive both the access in the first communication format and the access in the second communication format from a particular slave for a predetermined number of times, the master repeats the access in a predetermined cycle. To the particular slave Abnormality diagnosis method for multiplex communication system, characterized by determining the disconnection of the signal line. 2. A multiplex communication apparatus comprising a Matasu and a slave and a communication line connecting them, wherein the master and the slave monitor a reference voltage and output a reset signal when the reference voltage is lower than a predetermined value. A communication IC having a unit and a communication control unit, a CPU connected to the communication IC, and a regulator that generates the reference voltage from a power supply and provides the reference voltage to the communication IC. A normal transmission data register, a dummy data register, a selector circuit for selecting and outputting one of an output signal of the normal transmission data register and an output signal of the dummy data register, and a dummy for outputting a select signal to the selector circuit. A data output permission circuit, wherein the dummy data output permission circuit in the slave monitors the voltage The reset signal output from the unit is stored, and when the reset signal is stored, when the access from the master is received before the end of the writing of the normal transmission data from the CPU, the dummy data output enable signal is transmitted to the selector circuit. When an access from the master is received after the writing of the normal transmission data from the CPU, a normal transmission data output enable signal is output to the selector circuit. When the output signal of the data register is received, it is determined that reset processing is being performed, and when neither the output signal of the normal transmission data register nor the output signal of the dummy data register is received from a specific slave, disconnection of the communication line is determined. Multiplex communication device.