JP2001147802A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a image processor equipped with a pair of image processing circuits capable of recombining the wiring of a gate array and a control part for controlling the image processing circuits for increasing the speed of the image processing operation. SOLUTION: Each processing circuit which can be arbitrarily programmed by recombining the wiring of a gate array based on applied constitution information executes a series of operations for executing prescribed processing to picture data based on a set program by controlling the starting timing of the series of operations according to the operating state of the other image processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a copying machine, a facsimile, or a multifunction peripheral thereof.

[0002]

2. Description of the Related Art Along with recent advances in information processing technology, in recent years, a wide variety of image processing apparatuses have become widespread. Equipped with an image processing circuit that can rearrange the wiring of the gate array based on the given configuration information, and can execute various processes with the same circuit resources by rewriting the program by rearranging the wiring of the gate array Is known.

[0003]

By the way, in recent image processing techniques, it is especially important to speed up the image processing operation by the apparatus. However, in the above-described image processing apparatus, no specific study has been made on a specific control method as to what kind of control can be performed to increase the speed.

Accordingly, an object of the present invention is to provide an image processing apparatus capable of realizing a high-speed image processing operation.

[0005]

According to a first aspect of the present invention, there is provided an image processing apparatus having a pair of image processing circuits for performing predetermined processing on image data and a control unit for controlling the image processing circuits. Wherein the image processing circuit has a device which can be arbitrarily programmed by rearranging wiring of a gate array based on given configuration information. When sequentially executing the image processing based on the program setting and the program that enables the execution of the program, the program setting and the start timing of the image processing based on the program are controlled in accordance with the operation state of the other image processing circuit. It is characterized by the following.

According to a second aspect of the present invention, the control unit is configured to execute a predetermined image processing in the other image processing circuit while executing the image processing based on the program in the one image processing circuit. The program setting that enables the execution of the process is completed.

Further, in the invention according to claim 3 of the present application, the control unit executes the image processing based on the program in one image processing circuit, and executes the other image processing in the other image processing circuit. Is completed, and the other image processing circuit starts image processing based on the program.

Further, according to a fourth aspect of the present invention, a first determining means for determining a time required for a series of operations including a program setting in one of the image processing circuits and image processing based on the program. And a second determination unit for determining a time required for a series of operations including a program setting in the other image processing circuit and image processing based on the program,
The control unit compares the determination results of the first determination unit and the second determination unit and determines that a series of operations in one image processing circuit exceeds a series of operations in the other image processing circuit. In this case, the start timing of a series of operations in one image processing circuit is delayed.

Further, according to a fifth aspect of the present invention, a first determining means for determining a time required for a series of operations including a program setting in one of the image processing circuits and an image processing based on the program. And a second determination unit for determining a time required for a series of operations including a program setting in the other image processing circuit and image processing based on the program,
The control unit compares the determination results of the first determination unit and the second determination unit, and performs each of the series of operations on the image so that a difference in overall operation time between the image processing circuits is reduced. It is characterized in that it is assigned to one of the processing circuits.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Embodiment 1 FIG. FIG. 1 is a block diagram schematically showing a configuration incorporated in the image processing apparatus according to Embodiment 1 of the present invention. The image processing apparatus 10 includes a ROM 2 for recording various data, a central processing unit 3 (hereinafter referred to as a CPU) for receiving data from the ROM 2 and controlling a predetermined circuit based on the data, and a CPU 3 First and second processing for performing predetermined processing on input data
Image processing circuits 5 and 6. These first and second image processing circuits 5 and 6 are respectively connected to a CPU bus 8
Is connected to the CPU 3 via the
U3 is connected to the ROM 2 so as to receive data from the ROM 2.

The first and second image processing circuits 5, 6
Are equipped with a device capable of rearranging the wiring of the gate array based on given configuration information. In this embodiment, as such a device, a conventionally known user writable gate array 5a, 6a (so-called F
PGA (Field Programmable gate array) was used. According to the FPGAs 5a and 6a, a programmable logic module is regularly arranged, a wiring area is prepared therebetween, and a desired logic is realized by connecting the logic module and the wiring area based on configuration information. Can be. Further, in this embodiment, a plurality of circuit configuration information (hereinafter, circuit data) provided to the first and second image processing circuits 5 and 6 are stored in the ROM 2,
If necessary, one of the circuit data is read out,
The image data is transferred to the image processing circuits 5 and 6.

In the image processing apparatus 10 having such a configuration, the circuit data recorded in the ROM 2 is designated in response to a request from the CPU 3 during the image processing operation.
3 is transferred. The circuit data is transmitted from the CPU 3 to the CP
The first and second image processing circuits 5 and 6 are connected via the U bus 8
Transferred to These first and second image processing circuits 5,
6 indicates each FPGA 5 based on the transmitted circuit data.
The wiring of the gate arrays a and 6a are rearranged, and a program is set so as to execute a desired process as a part of the image processing operation. Thereby, each image processing circuit 5, 6
Now, depending on the type of circuit data,
Shading processing, scaling processing, MTF (modulation t
(ransfer function) processing and various processing such as γ (gamma) correction processing.

Further, in this embodiment, when processing image data, a program setting based on the circuit data and processing of the image data based on the program are performed between the first and second image processing circuits 5 and 6. The processing by the image processing circuits 5 and 6 can be performed efficiently by appropriately adjusting the timing of starting. FIG. 2 is a timing chart of various processes performed by the first and second image processing circuits 5 and 6. Hereinafter, a case will be described in which the first image processing circuit 5 is set to perform shading processing and scaling processing, and the second image processing circuit 6 is set to perform MTF processing and γ correction processing. . As you can see from this figure,
When processing the image data, first, the first image processing circuit 5 is set to program for shading processing (program setting time 250 ms), and the second image processing circuit 6 is set to program for MTF processing. (Program setting time 400 ms). The first
When the setting of the program for the shading process is completed, the image processing circuit 5 continuously executes the shading process on the image data (processing time 200 ms).

In the image processing apparatus 10, the first and second image processing circuits 5 and 6 can be programmed in parallel, but cannot simultaneously process image data. . Therefore, the second image processing circuit 6 waits for the completion of the shading processing in the first image processing circuit 5 and starts the MTF processing (processing time 600 ms). MT by the second image processing circuit 6
During the F processing (450 to 1,050 ms after the start of the operation), the first image processing circuit 5 is programmed for the scaling processing (program setting time: 300 ms). The “program setting time 300 ms” includes a time 150 ms for erasing the previous shading processing program before writing the scaling processing program.
Similarly, whenever a program is shuffled,
This includes 150 ms for erasing the previous program.

When the MTF processing by the second image processing circuit 6 is completed, the first image processing circuit 5 starts scaling processing (processing time 400 ms). During the scaling processing by the first image processing circuit 5 (1050 to 1050 after the operation starts)
At 1450 ms), the second image processing circuit 6 is programmed for γ correction processing (program setting time 200 ms). When the scaling process by the first image processing circuit 5 is completed, the second image processing circuit 6
The correction processing is started (processing time 100 ms).

As described above, the image having the first and second image processing circuits 5 and 6 capable of executing various processes by rearranging the wiring of the gate arrays of the FPGAs 5a and 6a based on the given circuit data. In the processing device 10, when processing image data, the first and second image processing circuits 5 and 6 appropriately adjust the program setting and the timing of starting the processing of the image data based on the program. Operation stop time can be reduced, and processing on image data can be performed efficiently in a relatively short time. As a result, the image processing operation in the image processing device 10 can be speeded up.

Hereinafter, another embodiment of the present invention will be described. In the following description, the same components as those in the first embodiment described above are denoted by the same reference numerals, and further description is omitted. Embodiment 2 FIG. FIG. 3 is a timing chart of various processes by the first and second image processing circuits incorporated in the image processing device according to Embodiment 2 of the present invention. This image processing apparatus has the same configuration as that of the first embodiment. In the second embodiment, the first and second image processing circuits 5 and 6 are programmed and set in parallel. In addition, image data can be processed simultaneously. As can be seen from the figure, when processing the image data,
First, the first image processing circuit 5 is programmed for shading processing (program setting time 250 ms), and the second image processing circuit 6 is programmed for MTF processing (program setting time 40).
0 ms).

After the first image processing circuit 5 is programmed for shading processing, the first image processing circuit 5 continuously performs shading processing on the image data (processing time 200 ms). The setting of the MTF processing program in the second image processing circuit 6 is completed. In this embodiment, since the first and second image processing circuits 5 and 6 can process image data in parallel, the second image processing circuit 6 continuously executes the MTF processing on the image data. (Processing time 600 ms).

After that, the MT by the second image processing circuit 6
When the shading processing by the first image processing circuit 5 is completed during the F processing, the first image processing circuit 5 is subsequently programmed for the scaling processing (program setting time 300 ms). This first image processing circuit 5
Is completed, the first image processing circuit 5 further executes a scaling process on the image data (processing time 400 m).
s). When the MTF processing by the second image processing circuit 6 is completed during the scaling processing by the first image processing circuit 5, the second image processing circuit 6 is subsequently programmed for the γ correction processing. (Program setting time 200m
s).

During the setting of the program for the γ correction processing in the second image processing circuit 6, the magnification change processing by the first image processing circuit 5 is completed. Further, when the setting of the program for the γ correction processing in the second image processing circuit 6 is completed, the γ correction processing for the image data is subsequently performed in the second image processing circuit 6 (processing time 100 ms).

As described above, when processing the image data, the program setting in the first and second image processing circuits 5 and 6 and the timing of starting the processing of the image data based on the program are appropriately adjusted. In addition, the stop time of the image processing operation can be reduced, and the processing on the image data can be performed efficiently in a relatively short time. As a result, the image processing operation in the image processing device can be speeded up.

Embodiment 3 FIG. FIG. 4 is a block diagram conceptually showing a configuration of a CPU incorporated in an image processing apparatus according to Embodiment 3 of the present invention. In the third embodiment, the CPU 3 has a control unit 3A that controls a predetermined circuit based on data supplied from the ROM 2,
A first determination unit 3B that determines a time required for a series of operations including a program setting in the first image processing circuit 5 and processing of image data based on the program;
And a second determination unit 3C that determines a time required for a series of operations including a program setting in the image processing circuit 6 and processing of image data based on the program. The first and second determination units 3B and 3C can calculate in advance the time required for a series of operations consisting of setting each program and processing based on the program when processing the image data.

In the CPU 3 having such a configuration, the control section 3A compares the determination results obtained by the first and second determination sections 3B and 3C, and in this comparison, a series of operations in one image processing circuit is performed. If it is determined that the operation overtakes the series of operations in the other image processing circuit, the start timing of the series of operations in one image processing circuit is delayed. In order to control the first and second image processing circuits 5 and 6 in a series of operation units, a write address and a read address to a memory (not shown) for storing data by the CPU 3 are stored. Can be dealt with by monitoring.

FIG. 5 is a timing chart of various processes by the first and second image processing circuits incorporated in the image processing apparatus according to the third embodiment. First, while the first image processing circuit 5 is programmed for shading processing (program setting time 250 ms),
The second image processing circuit 6 is programmed for MTF processing (program setting time 600 ms). When the setting of the program for shading processing in the first image processing circuit 5 is completed, the first image processing circuit 5
Then, shading processing is performed on the image data (processing time 200 ms).

The MTF in the second image processing circuit 6
When the processing program setting is completed, the second
In the image processing circuit 6, the MTF processing is performed on the image data (processing time 800 ms). In this case, the second
The time required for a series of operations including setting of a program for MTF processing in the image processing circuit 6 and processing based on the program is 1400 ms (= program time
00 ms + processing time 800 ms). Also, on the other hand,
In the first image processing circuit 5, the time required for a series of operations including the setting of the program for the scaling process and the process based on the program, which is performed after the shading process, is 700 ms (= program time 300 ms + processing time 400 ms). Yes, if this operation is started immediately after the shading process (after 450 ms), the scaling process is completed after 1150 ms. That is, the first
The magnification processing by the image processing circuit 5 overtakes the MTF processing by the second image processing circuit 6,
G.

In order to avoid such NG, in this embodiment, the start timing is delayed so that the scaling process by the first image processing circuit 5 does not overtake the MTF process by the second image processing circuit 6. Let me do. As a result,
The scaling process by the first image processing circuit 5 is completed after the completion of the MTF process by the second image processing circuit 6.
In this case, when it is determined that a series of operations by the first image processing circuit 5 exceeds a series of operations by the second image processing circuit 6, the clock signal supplied to the CPU 3 is stopped for a predetermined period. Then, the instruction to the first image processing circuit 5 is interrupted. After a predetermined period, when the supply of the clock signal is restarted, a series of operations in the first image processing circuit 5 is started. As a result, the start timing of a series of operations in the first image processing circuit 5 is delayed.

When the MTF processing by the second image processing circuit 6 is completed, the second image processing circuit 6 is program-set for γ correction processing (program setting time 200 ms). Note that during the program setting, the scaling process by the first image processing circuit 5 is completed. Second
After the setting of the program for the γ correction process in the image processing circuit 6 is completed, the second image processing circuit 6 continuously executes the γ correction process on the image data (processing time 100 ms).

As described above, in the third embodiment, the time required for a series of operations is compared between the first and second image processing circuits 5 and 6, and then the time required for one of the image processing circuits is compared. If it is determined that the series of operations overtake the series of operations in the other image processing circuit, the start timing of the series of operations in one image processing circuit is delayed,
This can be avoided.

Embodiment 4 FIG. 6 shows a timing chart of various processes by the first and second image processing circuits incorporated in the image processing device according to Embodiment 4 of the present invention. This image processing apparatus has the same configuration as that of the above-described third embodiment. In the fourth embodiment, the time required for a series of operations including each program setting and processing based on the program is set in advance. The calculation and the processing requiring substantially the same operation time are performed in parallel.

As can be seen from the figure, first, the first image processing circuit 5 is programmed for shading processing (program setting time 250 ms), and the second image processing circuit 6 is programmed for MTF processing. (Program setting time 200 ms). When the program setting for the shading process in the first image processing circuit 5 is completed, the first image processing circuit 5 executes the shading process on the image data (processing time 20).
0 ms). On the other hand, the MTF in the second image processing circuit 6
When the setting of the processing program is completed, the second image processing circuit 6 executes the MTF processing on the image data (processing time 250 ms). The shading processing in the first image processing circuit 5 and the MTF processing in the second image processing circuit 6 end at the same time when 450 ms has elapsed.

Thereafter, subsequently, the first image processing circuit 5 is set for the program for the scaling process (program setting time 300 ms), and the second image processing circuit 6 is set for the γ correction process. (Program setting time 400 ms). When the setting of the program for the scaling process in the first image processing circuit 5 is completed, the first image processing circuit 5 executes the scaling process on the image data (processing time 400 ms). On the other hand, when the program setting for the γ correction processing in the second image processing circuit 6 is completed, the second
In the image processing circuit 6, a gamma correction process is performed on the image data (processing time 300 ms). The scaling processing in the first image processing circuit 5 and the γ correction processing in the second image processing circuit 6 end at the same time when 1150 ms has elapsed.

As described above, the time required for a series of operations including the program setting and the processing based on the program in the first and second image processing circuits 5 and 6 is calculated in advance, and substantially the same operation time is required. By performing the processing in parallel, the first and second image processing circuits 5 and 6 can reduce their processing waiting time, can operate efficiently in a relatively short time, and can speed up the image processing operation. Can be realized. In this case, in order to perform processes requiring substantially the same operation time in parallel, the first and second image processing circuits 5 and 5
In 6, the order of the assigned processes may be changed.

The present invention is not limited to the illustrated embodiment, and it goes without saying that various improvements and design changes can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, shading processing, MTF processing, and MTF processing are described as specific examples of the processing executed by the first and second image processing circuits.
Although the scaling process and the γ correction process have been described, the present invention is not limited to these processes. Also, the programming time and the processing time for each process are not limited to the numerical values described above, and arbitrarily set numerical values may be used.

[0034]

As is apparent from the above description, according to the first aspect of the present invention, a program setting that enables each image processing circuit to execute a predetermined process and image processing based on the program are performed. Are sequentially executed, the start timing of the image processing is controlled based on the program setting and the program setting according to the operation state of the other image processing circuit. While the predetermined processing is being performed on the other image processing, the other image processing circuit is programmed so that the stop time of the processing operation in the image processing circuit can be reduced. It can be performed efficiently in a short time. As a result, the image processing operation in the image processing device can be speeded up.

According to the second aspect of the present invention, while one image processing circuit is executing image processing based on a program, the other image processing circuit executes predetermined processing. By completing the setting of the program to be enabled, the processing of the image data can be efficiently performed between the pair of image processing circuits in a relatively short time. As a result, the image processing operation in the image processing device can be speeded up.

Further, according to the third aspect of the present invention, while one image processing circuit is executing a process based on a program, the other image processing circuit is executing another predetermined process. Complete the setting of the program to be executable, and then, in the other image processing circuit, to start the processing based on the program,
Processing of image data can be efficiently performed in a relatively short time between a pair of image processing circuits. As a result, the image processing operation in the image processing device can be speeded up.

Further, according to the invention of claim 4 of the present application, each of the first image processing circuits determines the time required for a series of operations consisting of program setting and image processing based on the program. Determining means;
A second determining means for determining a time required for a series of operations including a program setting and an image processing based on the program in the other image processing circuit, wherein the first determining means and the second determining means As a result of comparing the determination results of above, a series of operations in one image processing circuit,
When it is determined that a series of operations in the other image processing circuit is overtaken, the start timing of the series of operations in the one image processing circuit can be delayed to avoid this.

Further, according to the invention of claim 5 of the present application, each of the first image processing circuits determines the time required for a series of operations consisting of program setting and image processing based on the program. Determining means;
A second determining means for determining a time required for a series of operations including a program setting and an image processing based on the program in the other image processing circuit, wherein the first determining means and the second determining means In order to distribute the series of operations to any of the above-described image processing circuits so that the difference in the overall operation time between the image processing circuits is reduced, the processing on the image data is performed in a relatively short time. Can be performed efficiently. As a result, the image processing operation in the image processing device can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram conceptually showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart of various processes performed by first and second image processing circuits incorporated in the image processing apparatus.

FIG. 3 is a timing chart of various processes by first and second image processing circuits incorporated in an image processing apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram conceptually showing a configuration of a CPU incorporated in an image processing apparatus according to Embodiment 3 of the present invention.

FIG. 5 is a timing chart of various processes performed by first and second image processing circuits incorporated in the image processing apparatus according to the third embodiment.

FIG. 6 is a timing chart of various types of processing performed by first and second image processing circuits incorporated in an image processing apparatus according to Embodiment 4 of the present invention.

[Explanation of symbols]

 2 ROM 3 CPU 3A Controller 3B First judging unit 3C Second judging unit 5 First image processing circuit 6 Second image processing circuit 10 Image processing device

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Nobuo 2-3-13 Azuchicho, Chuo-ku, Osaka-shi, Osaka Inside Osaka International Building Minolta Co., Ltd. (72) Inventor Hiroyuki Suzuki Azuchi-cho, Chuo-ku, Osaka-shi, Osaka 2-3-1-3 Osaka International Building Minolta Co., Ltd. (72) Inventor Hideyuki Toriyama 2-3-1-13 Azuchicho, Chuo-ku, Osaka-shi, Osaka F-term in Osaka International Building Minolta Co., Ltd. 5B013 DD01 5B076 EA17 5C062 AB40 AF06 BA00 BA04

Claims (5)

[Claims] 1. An image processing apparatus comprising: a pair of image processing circuits for performing predetermined processing on image data; and a control unit for controlling the image processing circuits, wherein the image processing circuits have a given configuration. The device has a device that can be arbitrarily programmed by rearranging the wiring of the gate array based on the information. An image processing apparatus for sequentially executing image processing, wherein the program setting and the start timing of image processing based on the program are controlled in accordance with the operation state of the other image processing circuit. 2. The computer according to claim 1, wherein the control unit is configured to execute another predetermined process in the other image processing circuit while executing the image processing based on the program in the one image processing circuit. The image processing apparatus according to claim 1, wherein the setting is completed. 3. A program that enables one of the image processing circuits to execute another predetermined process while the other image processing circuit executes an image process based on the program. 2. The image processing device according to claim 1, wherein the setting is completed, and the other image processing circuit starts image processing based on the program.
An image processing apparatus as described in the above. 4. A first determining means for respectively determining a time required for a series of operations including a program setting in one image processing circuit and image processing based on the program, and a program setting in the other image processing circuit and the same. A second determination unit for determining a time required for a series of operations including image processing based on a program, wherein the control unit determines a determination result of the first determination unit and the second determination unit. When it is determined that a series of operations in one image processing circuit exceeds a series of operations in the other image processing circuit, the start timing of the series of operations in one image processing circuit is delayed. The image processing apparatus according to claim 1, wherein: 5. A first determining means for respectively determining a program setting in one image processing circuit and a time required for a series of operations consisting of image processing based on the program, and a program setting in the other image processing circuit and the same. A second determination unit for determining a time required for a series of operations including image processing based on a program, wherein the control unit determines a determination result of the first determination unit and the second determination unit. 2. An image processing apparatus according to claim 1, wherein said series of operations are assigned to one of the image processing circuits so that a difference in overall operation time between the image processing circuits is reduced.