JP3022848B2 - Multitask task switching method and real-time operating system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real-time operating system (hereinafter referred to as "real-time OS"), and more particularly, to a technique for task switching of a time-division real-time OS.

[0002]

2. Description of the Related Art A real-time OS includes a subroutine call called a system call for processing activation and termination of a task requested by a user program, and a real-time OS itself called a kernel switches tasks independently of the user program. It is mainly used as the OS of a microprocessor incorporated in control, communication, peripheral devices, etc., while a man-machine interface is emphasized in a general OS, whereas a real-time OS The emphasis is on execution speed over man-machine interface.

In some peripheral devices controlled by a microprocessor, status information is stored in a control register assigned to a fixed address of a memory. Of these peripheral devices, after the status information stored in the allocated control register is once saved to another memory address, when the saved information is returned to the original control register again, the state before the save is restored. A peripheral device that can operate back is defined as time-sharing enabled hardware. Typical examples of such hardware include:
There is a flash memory used for a silicon disk or the like which is one of external auxiliary storage devices.

FIG. 8 is a flowchart of task switching by the above-described conventional typical time-division real-time OS.

First, a timer interrupt for task switching is generated (step S1), the dynamic variables used by the current task are saved (step S2), the address of the current task is saved (S3), and the task is switched. The next task is selected, the execution time of the task is set (S4), the dynamic variables used by the selected task are restored (S5), and the return address of the selected task is set in the stack ( S
6), returning from the timer interrupt (S7).

For example, the "stack pointer management method" disclosed in Japanese Unexamined Patent Publication No. Hei 3-201138 keeps real-time performance in multiple interrupt processing and greatly increases a spare stack area for interrupt processing provided in the stack area of each task. In addition to the stack area for each task, an "interrupt processing stack area" and a "stack pointer storage work area" are provided for the purpose of reducing the number of tasks. First, it is determined whether or not the stack pointer has been switched to the interrupt processing stack area when an interrupt from the task occurs (1). If it is determined that the stack pointer has not been switched yet, a temporary work area is added to the stack area of the task. Then, the contents of the save work area are moved to it, and the contents of the stack pointer of the task are also saved in the save work area (2). Then, the contents of the stack pointer are switched for the interrupt processing stack area. It discloses that interrupt processing is performed (3), and after the interrupt processing is completed, the contents of the stack pointer are returned to the contents previously saved in the save work area (4) and the task is executed.

The "multitask processing device" disclosed in Japanese Patent Application Laid-Open Nos. 7-141208 and 7-210400 discloses a dispatch processing time at the time of task switching in multitask processing, that is, a task issues a processing request. For the purpose of shortening the time from when the context is saved and the execution right is given to the execution right after execution, a plurality of register banks occupied for each task, and It is disclosed that a vacant waiting means is provided, and these plurality of register banks are dynamically allocated to each task.

[0008]

However, in the conventional time-division real-time OS, the memory address allocated to the control register is fixed, which is different from the variable used in the program. Only the saving and restoring of the dynamic variables used by each task and the execution address management of each address are performed at the time of switching, so peripheral devices such as flash memory that can be used in a time-sharing manner In other words, there was a problem that the software on the task side had to be changed.

When a time-sharing real-time OS is used,
For example, if the memory address register of the flash memory is used as a variable in the user's program, the memory address register of the flash memory becomes common, so if the memory processing periods of multiple tasks overlap, There is a problem that data cannot be written to a predetermined flash memory.

Conventionally, in order to avoid this problem, a memory area for storing a memory address managed by each task is prepared, and 1 is added to this memory area immediately before writing to the flash memory, and the memory address of the flash memory is added. After the data was stored in the register, data writing to the flash memory was started (see FIG. 9).

Therefore, in order to improve the throughput by multitasking, it is necessary to change all the existing programs of each task created for sequential processing in this way to enable parallel processing. .

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a real-time OS capable of easily creating a program on the task side accompanying the multiprocessing and reducing man-hours.

[0013]

According to the present invention, a real-time O
S saves and restores dynamic variables used by each task
Means, execution address management means for each task, and running
Time-sharing available hardware used by other tasks
Means for saving and restoring information in the kernel
In a real-time operating system,
Hardware information is time-shared hardware
Address of the memory address register of the flash memory
Address information and data information stored in the flash memory.
Information, and flash memory operating status information.
And stored in a control register.

The kernel part of the real-time OS according to the present invention includes “means for saving and restoring dynamic variables used by each task” and “means for managing the execution address of each task” as in the conventional case. And means for storing and saving “time-division usable hardware information” used by the running task. And turn off multitasking
A timer interrupt for task switching
Dynamic variables used by the current task
Saves the address of the line task and saves the address used by the current task.
Saves flash memory information and sets execution time
To select the next task to execute and execute the current task.
Switches to the execution of the selected task, and the selected task
Restore the used dynamic variables from the save destination and
Set the return address on the stack and start from the timer interrupt.
Return.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a time-division real-time OS according to the present invention.
FIG. 2 is a flowchart of one embodiment of the task switching method of FIG.
FIG. 3 is a diagram showing memory allocation of control registers, and FIG. 4 is a diagram showing transition of an internal memory during multitask processing.

As shown in FIG. 2, the system according to the present embodiment includes a program memory 2 for storing a sequence program having a plurality of tasks, a system memory 3 for storing a system program, a control register 11 and an internal memory. And a peripheral device 4 including a flash memory 41 for executing a sequence program under the control of a system program. The real-time OS including the kernel portion is loaded from the system memory into the central processing unit 1, drives the peripheral device 4 using the control register 11, and executes the sequence program while switching tasks. Note that the control register
Reference numeral 11 denotes a flash memory at address 100 as shown in FIG.
Memory memory address register, flash memory at address 101
Memory data contents register, writing to address 102
Flash memory with lag and write request flag
Are respectively assigned.

The operation at the time of task switching will be described with reference to FIG.

First, a timer interrupt for task switching is generated (step S1), and the dynamic variables used by the current task are saved (step S2). Possible hardware information is saved (S25), and the address of the current task is saved (S25).
3) Selecting the task to be switched and setting the execution time of the task (S4), restoring the dynamic variables used by the selected task (S5), and using the time-sharing used by the selected task Restore available hardware information (S5
5) The return address of the selected task is set in the stack (S6), and the process returns from the timer interrupt (S7).

That is, when the execution task is switched at an arbitrary time, the stack information of the execution task and the shared hardware information used by the execution task that can be used in a time-sharing manner are saved, and the next task is stored before. The stack information that was used and the shared hardware information that can be used in a time-sharing manner used by the next task are returned to the original state, and the activation of the next task is instructed.

For example, in a section where the processing times of the flash memories which are the shared hardware of the task A and the task B overlap, when the task A is activated,
Memory address register of memory (10 of control register 11)
The memory address of the flash memory for task A is stored in address (0), and the memory address of the flash memory for task B is stored in the internal memory 12 managed by the real-time OS.

On the other hand, when the task B is activated in the same overlapping section, contrary to the activation of the task A, the memory address for the task B is stored in the memory address register of the flash memory. Reference numeral 12 stores a memory address of the flash memory for the task A.

Similarly, in the section where the processing times of task B and task C overlap, when task B is running, the memory address for task B is stored in the memory address register of the flash memory, and the internal memory 12 stores the memory address of the flash memory for the task C. When the task C is activated, the memory address for the task C is stored in the memory address register of the flash memory. Is the memory address of the flash memory for task B.

Therefore, the information on the shared hardware that can be used in a time-sharing manner is managed collectively, so that the program capacity is smaller and the program creation becomes easier as compared with the case where each task is managed individually. .

As a specific example of such a real-time OS, continuous photographing by a digital still camera,
That is, the case of controlling the continuous shooting function will be described.

For shooting with a digital still camera,
As shown in FIG. 5, it is necessary to sequentially perform two processes of a process of capturing and compressing video data for each shooting and a process of writing the compressed data to a flash memory. In the processing of
One series of processing each time is regarded as one task.

In the case of the conventional continuous shooting, as shown in FIG.
After completing the writing process for the first shot, the video capture compression process for the next second shot was started, and each task was processed sequentially.

However, when the speed of continuous shooting is required, as shown in FIG. 6, when the first data fetching compression process is completed, the process of writing the first compressed data to the memory is started. At the same time, it is necessary to start the second data fetch / compression process and process the two tasks in an overlapping manner, and a multitask switching process is performed by a time-division real-time OS.

The processing of writing compressed data to the flash memory in each task will be described with reference to FIGS.

On the memory of the microprocessor 1, as a control register 11 relating to the flash memory 41, a "memory address register of flash memory" 100 indicating the memory address of the flash memory instructing the operation.
The address, a "flash memory data content register" 101 storing the content to be written to the specified memory, and a "flash memory status register" 102 storing the flash memory write status are stored. Assigned. The "flash memory status register" 102 has a "writing flag" indicating that the flash memory is being written, and a "write request flag" for requesting the flash memory to write.

As shown in FIG. 7, when the user program tries to start writing compressed data to the flash memory, the user program first looks at the writing flag of the status register at address 102, and the previous writing ends. It is determined whether or not the data has been written (step S11). If the previous writing has been completed, 1 is added to the content of the memory address register 100 to specify the write destination address of the compressed data (step S12). The contents of the compressed data are stored in the address 101 (step S13), the write request flag in the status register 102 of the flash memory is set, writing to the flash memory 41 is started, and the writing flag is set during writing. (Step S1
4).

In this example of the program, the memory address register of the flash memory is used as a variable. However, if a time-division real-time OS is used, the "memory address register of the flash memory" 100 of this control register is assigned to each task. When the memory write processing periods of the two tasks overlap as shown in section 1 and section 2 in FIG. 6, compressed data cannot be written to a predetermined flash memory. The problem described above occurs.

Conventionally, in order to avoid this problem, a memory area for storing a memory address managed by each task is prepared, and 1 is added to this memory area as shown in FIG. 9 (steps S21 and S22). Immediately before writing to the flash memory, the data is stored in the memory address register of the flash memory and then data writing to the flash memory is started. Therefore, all programs that perform such parallel processing of tasks have to be changed.

However, according to the present invention, by setting the "memory address register of the flash memo" as hardware information that can be used in a time-division manner, every time a task is switched, the "flash memory" of the task and the stack information of the task to be executed are updated. The memo memory address register is also saved,
When the next task is started, the stack information of the next task and the “memory address register of the flash memo” are restored. Therefore, during the period 1 in FIG. 6 in which the data write processing of task 1 and task 2 overlap, when task 1 is activated and the first sheet is written, the memory address register 100 of the flash memory is used. The address stores the memory address of the flash memory for task 1, and the internal memory 12 managed by the real-time OS stores the memory address of the flash memory for task 2, which is the second write. Is stored.

On the other hand, task 2 is started in the same section 1 and 2
When the first page is being written, the memory address for the task 2 is stored in the memory address register of the flash memory, and the flash memory for the task 1 is stored in the internal memory 12, as opposed to when the task 1 is started. Are respectively stored.

Similarly, in the section 2 where the writing of the second sheet and the writing of the third sheet are overlapped, when the task 2 is activated, the memory address for the task 2 is stored in the memory address register of the flash memory. The memory address of the flash memory for task 3 is stored in the memory 12.
Is activated, the memory address for task 3 is stored in the memory address register of the flash memory, and the memory address of the flash memory for task 2 is stored in the internal memory.

Therefore, since the information of the flash memory is collectively managed by the internal memory 12 managed by the real-time OS, the program capacity can be reduced as compared with the case where each task is individually managed.
Program creation becomes easy.

[0038]

As described above, the present invention provides a hardware
Flash is hardware that can be used in a time-sharing manner for information
・ Address information and flash memory address register
Information stored in flash memory and flash
・ Stored in the control register including the operation status information of the memory
And, man-hours and saving and restoring division available hardware information when each task is using by performing the kernel portion of the real-time OS, and the prepared program changes accompanying tasks side multiprocessing of There is an effect that can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of one embodiment of a task switching method of a time-division real-time OS according to the present invention.

FIG. 2 is a system configuration diagram of the embodiment of FIG.

FIG. 3 is a diagram illustrating a flash memory of an embedded microprocessor.
FIG. 6 is a diagram showing one embodiment of memory allocation of a memory and a control register.

FIG. 4 is an operation example of a memory managed by a real-time OS.

FIG. 5 is a sequence diagram of continuous shooting by a digital still camera.

FIG. 6 is a sequence diagram of continuous shooting of a digital still camera to which a time-division real-time OS is applied.

FIG. 7 is a flowchart illustrating an example of a process of writing compressed data to a flash memory;

FIG. 8 is a flowchart of task switching by a conventional time-division real-time OS.

FIG. 9 is a flowchart of a process of writing compressed data to a flash memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Program memory 3 System memory 4 Peripheral device 11 Control register 12 Internal memory 41 Flash memory S1-S55 Step

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-111032 (JP, A) JP-A-51-114839 (JP, A) JP-A-7-284063 (JP, A) JP-A-6-110 86203 (JP, A) JP-A-8-125957 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/46 G06F 9/30 G06F 13/10 G06F 13/12 G06F 12/02 G06F 12/00 G06F 12/06 G06F 15/78 G06F 3/06 G06F 3/08 G06T 1/60 H04N 5/781 H04N 5/907 G06K 17/00 G06K 19/00

Claims (5)

(57) [Claims] A program memory for storing a sequence program having a plurality of tasks; a system memory for storing a real-time operating system including a kernel portion; a control register and an internal memory therein; A central processing unit for executing the sequence program under the control of the system program; and a peripheral device including a flash memory, wherein the real-time operating system drives the peripheral device using the control register. In a real-time operating system for executing the sequence program while switching tasks, address information of a memory address register of a flash memory corresponding to a task being started, data stored in the flash memory Information and operation status information of the flash memory are stored in the control register, and address information of a memory address register of the flash memory corresponding to a task that is not running is stored in the internal memory. operating system. 2. The real-time operating system according to claim 1, wherein the operation state information of the flash memory includes a writing flag and a writing request flag.
system. 3. The real-time operating system according to claim 1, wherein the address information of the memory address register, the data information, and the operation state information are stored in respective registers at consecutive address addresses of the control register. system. 4. The address information, the data information, and the operation state information of the memory address register are stored in a memory address register, a data content register, and a state register at consecutive address addresses of the control register, respectively. 2. The real-time operating system according to claim 1, wherein the status register includes a writing flag and a write request flag. 5. A method of writing to the flash memory, comprising the steps of: detecting the turning-off of the writing flag; and setting the flash address specified by the memory address register.
A predetermined number is added to the address of the
Write Mbeki the over data the flash memory of the address number
Specifying a location, storing the content to be written to the flash memory in the data content register, setting the write request flag, and starting writing to the flash memory;
5. The real-time operating system according to claim 4, comprising a step of terminating writing to said flash memory.