JP2001141789A - Semiconductor and good/defective product identification device for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of the test time even if the number of chips on a wafer increases, differently from a conventional method of testing the chips on the wafer one by one and marking the chips to identify good/defective products or storing information about the good/defective products. SOLUTION: In this semiconductor, the test of chip itself is carried out inside the chip, and by changing the temperature of a part of the chip or the whole chip according, the test result is made recognizable from the outside of the chip as the temperature change. By capturing the temperature changes of the chips, the good/defective products are identified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor non-defective / defective determining method used for data processing, control of various devices, and the like.

[0002]

2. Description of the Related Art An example of a conventional method for determining a non-defective / defective semiconductor in a wafer state will be described with reference to the drawings. FIG. 5 shows the semiconductor in a wafer state.

In FIG. 5, (5.0) is a wafer.
(5.1) is the chip 1 on the wafer. (5.2) is a chip 2 on the wafer. (5.3) is a chip 3 on the wafer. (5.4) is a chip 4 on the wafer. (5.5) is a chip 5 on the wafer. (5.6) is the chip 6 on the wafer
It is.

[0004] All chips on the wafer have the same function, and chips 1 (5.1) to 6 (5.6) all have the same function. Some of the chips on the wafer are good and some are defective. On the wafer, the chip is
It is spread like a.

FIG. 6 shows a chip 1 (5.1) on a wafer (5.0),
Chip 2 (5.2), chip 5 (5.5), and chip 6 (5.6) are enlarged. (6.1) is the chip 1 (5.1) in FIG.
(6.2) is chip 2 (5.2) in FIG. (6.3) is the chip of Fig. 5.
5 (5.5). (6.4) is the chip 6 (5.6) in FIG. (6.
1.1) is one of a plurality of PADs, and exchanges signals with the outside of the chip 1 (6.1). (6.2.1) is one of a plurality of PADs, and exchanges signals with the outside of the chip 2 (6.2).
(6.3.1) is one of the multiple PADs, chip 3 (6.3)
Exchange signals with the outside world. (6.4.1) is one of a plurality of PADs, and exchanges signals with the outside of the chip 4 (6.4). (6.5) is a scribe lane, which is an area provided between chips, and cuts (cuts) this area to separate each chip.

[0006] Each chip on the wafer state shown in FIG.
The defective product is determined as follows.

A probe is applied to the pad of chip 1 (5.1) on the wafer. Assuming that the chip shown in FIGS. 5 and 6 has 24 pads and all the chips are required for the inspection, 24 probes are respectively applied to the corresponding pads. A test input signal is input to the chip 1 (5.1) from the LSI tester via the probe. The output of chip 1 (5.1) obtained through the probe is compared with an expected value by an LSI tester. If the output of the chip 1 (5.1) is in accordance with the expected value, it is determined to be a good product. If the chip 1 (5.1) is defective, the chip 1 (5.1) is marked with ink so that the chip 1 (5.1) can be distinguished from a non-defective product, or the information of the non-defective / defective product is stored in the LSI tester. When the inspection of the chip 1 (5.1) is completed, a probe is applied to the chip 2 (5.2) to perform a test in the same manner as the chip 1 (5.1).

FIG. 4 is a flowchart of a conventional method for determining a good / defective semiconductor in a wafer state. A probe is applied to the chip to be tested, and the chip is tested. According to the judgment result of the test, the chip subjected to the test is marked, or the judgment information is stored in the LSI tester. Then, a probe is applied to the next chip to perform a similar test. In this way, all the chips are inspected.

[0009]

In the conventional non-defective / defective judgment method, the number of chips that can be judged to be non-defective / defective in one test is limited by the limitation of the number of probes, the limit of the LSI tester, and the like. One or several as described above. Therefore, as the number of chips on the wafer increases, the inspection time increases.

[0010]

In order to solve this problem, the present invention performs a test of itself within a chip, and changes the temperature of a part or the whole of the chip according to the test result, thereby obtaining the test result. Proposed a non-defective / defective product identification device characterized by the fact that it can be known from the outside of the chip as a change in the temperature, and a non-defective / defective product is identified by capturing the temperature change of this semiconductor. I do.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a chip on a wafer according to an embodiment of the present invention. (2.1) is a test terminal VDD, which is connected to the VDD terminals of all chips on the wafer to
Supply. (2.2) is a test terminal OSC, which is connected to the OSC terminals of all chips on the wafer and supplies the clock OSC to all chips. (2.3) is a test terminal RST, which is connected to the RST terminals of all chips on the wafer,
A reset signal RST is supplied to all chips. (2.4) is the test terminal VSS, which is the VSS of all the chips on the wafer.
Connect to the terminal to supply the ground potential VSS to all chips. (2.5) is a test terminal TST, which is connected to the TST terminals of all chips on the wafer and makes this signal valid to notify all chips of the test mode. (2.6) is the chip 1 on the wafer shown in FIG.
(2.7) is a chip 2 on the wafer shown in FIG. (2.
8) is a chip 5 on the wafer shown in FIG. (2.9) is the chip 6 on the wafer shown in FIG. (2.10) is a test wiring formed on the scribe lane on the wafer, and is composed of VDD wiring, OSC wiring, RST wiring, VSS wiring, and TST wiring.

FIG. 3 shows a block diagram of a chip. (3.0)
Are chips, and all the chips on the wafer have the same configuration. (3.1) is a VDD pad, which is connected to the VDD terminal (2.1) on the wafer. (3.2) is the OSC pad and the OSC terminal (2.
Connect to 2) on the wafer. (3.3) is the RST pad,
Connect to the RST terminal (2.3) on the wafer. (3.4) is a VSS pad, which is connected to the VSS terminal (2.4) on the wafer. (3.
5) is a TST pad, which is connected to the TST terminal (2.5) on the wafer. (3.6) is a test ROM, which stores the procedure when the chip (3.0) performs a self-test. (3.7)
Is a chip (3.0) CPU. (3.8) is the peripheral circuit 1,
The peripheral circuit of the chip (3.0) is made. (3.9) is a peripheral circuit 2 in which a peripheral circuit of the chip (3.0) is formed.

FIG. 8 (8.1) shows a chip 1 (2.
6), a chip 2 (2.7), a chip 5 (2.8), a chip 6 (2.9) and a test wiring (2.10) on a wafer. The pattern shown in FIG. 2 is formed on the wafer by laying the pattern on the wafer using the mask of (8.1).

FIG. 9 shows a non-defective / defective product determination device (9.0) according to the present embodiment. (9.1) is a temperature state reading means for reading the temperature state of the wafer (9.9) using a temperature measuring device using infrared rays. (9.2) is an initial temperature state storage means for storing the temperature state of the wafer (9.9) before the test read by the temperature state reading means (9.1). (9.
3) is a judgment temperature state storage means, the wafer (9.9) under test result judgment read by the temperature state reading means (9.1)
Is stored. (9.4) is a temperature difference calculating means for performing an operation between data stored in the initial temperature state storing means (9.2) and the judgment temperature state storing means (9.3) to calculate a temperature difference between the initial state and the judgment state. . (9.5) is wafer map information, in which arrangement information of chips (3.0) on the wafer (9.9) is stored. (9.6) is a temperature difference information / wafer map information calculation means, which outputs the temperature information of the initial state and the judgment state of the wafer and the chip arrangement information of the wafer map information (9.5) output by the temperature difference calculation means (9.4). By superimposing, it is determined which chip is good or defective. (9.7) is non-defective / defective information output from the temperature difference information / wafer map information calculating means (9.6). (9.8) is a test signal applying means for wafer (9.9), VDD terminal (2.1), OSC terminal (2.2), RST terminal (2.3), VSS
Supply the signals required for the test to the terminal (2.4) and the TST terminal (2.5).

FIG. 1 is a test flow according to the embodiment of the present invention.

First, a semiconductor in a wafer state to be tested is set in a non-defective / defective discriminating apparatus (9.0), a temperature state in an initial state is measured by a temperature state reading means (9.1), and an initial temperature state storing means (9.2) is measured. ). Next, the test terminal, VDD terminal (2.1), O
SC terminal (2.2), RST terminal (2.3), VSS terminal (2.4), TST terminal
Apply probe to (2.5), supply voltage to VDD terminal (2.1), clock to OSC terminal (2.2), reset signal to RST terminal (2.3), ground potential to VSS terminal (2.4). , TST terminal
In (2.5), a signal indicating the test mode is applied.

The chip shown in FIG. 3 in which signals necessary for conducting a test are input to the VDD pad (3.1), the OSC pad (3.2), the RST pad (3.3), the VSS pad (3.4), and the TST pad (3.5). In (3.0), the CPU (3.7) reads out the procedure when the chip (3.0) performs the self-test from the test ROM (3.6), and reads the procedure of the CPU (3.7) itself, the peripheral circuit 1 (3.8), and the peripheral circuit 2 (3.9). ) Test.

If the self-test determines that the CPU (3.7) is non-defective, processing is performed so that a large amount of current flows on the chip (3.0). In the test ROM (3.6), if the CPU (3.7) is judged to be non-defective, the peripheral circuit 1 (3.8)
Is operated so that current flows as much as possible. As a result, the temperature of the peripheral circuit 1 (3.8) increases.

The procedure for performing the self-test stored in the test ROM (3.6) is as shown in FIG.

When the self-test is started, first, a procedure for testing the CPU (3.7) itself is read from the test ROM (3.6), and the CPU (3.7) is tested. CPU (3.7)
If the test result of FAIL is FAIL, the operation of the chip is stopped.
If the test result of the CPU (3.7) is PASS, the process proceeds to the test of the peripheral circuit 1 (3.8), and the test of the peripheral circuit 1 (3.8) is similarly performed. If the test result of the peripheral circuit 1 (3.8) is FAIL, the operation of the chip is stopped. Test result of peripheral circuit 1 (3.8) is PASS
If so, the process proceeds to the test of the peripheral circuit 2 (3.9), and similarly, the test of the peripheral circuit 2 (3.9) is performed. If the test result of the peripheral circuit 2 (3.9) is FAIL, the operation of the chip is stopped. Peripheral circuit 2
If the test result in (3.9) is PASS, the peripheral circuit 1 (3.8) is operated so that current flows as much as possible.

When the chip cannot operate at all, the temperature state in the initial state (before starting the test) is maintained. When the chip moves halfway, the CPU is almost always
Runaway occurs during the test of (3.7), and the temperature of the CPU (3.7) rises.

The non-defective / defective discriminating device (9.0) measures the temperature state of the wafer (9.9) during the test result judgment by the temperature state reading means (9.1) and records it in the judged temperature state storage means (9.3).

The temperature difference calculating means (9.4) performs an operation between the data in the initial temperature state storing means (9.2) and the data in the judgment temperature state storing means (9.3) to calculate the temperature difference between the initial state and the judgment state. The wafer map information (9.5) is superimposed on the result by the temperature difference information / wafer map information calculation means (9.6), and it is determined which chip is a good product or a defective product. Information on which chip is non-defective or defective is stored in non-defective / defective information (9.7).

As described above, on the wafer, each chip is simultaneously tested on its own inside the chip, and the temperature of the chip is changed based on the test result. By detecting the change in temperature, non-defective / defective products can be identified, and all chip tests on the wafer can be performed in one chip test time.

In the present embodiment, since the test wiring (2.10) is provided on the scribe lane, there is no increase in the chip area and no decrease in the number of chips per wafer.

In this embodiment, as a process when the CPU (3.7) is judged to be non-defective, a process of frequently operating only the peripheral circuit 1 (3.8) is performed. By causing the "H" output to collide with the "L" output, that is, creating a state in which the VDD line and the VSS line are short-circuited inside the chip, the temperature of the short-circuited portion can be increased.

Further, in this embodiment, the CPU (3.7) reads the test procedure from the test ROM (3.6), performs a self-test, and performs a process of raising the temperature when it is determined to be a non-defective product. A dedicated self-test circuit and a temperature increasing circuit may be provided.

Further, in the present embodiment, the method of raising the temperature in the case of a non-defective product is adopted. However, the method of raising the temperature in the case of a defective product may be used.

[0030]

As described above, according to the present invention, a self-test is performed inside the chip, and the temperature of a part or the whole of the chip is changed based on the test result.
Non-defective / defective discriminating device, characterized in that it is possible to know the test result from outside of the chip as a temperature change. Thus, all the chips on the wafer can be tested in a time per one chip.

[Brief description of the drawings]

FIG. 1 is a test flowchart of the present invention.

FIG. 2 is a diagram showing wiring on a wafer according to the embodiment of the present invention;

FIG. 3 is a chip block diagram according to the embodiment of the present invention;

FIG. 4 is a conventional test flowchart.

FIG. 5 shows a semiconductor in a wafer state.

FIG. 6 is a view showing a semiconductor (4 chips in part) on a wafer.

FIG. 7 is a flowchart of a self-test stored in a test ROM.

FIG. 8 is a view showing a mask for forming a pattern on a wafer.

FIG. 9 is a diagram showing a non-defective / defective product determination device.

[Explanation of symbols]

 (2.1) VDD pin (2.2) OSC pin (2.3) RST pin (2.4) VSS pin (2.5) TST pin (2.6) Chip 1 (2.7) Chip 2 (2.8) Chip 5 (2.9) Chip 6 (2.10) Scribe lane Top test wiring (3.0) Chip (3.1) VDD pad (3.2) OSC pad (3.3) RST pad (3.4) VSS pad (3.5) TST pad (3.6) Test ROM (3.7) CPU (3.8) Peripheral circuit 1 (3.9) Peripheral circuit 2 (5.0) Wafer (5.1) Chip 1 on wafer (5.2) Chip 2 on wafer (5.3) Chip 3 on wafer (5.4) Chip 4 on wafer (5.5) Chip 5 on wafer (5.6) Chip 6 on wafer (6.1) Chip 1 (5.1) (6.2) Chip 2 (5.2) (6.3) Chip 5 (5.5) (6.4) Chip 6 (5.6) (6.1.1) One of the PADs (6.2.1) One of the PADs (6.3.1) One of the PADs (6.4.1) One of the PADs (6.5) Scribe lane (7.1) Chip 1 (5.1) (7.2) One of multiple PADs (9.0) Good / defective Equipment (9.1) Temperature state reading means (9.2) Initial temperature state storage means (9.3) Judgment temperature state storage means (9.4) Temperature difference calculation means (9.5) Wafer map information (9.6) Temperature difference information / wafer map information calculation means ( 9.7) Good / defective information (9.8) Test signal application means (9.9) Wafer

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Claims (5)

[Claims] 1. Performing its own test inside the chip,
A good or bad chip changes the temperature of a part or the whole of the chip based on the test result, and the test result is known from the outside of the chip as a temperature change before and after the test or a temperature difference between good and bad products. Semiconductors characterized by the ability to do things. 2. The method according to claim 1, wherein the temperature of the semiconductor before and after the test is detected, or the temperature difference between the non-defective / defective product is used to discriminate the non-defective / defective product. Non-defective / defective product identification device. 3. The method according to claim 1, wherein after the test within the chip itself, if it is determined as a non-defective product or a defective product based on the test result, the temperature in the chip is increased by operating a circuit in the chip. The semiconductor of claim 1. 4. After a self test inside the chip, if a good or defective product is determined based on the test result, a short circuit is created between the power supply and the ground in the chip to raise the temperature. The semiconductor according to claim 1, wherein: 5. An initial temperature state storage means for storing a temperature state of an initial state of the semiconductor chip before the test, a determination temperature state storage means for storing a temperature state during test result determination after the test of the semiconductor chip itself, 3. The apparatus according to claim 2, further comprising a temperature difference calculating means for calculating a temperature difference between the temperature state storing means and the judgment temperature state storing means, and identifying a non-defective / defective product based on a result of the temperature difference calculating means. Non-defective / defective product identification device.