JP2006261391A - Semiconductor device and its inspection method - Google Patents

Semiconductor device and its inspection method Download PDF

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JP2006261391A
JP2006261391A JP2005076838A JP2005076838A JP2006261391A JP 2006261391 A JP2006261391 A JP 2006261391A JP 2005076838 A JP2005076838 A JP 2005076838A JP 2005076838 A JP2005076838 A JP 2005076838A JP 2006261391 A JP2006261391 A JP 2006261391A
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needle
pad
probe
inspection
voltage
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Takashi Aoyama
孝 青山
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of surely detecting the deviation of the needle of a probe card and preventing measurement troubles. <P>SOLUTION: The semiconductor device is equipped with an inspection pad 2 and a deviated-needle measuring pad 3, and the inspection pad 2 is equipped with a probing area 4 where a voltage is applied from a voltage source 7 and a deviated-needle detection area 5 which detects the deviation of the probe needle. When the probe needle 6 is not deviated, the pinpoint of the probe needle 6 is kept staying in the probing area 4, so that a voltage value measured by the deviated-needle measuring pad 3 is equal to a voltage value applied from the voltage source 7. When the probe needle 6 is deviated, the pinpoint of the probe needle 6 reaches the deviated-needle detection area 5 over the probing area 4, so that a voltage value measured by the deviated-needle measuring pad 3 is equal to a voltage value applied to the probing area 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置、特に半導体集積回路およびその測定方法に関し、微細な検査用パッドを有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit and a measuring method thereof, and more particularly to a semiconductor device having a fine test pad.

半導体ウェハー上に形成されたＬＳＩの回路動作及び特性を測定するウェハー検査工程において、一般に、ウェハー搬送部と、複数のプローブ針を有するプローブカードと、を備えたプローバーと、ＬＳＩへ所望の電圧、駆動信号を与え、出力信号、電流値を測定するＬＳＩテスタ等のテスト装置が用いられる。   In a wafer inspection process for measuring the circuit operation and characteristics of an LSI formed on a semiconductor wafer, in general, a prober including a wafer transfer unit and a probe card having a plurality of probe needles, a desired voltage to the LSI, A test apparatus such as an LSI tester that applies a drive signal and measures an output signal and a current value is used.

ウェハー搬送部は、ウェハートレイにあらかじめ用意された複数枚のウェハーから測定対象のウェハーを搬送し、ステージにセットする。ステージは、あらかじめプローバーに登録された測定対象マップの情報を元にＸＹ方向に動作し、プローブカードに取り付けられている複数のプローブ針と、ウェハー上の検査用パッドを接触させる。プローブカードは、テスト装置と接続されており、プローブ針、被測定パッドを介して、テスト装置からの電源電圧、バイアス電圧、駆動信号をＬＳＩへ印加するとともに、ＬＳＩからの出力信号を測定し、ＬＳＩの特性評価ならびに検査をおこなうことが可能である。   The wafer transfer unit transfers a wafer to be measured from a plurality of wafers prepared in advance on a wafer tray and sets the wafer on a stage. The stage operates in the X and Y directions based on the information of the measurement target map registered in advance in the prober, and brings a plurality of probe needles attached to the probe card into contact with the inspection pad on the wafer. The probe card is connected to the test device, and applies the power supply voltage, bias voltage, and drive signal from the test device to the LSI via the probe needle and the pad to be measured, and measures the output signal from the LSI. It is possible to perform LSI characteristic evaluation and inspection.

しかし、ＬＳＩの特性評価や検査では、プローブカードが針ずれを起こすことにより、正しい測定結果が得られないことが問題となる。   However, in the LSI characteristic evaluation and inspection, there is a problem that a correct measurement result cannot be obtained due to needle misalignment of the probe card.

すなわち、近年の半導体プロセスの微細化により、半導体の集積度が飛躍的に向上し、それに伴い、検査用パッドのパッドピッチも微細化が進んでいる。具体的には、システムＬＳＩ等の大規模半導体集積回路では、検査用パッドの大きさが６０μｍを下回るものも存在する。従って、プローブカードのプローブ針のピッチも小さく設計されているが、半導体の集積度向上とは相反して、プローブカード針の強度、寿命が低下し、針ずれが起こる頻度が高くなった。   That is, with the recent miniaturization of semiconductor processes, the degree of integration of semiconductors has dramatically improved, and accordingly, the pad pitch of test pads has also been miniaturized. Specifically, some large-scale semiconductor integrated circuits such as system LSIs have a test pad size of less than 60 μm. Therefore, although the probe needle pitch of the probe card is designed to be small, contrary to the improvement in the degree of integration of semiconductors, the strength and life of the probe card needle are reduced, and the frequency of needle misalignment is increased.

針ずれが発生した場合、テスト装置からの駆動信号や、ＬＳＩからの出力信号が伝達されないため、正しい測定結果が得られない。特に、ＬＳＩの出荷検査の場合、検査結果からはＬＳＩの不良であるのか、プローブカードが針ずれを起こしているのか判断がつかず、測定上はＬＳＩを不良品と判定してしまうため、歩留り低下やコスト増大の原因となる。   When needle misalignment occurs, the drive signal from the test device and the output signal from the LSI are not transmitted, so that a correct measurement result cannot be obtained. In particular, in the case of LSI shipment inspection, it is not possible to determine whether the LSI is defective or whether the probe card is misaligned from the inspection result, and the LSI is determined to be defective for measurement. This causes a decrease and an increase in cost.

また、針ずれが大きくなった場合、プローブ針がＬＳＩのパッシベーション膜を破壊してしまうこともあり、最悪の場合、良品のＬＳＩを破壊し、不良品にしてしまう。   In addition, when the needle misalignment becomes large, the probe needle may break the passivation film of the LSI. In the worst case, the non-defective LSI is broken and becomes a defective product.

針ずれが起こったか否かを検出する手段としては、目視検査しかないが、近年、ＬＳＩのピン数は数百ピンのオーダーになってきており、すべてのプローブ針の針ずれを目視検査で検出するためには大変工数が必要で、加えて検出精度も悪いため、現実的でない。   Visual inspection is the only means of detecting whether or not needle misalignment has occurred, but in recent years, the number of LSI pins has been on the order of several hundred pins, and all probe needle misalignments are detected by visual inspection. In order to do this, it takes a lot of man-hours, and in addition, the detection accuracy is poor, which is not realistic.

一方、この課題を解決するために、他パッドの信号の混信の有無をもって、パッド端子と周囲金属配線との非導通状態を検出し、プローブ針ずれがないことを確認する検査方法がある（例えば特許文献１参照）。
特開平５−３４３４８７号公報 On the other hand, in order to solve this problem, there is an inspection method for detecting the non-conduction state between the pad terminal and the surrounding metal wiring based on the presence or absence of signal interference of other pads and confirming that there is no probe needle displacement (for example, Patent Document 1).
JP-A-5-343487

しかしながら、特許文献１に開示された検査方法では、信号の混信を観測したときに、ＬＳＩの不具合なのか、針ずれが発生しているのか判断できないという欠点がある。また、針ずれは、プローブカード上にある任意のプローブ針で発生するため、すべてのプローブカードの針ずれを検出することができないと効果はない。   However, the inspection method disclosed in Patent Document 1 has a drawback that when signal interference is observed, it cannot be determined whether the LSI is defective or needle misalignment has occurred. Further, since the needle misalignment occurs with an arbitrary probe needle on the probe card, there is no effect unless it is possible to detect the needle misalignment of all the probe cards.

そこで、本発明の目的は、プローブカードの針ずれを、すべてのプローブ針に対し、かつ確実に検出することで、測定不具合、ならびに、パッシベーション膜の破壊による素子破壊を防止することのできる半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing measurement failure and element destruction due to destruction of a passivation film by reliably detecting the probe card misalignment with respect to all probe needles. Is to provide.

前記課題を解決するために、本発明に係る半導体装置は、検査用パッドと針ずれ測定用パッドを有し、前記検査用パッドは電圧源から電圧が印加されるプロービングエリアとプローブ針のずれを検出する針ずれ検出エリアを有することを特徴とする。   In order to solve the above-described problems, a semiconductor device according to the present invention includes an inspection pad and a needle misalignment measurement pad, and the inspection pad detects a misalignment between a probing area to which a voltage is applied from a voltage source and a probe needle. It has a needle deviation detection area to be detected.

前記針ずれ測定用パッドは、前記検査用パッドよりも広い面積を有することが好ましい。   It is preferable that the needle misalignment measuring pad has a larger area than the inspection pad.

前記針ずれ測定用パッドと前記針ずれ検出エリアとを電気的に接続し、所定の電圧を印加する電圧源を有することが好ましい。   It is preferable to have a voltage source that electrically connects the needle misalignment measurement pad and the needle misalignment detection area and applies a predetermined voltage.

本発明の半導体装置の検査方法は、上記本発明の半導体装置に対して、前記プロービングエリアに所望の電圧を印加し、前記針ずれ測定用パッドの電圧値を測定することでプローブ針のずれの有無を検出することを特徴とする。   According to the semiconductor device inspection method of the present invention, a probe needle displacement is measured by applying a desired voltage to the probing area and measuring the voltage value of the needle displacement measurement pad with respect to the semiconductor device of the present invention. The presence or absence is detected.

本発明によると、ＬＳＩの微細化に伴い、被測定パッドのサイズが小さくなった場合にも、プローブ針の針ズレや、パッシベーション膜の破壊を起こすことなく、ＬＳＩのウェハー測定が可能である。   According to the present invention, even when the size of a pad to be measured is reduced as LSI is miniaturized, LSI wafer measurement can be performed without causing probe needle misalignment or destruction of the passivation film.

本発明の好ましい実施の形態について、以下に図面を交えて説明する。   A preferred embodiment of the present invention will be described below with reference to the drawings.

（実施の形態１）
図１は本発明の実施の形態１に係る半導体装置の検査時の構成を示す図である。 (Embodiment 1)
FIG. 1 is a diagram showing a configuration at the time of inspection of a semiconductor device according to the first embodiment of the present invention.

１はウェハー、２はウェハーを検査するための検査用パッド、３は針ずれ測定用パッドである。検査用パッド２は、外部の電圧源から電圧が印加されるプロービングエリア４と、プローブ針のずれを検出する針ずれ検出エリア５を有する。また、針ずれ測定用パッド３は、検査用パッド２よりも広い面積を有し、検査用パッド２よりも針ずれが起こりにくい構造としている。また、針ずれ測定用パッド３と針ずれ検出エリア５を電気的に接続し、所望の電圧印加が可能な電圧源７を有する。６はプローブ針である。   Reference numeral 1 denotes a wafer, 2 denotes an inspection pad for inspecting the wafer, and 3 denotes a needle misalignment measurement pad. The inspection pad 2 has a probing area 4 to which a voltage is applied from an external voltage source, and a needle deviation detection area 5 for detecting a probe needle deviation. The needle misalignment measuring pad 3 has a larger area than the inspection pad 2 and has a structure in which needle misalignment is less likely to occur than the inspection pad 2. In addition, the needle deviation measuring pad 3 and the needle deviation detection area 5 are electrically connected, and a voltage source 7 capable of applying a desired voltage is provided. 6 is a probe needle.

本実施の形態における検査方法は、次の通りである。ウェハー１上のＬＳＩの検査用パッド２とプローブ針６を接触させ、検査用パッド２へ所望の電圧を印加する。このときの電圧値は、電圧源７で印加している電圧値よりも低い値とする。次に、針ずれ測定用パッド３の電圧値を測定する。   The inspection method in the present embodiment is as follows. The LSI inspection pad 2 on the wafer 1 and the probe needle 6 are brought into contact with each other, and a desired voltage is applied to the inspection pad 2. The voltage value at this time is set to a value lower than the voltage value applied by the voltage source 7. Next, the voltage value of the pad misalignment measuring pad 3 is measured.

このとき、プローブ針６が針ずれを起こしていないときには、プローブ針６の針先が、プロービングエリア４内に納まっているため、針ずれ測定用パッド３で測定される電圧値は、電圧源７で印加している電圧値と同値となる。   At this time, when the probe needle 6 is not displaced, the probe tip of the probe needle 6 is within the probing area 4, so that the voltage value measured by the needle displacement measuring pad 3 is the voltage source 7. It becomes the same value as the voltage value applied at.

また、プローブ針６が針ずれを起こしているときには、プローブ針６の針先が、プロービングエリア４を越えて針ずれ検出エリア５へ達しているため、針ずれ測定用パッド３で測定される電圧値は、プロービングエリア４へ与えた電圧値と同値となる。   Further, when the probe needle 6 is causing needle misalignment, the needle tip of the probe needle 6 has reached the needle misalignment detection area 5 beyond the probing area 4, and therefore the voltage measured by the needle misalignment measuring pad 3. The value is the same as the voltage value given to the probing area 4.

このように、針ずれ測定用パッド３の電圧を測定するだけで、プローブ針６のずれの有無を検出することが可能となる。また、すべての被測定パッドが、プロービングエリア４と針ずれ検出エリア５を有する構造となっているため、すべてのプローブ針の針ずれを検出することが可能である。   In this way, it is possible to detect the presence or absence of the probe needle 6 by merely measuring the voltage of the needle deviation measuring pad 3. Moreover, since all the pads to be measured have a structure having the probing area 4 and the needle deviation detection area 5, it is possible to detect the needle deviation of all the probe needles.

（実施の形態２）
図２は本発明の実施の形態２に係る半導体装置の検査時の構成を示す図である。 (Embodiment 2)
FIG. 2 is a diagram showing a configuration at the time of inspection of the semiconductor device according to the second embodiment of the present invention.

１はウェハー、２はウェハーを検査するための検査用パッド、３は針ずれ測定用パッドである。検査用パッド２は、外部の電圧源から電圧が印加されるプロービングエリア４と、プローブ針のずれを検出する針ずれ検出エリア５を有する。また、針ずれ測定用パッド３は、検査用パッド２よりも広い面積を有する。また、針ずれ測定用パッド３と針ずれ検出エリア５は電気的に接続され、デバイス電源８に接続されている。６はプローブ針である。   Reference numeral 1 denotes a wafer, 2 denotes an inspection pad for inspecting the wafer, and 3 denotes a needle misalignment measurement pad. The inspection pad 2 has a probing area 4 to which a voltage is applied from an external voltage source, and a needle deviation detection area 5 for detecting a probe needle deviation. The needle misalignment measurement pad 3 has a larger area than the inspection pad 2. The needle misalignment measuring pad 3 and the needle misalignment detection area 5 are electrically connected to each other and connected to a device power supply 8. 6 is a probe needle.

実施の形態１に示したように、針ずれ検出エリア５と針ずれ測定用パッド３の導通を確認することで、プローブ針６のずれを検出できるが、プロービングエリア４に対する、針ずれ検出エリア５のはみ出し方向は、上下左右の任意の方向を取ることが可能で、また、複数方向に設けてもよい。   As shown in the first embodiment, it is possible to detect the displacement of the probe needle 6 by confirming the continuity between the needle displacement detection area 5 and the needle displacement measurement pad 3, but the needle displacement detection area 5 with respect to the probing area 4 is detected. The protruding direction can be in any direction, up, down, left and right, and may be provided in a plurality of directions.

本実施の形態では、上下左右の４方向にはみ出し部を設けた例を示している。これにより、上下左右方向のプローブ針６のずれを検出することが可能となる。プロービングエリア４に対する針ずれ検出エリア５のはみ出す方向とはみ出す辺数は、検査用パッド２に対するプローブ針６の進入方向や、チップ面積とのトレードオフにより、それぞれのケースに適した形を取ることが望ましい。   In the present embodiment, an example is shown in which protrusions are provided in four directions, up, down, left, and right. Thereby, it is possible to detect the displacement of the probe needle 6 in the vertical and horizontal directions. The protruding direction of the needle misalignment detection area 5 with respect to the probing area 4 and the number of protruding sides may take a shape suitable for each case depending on the trade-off direction of the probe needle 6 with respect to the inspection pad 2 and the chip area. desirable.

また、本実施の形態では、実施の形態１で述べたような電圧源７を用いず、ＬＳＩの中に設けられているデバイス電源８を用い、余分な回路を省くことで、ＬＳＩの面積増大を抑えている。   In this embodiment, the area of the LSI is increased by using the device power supply 8 provided in the LSI without using the voltage source 7 as described in the first embodiment and omitting an extra circuit. Is suppressed.

（実施の形態３）
図３は本発明の実施の形態３に係る半導体装置の検査時の構成を示す図である。 (Embodiment 3)
FIG. 3 is a diagram showing a configuration at the time of inspection of the semiconductor device according to the third embodiment of the present invention.

１はウェハー、２はウェハーを検査するための検査用パッド、３は針ずれ測定用パッドである。検査用パッド２は、外部の電圧源から電圧が印加されるプロービングエリア４と、プローブ針のずれを検出する針ずれ検出エリア５を有する。また、針ずれ測定用パッド３は、検査用パッド２よりも広い面積を有する。また、針ずれ測定用パッド３と針ずれ検出エリア５は電気的に接続され、電圧源７に接続されている。６はプローブ針である。   Reference numeral 1 denotes a wafer, 2 denotes an inspection pad for inspecting the wafer, and 3 denotes a needle misalignment measurement pad. The inspection pad 2 has a probing area 4 to which a voltage is applied from an external voltage source, and a needle deviation detection area 5 for detecting a probe needle deviation. The needle misalignment measurement pad 3 has a larger area than the inspection pad 2. Further, the needle misalignment measuring pad 3 and the needle misalignment detection area 5 are electrically connected to each other and connected to a voltage source 7. 6 is a probe needle.

また、一部の検査用パッド２は、針ずれ検出エリア５の外側に、第２の電圧源１１と接続された第２の針ずれ検出エリア９を有し、第２の針ずれ測定用パッド１３に接続されている。さらに、第２の針ずれ検出エリア９の外側に、第３の電圧源１２と接続された第３の針ずれ検出エリア１０を有し、第３の針ずれ測定用パッド１４に接続されている。   Further, some of the test pads 2 have a second needle deviation detection area 9 connected to the second voltage source 11 outside the needle deviation detection area 5, and the second needle deviation measurement pad. 13 is connected. Further, the third needle deviation detection area 10 connected to the third voltage source 12 is provided outside the second needle deviation detection area 9 and is connected to a third needle deviation measurement pad 14. .

本実施の形態によれば、複数の針ずれ検出エリアを設けることにより、プローブ針のずれのみでなく、ずれ量を段階的に測定することが可能となる。また、各針ずれ検出エリアに異なる電源を接続することでずれ量を検出する信号レンジを大きく取ることが可能となる。   According to the present embodiment, by providing a plurality of needle deviation detection areas, it is possible to measure not only the probe needle deviation but also the deviation amount in stages. In addition, it is possible to increase the signal range for detecting the deviation amount by connecting different power sources to each needle deviation detection area.

本発明は、針ずれ検出エリアを検査用バッドに設けることで、検査起因の不良を大幅に低減でき、狭ピッチのパッド配置のＬＳＩをウエハーレベルで検査するのに有用である。   The present invention can significantly reduce defects caused by inspection by providing a needle misalignment detection area in an inspection pad, and is useful for inspecting LSIs with a narrow pitch pad arrangement at the wafer level.

本発明の実施の形態１に係る半導体装置の検査時の構成を示す図The figure which shows the structure at the time of the test | inspection of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置の検査時の構成を示す図The figure which shows the structure at the time of the test | inspection of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の検査時の構成を示す図The figure which shows the structure at the time of the test | inspection of the semiconductor device which concerns on Embodiment 3 of this invention.

符号の説明Explanation of symbols

１ ウェハー
２ 検査用パッド
３ 針ずれ測定用パッド
４ プロービングエリア
５ 針ずれ検出エリア
６ プローブ針
７ 電圧源
８ デバイス電源
９ 第２の針ずれ検出エリア
１０ 第３の針ずれ検出エリア
１１ 第２の電圧源
１２ 第３の電圧源
１３ 第２の針ずれ測定用パッド
１４ 第３の針ずれ測定用パッド DESCRIPTION OF SYMBOLS 1 Wafer 2 Inspection pad 3 Stitch deviation measurement pad 4 Probing area 5 Stitch deviation detection area 6 Probe needle 7 Voltage source 8 Device power supply 9 Second stitch deviation detection area 10 Third stitch deviation detection area 11 Second voltage Source 12 third voltage source 13 second misalignment measuring pad 14 third misalignment measuring pad

Claims (4)

検査用パッドと針ずれ測定用パッドを有し、前記検査用パッドは電圧源から電圧が印加されるプロービングエリアとプローブ針のずれを検出する針ずれ検出エリアを有することを特徴とする半導体装置。 A semiconductor device comprising an inspection pad and a needle deviation measuring pad, wherein the inspection pad has a probing area to which a voltage is applied from a voltage source and a needle deviation detection area for detecting deviation of a probe needle. 前記針ずれ測定用パッドは、前記検査用パッドよりも広い面積を有することを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the needle misalignment measurement pad has a larger area than the inspection pad. 前記針ずれ測定用パッドと前記針ずれ検出エリアとを電気的に接続し、所定の電圧を印加する電圧源を有することを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, further comprising a voltage source that electrically connects the needle misalignment measurement pad and the needle misalignment detection area and applies a predetermined voltage. 前記プロービングエリアに所望の電圧を印加し、前記針ずれ測定用パッドの電圧値を測定することでプローブ針のずれの有無を検出することを特徴とする請求項１ないし３のいずれかに記載の半導体装置の検査方法。 4. The presence or absence of probe needle displacement is detected by applying a desired voltage to the probing area and measuring the voltage value of the needle displacement measurement pad. Inspection method of semiconductor device.
JP2005076838A 2005-03-17 2005-03-17 Semiconductor device and its inspection method Withdrawn JP2006261391A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106154095A (en) * 2015-03-31 2016-11-23 上海和辉光电有限公司 The detection method of contact LTPS and the pad structure for the method
WO2021255842A1 (en) * 2020-06-16 2021-12-23 日本電信電話株式会社 Semiconductor wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106154095A (en) * 2015-03-31 2016-11-23 上海和辉光电有限公司 The detection method of contact LTPS and the pad structure for the method
WO2021255842A1 (en) * 2020-06-16 2021-12-23 日本電信電話株式会社 Semiconductor wafer

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