JP2001136105A5 - - Google Patents

Description

[0059]
【Effect of the invention】
As described above, according to the present invention, the correlation calculation result can be obtained by adding the correction constant using the bit inverter instead of the code converter, so the circuit size can be significantly reduced and the power consumption can be reduced. it can.
In addition, when the correction constant is a power of 2, addition to the correction constant can be realized by an incrementer, and further reduction in circuit size can be expected.
In addition, in the case where it is difficult to fix the correction constant in advance, such as in the case of an application where correlation calculation processing is performed on a partial sequence of a long period spreading code sequence, the architecture of the matched filter by the bit inverter It is possible to significantly reduce the circuit size and power consumption.

Claims (10)

Inversion means for inverting a predetermined chip among the input signals, correction constant output means for outputting a correction constant according to the number of chips inverted by the inversion means, output of the inversion means and the correction constant And generating means for generating a filter output signal to which is added. Correction according to the number of delay means for storing the input signal, inverting means for inverting a predetermined delay output among delay outputs of the plurality of delay means, and the number of delay outputs to be inverted by the inverting means A correction constant output unit for outputting a constant, a filter in which the correction constant is added to the sum of the predetermined delay output inverted by the inversion unit and a delay output other than the predetermined delay output inverted by the inversion unit And a generating means for generating an output signal. Correction means for demodulating the received signal, inverting means for inverting a predetermined chip of the received signal demodulated by the demodulating means, and correction for outputting a correction constant according to the number of chips inverted by the inverting means A receiver comprising: constant output means; generation means for generating a filter output signal obtained by adding the output of the inverting means and the correction constant; and determination means for determining the filter output signal. Demodulation means for demodulating a received signal, a plurality of delay means for storing the received signal demodulated by the demodulation means, and inversion means for inverting a predetermined delay output of delay outputs of the plurality of delay means Correction constant output means for outputting a correction constant according to the number of delay outputs to be inverted by the inverting means, the predetermined delay output inverted by the inverting means, and the predetermined delay inverted by the inverting means A receiver comprising: generation means for generating a filter output signal in which the correction constant is added to the sum of delay outputs other than the output, and determination means for determining the filter output signal. A matched filter for despreading a code-spread signal, and from among a plurality of chips forming a spreading code sequence, the corresponding receive signal configuration bits for chips that perform code conversion on the receive signal Bit inversion means for inverting and outputting the received signal without inverting the corresponding received signal for chips not subjected to code conversion, sum calculation means for calculating the sum of the output of the bit inverting means, correlation A matched filter comprising correction constant addition means for adding a correction constant for generating an operation result. 6. A matched filter according to claim 5, wherein said correction constant addition means is an incrementer for realizing addition of a correction constant of power of two. A matched filter for despreading a code-spread signal, and from among a plurality of chips forming a spreading code sequence, the corresponding receive signal configuration bits for chips that perform code conversion on the receive signal Bit inversion means for inverting and outputting the received signal without inverting the corresponding received signal for a chip which does not perform code conversion on the received signal, sum calculation means for calculating the sum of the output of the bit inverting means, spreading code It comprises a counter means for counting the number of chips which perform code conversion on received signals among a plurality of chips constituting a series, and a count output addition means for adding counter outputs to generate a correlation calculation result. Characteristic matched filter. A receiving apparatus comprising: demodulation means for demodulating a reception signal; a matched filter for despreading the reception signal demodulated by the demodulation means; and determination means for determining an output signal of the matched filter
The matched filter performs code conversion on the received signal by inverting configuration bits of the corresponding received signal with respect to a chip that performs code conversion on the received signal from among a plurality of chips forming the spreading code sequence In the case of a chip that does not perform the above operation, bit inversion means for outputting the corresponding reception signal without inverting it, sum calculation means for calculating the sum of the outputs of the bit inversion means, and correction constant for generating the correlation calculation result are added. A receiver comprising: a correction constant addition means for 9. A receiver according to claim 8, wherein said correction constant addition means is an incrementer for realizing addition of a correction constant of a power of two. A receiving apparatus comprising: demodulation means for demodulating a reception signal; a matched filter for despreading the reception signal demodulated by the demodulation means; and determination means for determining an output signal of the matched filter
The matched filter performs code conversion on the received signal by inverting configuration bits of the corresponding received signal with respect to a chip that performs code conversion on the received signal from among a plurality of chips forming the spreading code sequence With respect to chips that do not perform bit conversion, bit inversion means that outputs the corresponding received signal without inverting it, sum calculation means that calculates the sum of the outputs of the bit inversion means, and reception among a plurality of chips that make up the spreading code sequence A receiving apparatus comprising: counter means for counting the number of chips that perform code conversion on a signal; and count output addition means for adding counter outputs to generate a correlation calculation result.