JP2001119433A - Video data transmitter and program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional video data transmitter that cannot have coped with a difference from a transmission delay of data transmitted through a plurality of channels because a high transmission capacity of video data requires use of a plurality of the channels. SOLUTION: The video data transmitter is provided with a coding circuit 2 that digitizes a video signal, a distribution circuit 3 that distributes data from the coding circuit 2 into a plurality of data, transmission circuits 4a, 4b that output the data from the distribution circuit 3 respectively to a public network 5, reception circuits 6a, 6b that receive the data from the public network 5, a coupling circuit 7 that couples the received data, and a decoding circuit 9 that decodes the coupled data into a video signal. The distribution circuit 3 gives a sequence number to the data and the coupling circuit 7 couples the data on the basis of the sequence numbers of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a video data transmission apparatus and a program recording medium for communicating image data in real time via a network.

[0002]

2. Description of the Related Art In recent years, computers such as personal computers and workstations have
Along with the advancement of microprocessors, the emergence of OSs equipped with network functions, the acceleration of peripheral device interfaces, and the advancement of computers, the information handled by computers has also undergone major changes. The information that was initially handled was character codes such as ASCII codes and JIS codes, but figures and the like in the CAD field have been increasingly handled, and today, the handling of multimedia information such as moving images and audio is Is important. In particular, the greatest feature of multimedia is that such information is continuously generated in real time (hereinafter, referred to as real-time property).

On the other hand, with the spread of high-speed wide area networks, these multimedia data are stored and stored.
Networks that have high data transfer rates that can be managed and transferred are also emerging.

By the way, a signal having a real-time property is
In order to transmit data using these networks, the transmitting terminal must transmit data to the receiving terminal without interruption.

As a network suitable for multimedia communication, for example, ATM (Asynchronous)
Transfer Mode (Asynchronous Transfer Mode). According to this, 155 Mbit / s data transmission is possible. Regarding ATM, ITU-T (I
international Telecommunication
ation Union-Telecommunica
Tion Standardization Sect
or: International Telecommunication Union-Telecommunication Standardization Sector) and The ATM Forum, etc., which have been discussed and standardized, and many related books have been published.

[0006] Other than ATM, 100 Mega Ethernet (100BASE-T), FDDI (Five
r Distributed Data Interf
ace) and the like, a high-speed transmission capability of 100 Mbit / s or more can be obtained, and multimedia communication can be realized. In addition, Ethernet (IEEE802.2, IE
Also in EE802.3), with the spread of switching hubs, each terminal is capable of transmitting at about 10 Meg / s, and it is possible to transmit real-time signals of less than this. Also, on the Internet, transmission of signals having real-time properties, such as video conferences and Internet telephones, is being performed.

FIG. 10 is a block diagram of a conventional data transmission apparatus. As shown in the figure, the video signal input to the encoding circuit 2 is encoded and sent to the sending circuit 100 as digital video data. The transmission circuit 100 packetizes the input digital video data to a public network such as an ATM and transmits it. On the receiving side, the receiving circuit 101 receives the digital video data and outputs it to the decoding circuit 8. The decoding circuit 8 decodes the input digital video data and outputs video data to the monitor 9.

[0008]

By the way, in the data transmission of a video signal, the transmission capacity becomes large. Therefore, even in a large-capacity network such as an ATM, desired data transmission is performed by using a plurality of lines. There is a request to do.

However, when data is transferred using a plurality of lines in a network having an asynchronous transfer mode such as an ATM, a difference in transmission delay occurs between the lines, so that a single line must be used. There was a problem that.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a data transmission apparatus and a program recording medium capable of transmitting video data using a plurality of lines in a network having an asynchronous transfer mode. The purpose is to:

[0011]

In order to achieve the above object, a first aspect of the present invention (corresponding to claim 1) is an encoding means for digitizing a video signal, and an output from the encoding means. Distribution means for distributing digital video data into a plurality of data; and a plurality of transmission means for outputting the divided digital video data output by the distribution means to a public network, respectively.
A plurality of receiving means for receiving the divided digital video data from a public network, a combining means for combining the received divided digital video data, and a decoding circuit for decoding the combined digital video data into a video signal. In the video data transmission device having, the distribution unit adds a sequence number to the distributed data, and the combining unit includes:
A video data transmission apparatus characterized in that digital video data is combined based on a sequence number of the received divided digital video data.

Further, the second invention (corresponding to claim 2)
The distributing means comprises: frame dividing means for dividing the input digital video data in a frame; sequence number generating means for generating the sequence number from a reference sync; and adding the sequence number to the divided digital video data And a plurality of sequence number adding means.

Further, the third invention (corresponding to claim 3)
A plurality of data delay means for delaying the input divided digital video data on a frame basis, a plurality of sequence number delay means for delaying an input sequence number on a frame basis, Determining means for determining data to be output based on the output of the sequence number delaying means; a plurality of selecting means for selecting data delayed by the data delaying means based on the determination of the determining means; and data selected by the selecting means And a mixing means for combining digital video data into digital video data.

A fourth aspect of the present invention (corresponding to claim 4)
The combining means includes a buffer for synchronizing the input divided digital video data with a reference sync, a plurality of data delaying means for delaying the output of the buffer in frame units, and an input sequence number. A plurality of sequence number delay means for delaying in units of frames, a determination means for determining data to be output based on the output of the sequence number delay means, and selecting data delayed by the data delay means based on the determination of the determination means The present invention is characterized in that it has a plurality of selecting means and a mixing means for combining the data selected by the selecting means into digital video data.

Further, a fifth aspect of the present invention (corresponding to claim 5)
Means that the public network is an ATM (Asynchronous Transfer Mod
e) The present invention is characterized in that the present invention is a method.

A sixth aspect of the present invention (corresponding to claim 6)
Is a program recording medium in which a program for causing a computer to execute all or a part of functions of all or a part of the video data transmission device of the present invention is recorded.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a video data transmission device according to the present embodiment. As shown in the figure, an encoding circuit 2 is a means for inputting a video signal from the camera 1, and an encoding circuit 2 is a means for digitizing the input video signal and outputting it as digital video data to a distribution circuit 3. Circuit 3
Is a means for dividing the input one-frame digital video data 12 into two blocks. Here, the transmission path of one block is channel 1 and the transmission path of the other data is channel 2. The sending circuits 4a and 4b convert input data into ATM cells and output the converted data, the receiving circuits 6a and 6b convert the received cells into digital data, and the coupling circuit 7 converts the received cells into digital data. Means for combining digital data input from 6a and 6b as digital video data based on simultaneously input sequence numbers,
It is a means for decoding the input digital video data, converting it into a video signal, and outputting it to the monitor 9. The encoding circuit 2, the distribution circuit 3, and the transmission circuits 4a and 4b operate in synchronization with the reference sync 10. The receiving circuit 6a,
6b, the combining circuit 7, and the decoding circuit 8
It operates in synchronization with 1.

The operation of the data transmission apparatus according to the first embodiment of the present invention having the above configuration will be described below.

First, the operation on the transmitting side will be described. When receiving an input of a video signal from the camera 1, the encoding circuit 2 digitizes the video signal and converts it into digital video data.
Output to The distribution circuit 3 divides one frame of the input digital video data into two data. At this time,
Channels 1 and 2 are used as transmission paths for the respective data, a sequence number is added to each of the divided data, and the data of the channel 1 is transmitted to the transmission circuit 4a.
Are output to the sending circuit 4b. When receiving the data input, the sending circuits 4a and 4b send the data to A
The data is converted into TM cells and output to the receiving circuits 6a and 6b via the public network 5.

Next, the operation on the receiving side will be described. The receiving circuit 6a restores the cell received by the channel 1 to digital data and outputs the digital data to the coupling circuit 7 together with the received sequence number. Similarly, the receiving circuit 6b also restores the received cell to digital data and outputs it to the coupling circuit 7 together with the received sequence number.

The combining circuit 7 combines the digital data input from the receiving circuits 6a and 6b based on the simultaneously input sequence number, restores the digital video data, and outputs it to the decoding circuit 8.

The decoding circuit 8 decodes the input digital video data, converts it into a video signal, and outputs it to the monitor 9.
In the above series of operations, the encoding circuit 2, the distribution circuit 3, and the transmission circuits 4a and 4b operate in synchronization with the reference sink 10. The receiving circuits 6a and 6b, the combining circuit 7, and the decoding circuit 8 operate in synchronization with the reference sync 11.

Here, a block diagram of the distribution circuit 3 is shown in FIG. 2, and the operation of the distribution circuit 3 will be described in detail with reference to the drawing.

In the distribution circuit 3, the digital video data 12 is first input to the frame division circuit 20. The frame dividing circuit 20 converts the digital video data 12
, The frame is divided into blocks of a predetermined size for each frame, and each block is output to the sequence number adding circuits 22a and 22b.

Next, the sequence number generation circuit 21 is provided with a register which receives the reference sync 10 and increments by one for each frame, and outputs the lower three bits of the numerical value to the sequence number addition circuits 21a and 21b. I do.

When receiving the data of channel 1, the sequence number adding circuit 22a adds the sequence number input from the sequence number generating circuit 21 to the data and outputs it to the sending circuit 4a. Similarly, when receiving the data of channel 2, the sequence number adding circuit 22 b adds the sequence number input from the sequence number generating circuit 21 to this and outputs it to the sending circuit 4 b. At this time, the same sequence number is added to data obtained by dividing the same frame of the digital video data 12.

FIG. 3 is a block diagram of the coupling circuit 7, and the operation of the coupling circuit 7 will be described in detail with reference to the drawing. In the figure, reference numerals 30a to 30h denote data delay circuits which delay input data by one frame and output the data. Also,
Reference numerals 32a to 30h denote sequence number delay circuits which delay the input sequence number by one frame and output the delayed sequence number.

The divided digital video data of channel 1 is first input to the data delay circuit 30a in the combining circuit 7, and the output thereof is sequentially output to the data delay circuit 30a.
b, 30c, and 30d, and output to the output selection circuits 31a of the data delay circuits 30a to 30d.

Similarly, the divided digital video data of channel 2 is input to a data delay circuit 30e, the output of which is sequentially delayed by data delay circuits 30f, 30g, and 30h. It is output to the output selection circuit 31b.

On the other hand, the received sequence number of channel 1 is inputted to a sequence number delay circuit 32a, and its output is sequentially outputted to sequence number delay circuits 32b, 32c, 3c.
Delayed by 2d. The sequence number delay circuit 32
Outputs of a to 32d are output to the judgment circuit 33.

Similarly, the sequence number of channel 2 received is input to a sequence number delay circuit 32e, and its output is sequentially output to sequence number delay circuits 32f, 32g, 3g.
Delayed for 2h. The sequence number delay circuit 32
Outputs of e to 32h are also output to the judgment circuit 33.

The determination circuit 33 determines from the input sequence numbers selection sequence numbers 35a and 35b for selecting data to be mixed by the mixing circuit 34,
Output to the selection circuits 31a and 31b, respectively.

Next, the determination algorithm of the selection sequence numbers 35a and 35b in the determination circuit 33 will be described.

The judgment circuit 33 compares the output of the input sequence number delay circuits 32a to 32h. Here, Table 1 shows a determination algorithm representing the correspondence between the output from the sequence number delay circuit and the selected sequence number.

[0035]

[Table 1] Hereinafter, an operation of determining the selection sequence number 35a and the selection sequence number 35b according to the determination algorithm shown in Table 1 will be described. However, in the table, for example, (30a) indicates a sequence number stored in the sequence number delay circuit 30a.

First, the comparison in step 1 is performed. If (30d) and (30h) match, the selected sequence number 35a and the selected sequence number 35b listed in the right column, that is, 0 and 0 are output. If step 1 does not match, a comparison of step 2 is performed. If (30d) and (30g) match, 0 is output as the selected sequence number 35a and 1 is output as the selected sequence number 35b.

Thereafter, a match is made or the comparison up to step 16 is performed. If the result of the comparison between (30a) and (30e) in step 16 does not match, the selection sequence numbers 35a and 35b
Outputs 0.

The selection circuit 31a selects data according to Table 2 and outputs the data to the mixing circuit 34.

[0039]

[Table 2] Here, the output data 30a means that the data delay circuit 30a
Is output to the mixing circuit 34.

Similarly, the selection circuit 31b selects data according to Table 3 and outputs the data to the mixing circuit 34.

[0041]

[Table 3] Next, FIG. 4 is an example of a timing chart of data input to the coupling circuit and sequence numbers. From the top, input data of channel 1, input sequence number of channel 1, output of data delay circuit 30a, sequence number delay circuit 3
2a, output of data delay circuit 30b, output of sequence number delay circuit 32b, output of data delay circuit 30c, output of sequence number delay circuit 32c, output of data delay circuit 30d, output of sequence number delay circuit 32d, channel 2, input sequence number of channel 2, output of data delay circuit 30e, output of sequence number delay circuit 32e, output of data delay circuit 30f, output of sequence number delay circuit 32f, output of data delay circuit 30g, sequence Output of number delay circuit 32g, output of data delay circuit 30h, output of sequence number delay circuit 32h, selected sequence numbers 35a, 35
b, output data of selection circuit 31a, and selection circuit 31b
Output data.

When digital video data is sequentially input to channels 1 and 2 and data having the same sequence number is input to both channels without duplication or omission at this time, selection sequence numbers 35a and 35
5b are both 0, and the outputs of the data delay circuit 30d and the data delay circuit 30h are connected to the selection circuit 31a and the selection circuit 3 respectively.
1b.

FIG. 5 is a diagram showing the timing when one frame of input data of channel 1 is lost. The cause of the loss of input data may be an error in the communication path or synchronization due to the difference between the reference sync on the sending side and the reference sync on the receiving side.

As shown in the figure, the sequence number of the input data changes from 3 to 5 in channel 1 from frame 3 to frame 4, and the data of sequence number 4 is missing.
On the other hand, in channel 2, the data is correctly input in order.

Up to frame 7, the selection sequence numbers 35a and 35b are both 0 as in the timing of FIG. 4, but from frame 8 onward, the selection sequence number 35b is 1 and the output of the selection circuit is 31a, 31b. Both 31b are sequence number 5 data.

FIG. 6 shows the timing when the input data of channel 1 overlaps by one frame. As a cause of the overlap of the input data, synchronization due to the difference between the reference syncs on the sending side and the receiving side can be considered. .

As shown in the figure, the sequence number of the input data in channel 1 from frame 3 to frame 4 remains the same and overlaps. On the other hand, the data of channel 2 is correctly input in order.

Up to frame 7, the selection sequence numbers 35a and 35b are both 0 as in the timing of FIG. 4, but after frame 8, the selection sequence number 35a becomes 1 and the output of the selection circuit is 31a, Both 31b are data of sequence number 4.

As described above, according to the data transmission apparatus of the present embodiment, even when data of one channel is lost or duplicated in frame units, the data output to the mixing circuit 34 is the same as that of the same frame. Output, and video data can be transmitted correctly. (Embodiment 2) An embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram of the video data transmission device according to the present embodiment. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. The sending circuits 40a and 40a
b is means for converting input data into ATM cells and outputting the data, receiving circuits 41a and 41b are means for restoring received cells to digital data, and combining circuit 42 is for receiving signals from receiving circuits 41a and 41b. This is means for combining input digital data as digital video data based on simultaneously input sequence numbers. However, unlike the first embodiment, the sending circuits 40a and 40a
0b, the receiving circuits 41a and 41b do not operate in synchronization with the reference sinks 10 and 11.

The operation of the data transmission apparatus having the above configuration according to the second embodiment of the present invention will be described below. However, the operation overlapping with the first embodiment will be described briefly.

First, the operation on the transmitting side will be described. The processing of signals from the camera 1 to the distribution circuit 3 is the same as in the first embodiment. Next, a sequence number is added to each block divided by the distribution circuit 3 and the data of channel 1 is sent to the transmission circuit 40a. The data of channel 2 is output to the transmission circuit 40b. Sending circuits 40a and 4
In 0b, the input data is converted into ATM cells,
The signals are output to the receiving circuits 6a and 6b via the public network 5.

Next, the operation on the receiving side will be described. Receiving circuit 4
At 1a, the cell received on channel 1 is restored to digital data and output to the combining circuit 42 together with the received sequence number. Similarly, the receiving circuit 41b restores the received cell to digital data and outputs the digital data to the coupling circuit 7 together with the received sequence number.

In the coupling circuit 7, the receiving circuits 41a and 41a
The digital data input from 1b is combined as digital video data based on the simultaneously input sequence number and output to the decoding circuit 8. The decoding circuit 8 decodes the input digital video data, converts it into a video signal, and outputs it.

FIG. 8 is a block diagram of the coupling circuit 42. As shown in the figure, the data buffer 50a is a channel 1 data buffer, and is a means for writing the divided digital video data in accordance with the output timing of the receiving circuit 60a. . The data is read from the data buffer 50 a in accordance with the timing of the reference sync 11.

Similarly, data buffer 50b is connected to channel 2
And a means for writing the divided digital video data in accordance with the output timing of the receiving circuit 60b. The data is read from the data buffer 50b in accordance with the timing of the reference sync 11.

The sequence number delay circuits 32i and 32j each delay the input sequence number by one frame in order to compensate for the delay in the data buffer.

The judgment and selection circuit 31a of the judgment circuit 33
The selection in steps 31b and 31b is performed in the same manner as in the first embodiment.

FIG. 10 is a diagram showing an example of a timing chart of data input to the coupling circuit and sequence numbers. As shown in the figure, the input data of channel 1 is synchronized with the reference sync in the data buffer 50a.
Thereafter, the timing is the same as in the first embodiment. The input sequence number of channel 1 is synchronized by the sequence number delay circuit 30i in the same manner as the data buffer 50a.

As described above, according to the present embodiment, transmission is performed using a reception circuit or a transmission circuit that is not synchronized with the reference sync. As a result, even if a transmission delay difference occurs between both channels, , Normal transmission can be performed.

In each of the embodiments of the present invention, a camera is used as a video signal source. However, a similar effect can be obtained with other signal sources such as a VTR and a tuner.

In each of the embodiments of the present invention, the description has been made assuming that the signal is divided into two channels.
The present invention is not limited to this, and the channel may be divided into three or more channels.

In each of the embodiments of the present invention, a description has been given of a case where a signal is transmitted over an ATM network as a public network. However, the present invention is not limited to this. If so, another standard may be used.

Further, in the embodiment of the present invention, the description has been made centering on the video data transmitting apparatus of the present invention. However, as a recording medium of the present invention, all or a part of the functions of each means described above, or A recording medium that stores a program that causes a computer to execute all or a part of each step may be used.

Further, the encoding means of the present invention is applied to the encoding circuit 2 of the embodiment, the distribution means of the invention is applied to the distribution circuit 3 of the embodiment, and the plurality of transmission means of the invention are transmitted to the embodiment. The circuits 4a, 4b or 40a, 40b include a plurality of receiving means of the present invention in the receiving circuit 6a, 6b or 41a, 41b of the embodiment, the coupling means of the present invention includes the coupling circuit 7 of the embodiment, and The decoding means of the invention corresponds to the decoding circuit 8 of the embodiment.

Further, the frame dividing means of the present invention corresponds to the frame dividing circuit 20 of the embodiment, and the sequence number generating means of the present invention corresponds to the sequence number generating circuit 21 of the embodiment. Are the sequence number adding circuits 22a and 22b of the embodiment, the plurality of data delay means of the present invention are the data delay circuits 30a to 30h of the embodiment, and the plurality of sequence number delay means of the present invention are the Sequence number delay circuit 32
a to 32j, the judging means of the present invention corresponds to the judging circuit 33 of the embodiment, the plural selecting means of the present invention corresponds to the selecting circuits 31a and 31b of the embodiment, and the mixing means of the present invention corresponds to the mixing of the embodiment. The circuit and the buffer of the present invention correspond to the data buffers 50a and 50b of the embodiment, respectively.

[0066]

As described above, according to the present invention, transmission of video data can be performed in real time without transmission delay even if a plurality of lines are used, and a low-cost and large-capacity transmission device can be obtained. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram of a division circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a coupling circuit according to the first embodiment of the present invention;

FIG. 4 is a timing chart in a normal state according to the first embodiment of the present invention;

FIG. 5 is a timing chart when data is lost according to the first embodiment of the present invention;

FIG. 6 is a timing chart at the time of data duplication according to the first embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 8 is a block diagram of a coupling circuit according to a second embodiment of the present invention.

FIG. 9 is a timing chart according to the second embodiment of the present invention;

FIG. 10 is a block diagram of a video data transmission device according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Camera 2 Encoding circuit 3 Distribution circuit 4a Sending circuit 4b Sending circuit 5 Public network 6a Receiving circuit 6b Receiving circuit 7 Coupling circuit 8 Decoding circuit 9 Monitor

Continued on the front page F term (reference) 5C059 KK34 RA06 RC02 RC22 RE01 SS06 SS14 SS20 UA05 UA34 UA39 5K030 GA03 HA10 HB02 HC06 KA03 KA19 LB11 LE14 MB13 9A001 BB06 CC02 EE04 FF01 HH23 KK56

Claims (6)

[Claims] An encoding unit that digitizes a video signal; a distribution unit that distributes the digital video data output by the encoding unit to a plurality of data; and a division unit that divides the digital video data output by the distribution unit. A plurality of transmitting means for respectively outputting to the public network; a plurality of receiving means for receiving the divided digital video data from the public network; a coupling means for coupling the received divided digital video data; A video data transmission device having a decoding circuit for decoding video data into a video signal, wherein the distribution unit adds a sequence number to the distributed data; A video data transmission device for combining digital video data based on a sequence number. 2. The distributing unit includes: a frame dividing unit that divides the input digital video data in a frame; a sequence number generating unit that generates the sequence number from a reference sync; 2. The video data transmission apparatus according to claim 1, further comprising a plurality of sequence number adding means for adding a number. 3. A plurality of data delaying means for delaying the input divided digital video data on a frame basis, and a plurality of sequence number delaying means for delaying an input sequence number on a frame basis. Determining means for determining data to be output based on the output of the sequence number delaying means; a plurality of selecting means for selecting data delayed by the data delaying means based on the determination of the determining means; selecting by the selecting means 3. A video data transmission apparatus according to claim 1, further comprising: mixing means for combining the obtained data into digital video data. 4. The combining means comprises: a buffer for synchronizing the input divided digital video data with a reference sync; a plurality of data delaying means for delaying the output of the buffer in frame units; A plurality of sequence number delay means for delaying a sequence number in frame units; a determination means for determining data to be output based on the output of the sequence number delay means; data delayed by a data delay means based on the determination of the determination means 3. The video data transmission device according to claim 1, further comprising: a plurality of selection units that select the image data; and a mixing unit that combines the data selected by the selection unit into digital video data. 4. 5. The public network is an ATM (Asynchronous Transcript).
5. The video data transmission device according to claim 1, wherein the video data transmission device uses a sfer mode. 6. A program for causing a computer to execute all or a part of functions of all or a part of the video data transmission device according to claim 1. Program recording medium.