JP2001111968A - Frame rate converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame rate converter that employs a circuit configured with a smaller number of frame memories to convert a video signal into a signal with an optional frame rate. SOLUTION: An input bank changeover device 102 writes a received video signal to a bank A or B under the control of a write control circuit 112, then the signal is read sequentially selectively by an output bank changeover device 110 under the control of a read control circuit 114, and outputted as a video signal with a desired frame rate. The video signal is alternately written in and read from the two banks basically. However, when a write address catches up with a read address in the case of writing the signal, the write is stopped and the succeeding image signal is written in the same bank. Furthermore, when a read address is going to catch up with a write address in the case of reading the signal, the same bank is again read and the same image data are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame rate converter for converting an input video signal having a predetermined frame rate into a desired frame rate and outputting the converted signal.

[0002]

2. Description of the Related Art There are various types of specifications for video image signals and graphics signals (hereinafter simply referred to as video signals or image signals) such as personal computers (PCs). Generally, VESA (Video E
Electronics standard associations (hereinafter referred to as VESA standard signals) are widely known, but even VESA standard signals alone can have dozens of formats when combined with image size and frame frequency. Also, for example, ATSC-DTV (Advanced Television System Commit
tee Digital TeleVision) has a total of 18 signal standards.

On the other hand, in an output side device such as a display device or a storage device, or an in-station video processing device such as an editing device, an image format to be processed is generally specified in many cases. Therefore, in order to process various signals as described above by the device, it is necessary to convert the signal format into a format that can be processed by the device. For that purpose, an apparatus capable of mutually converting these various video signals is desired.

A conventional example of such a frame rate conversion apparatus will be described with reference to FIGS. Here, a frame rate conversion device that outputs a non-interlaced input video signal at a frame rate frequency different from the input in order to display a video on a fixed pixel display device such as a liquid crystal display panel or a plasma display panel will be described. I do. FIG. 9 is a conceptual diagram for explaining the operation of the frame rate conversion device. The frame rate conversion device has ports (Input Controller, Output Controller) that are independently controlled for input and output, and video data (Input Data) input from the input port at a certain rate is temporarily stored in an image memory ( Frame Stor
eMemory) and output from the output port at the requested frame rate (Output Data). That is,
The frame rate converter converts the synchronization of the video signal by independently performing the operation of writing the video signal to the image memory and the operation of reading the video signal.

The image memory used at this time is generally a VRAM (Video-RAM) constituted by a multi-port memory, but any memory capable of storing digital signals can be stored as long as the input or output access speed is sufficient. Can be used. For example, SDRAM (S
An asynchronous dynamic RAM (Synchronous Dynamic RAM) is a single-port memory that has only one input / output port.
t-In First-Out) or the like as an I / O buffer, it is possible to pseudo-operate as a dual port memory such as a VRAM.
The image memory may be configured by the AM.

FIGS. 10A to 10C are diagrams for specifically explaining the operation of the frame rate conversion apparatus shown in FIG. 9, and in each of the figures, data i0 to i8 are shown.
Indicates image data for one frame of the raster scan structure, and the horizontal axis indicates time. FIG. 10 (A)
Is an example of down-rate conversion from 5 frames to 4 frames. For every 5 input frames, 1 frame (frame i
4) is discarded and four frames are output. FIG.
(B) is an example of up-rate conversion from three frames to four frames, and four frames are output by repeating one frame (frames i2, i5, i8) extra for three input frames.

FIG. 10 (C) shows the same-size conversion, and the input frame rate and the output frame rate are the same. In this example of constant rate conversion, a case is shown where the initial phase of the output image is different even though the frame rate is the same. Here, the frame rate ratio between input and output is an integer ratio, but in general, when performing frame rate conversion, the conversion ratio often does not become an integer ratio. In many cases, the initial phase difference between input and output images is not uniquely determined.

As described above, the frame rate conversion is performed under various conditions. It is important that the frame is not switched in the middle of one screen (one frame) image in any case. . what if,
If this condition is not satisfied in the process of frame rate conversion and a picture at a different time switches from the middle of one screen, the picture will appear discontinuous, or in the moving picture, the picture will be jagged in the time direction. You will see it.

Such a state is called so-called memory overtaking, and occurs because the speed of writing an image to the image memory is different from the speed of reading an image from the image memory. There are two types of overtaking depending on whether the write address overtakes the read address or the read address overtakes the write address.
In either case, pictures of different frames are displayed on the same output screen, and this boundary is recognized as an error. FIGS. 11A and 11B show the states of input / output data and memory access when the write address overtakes the read address and when the read address overtakes the write address, respectively.

As a method of preventing such overtaking, for an interlaced image, a method of controlling a read frame using an image memory for four fields so as not to read field data for which writing has not been completed, for example, There is a method disclosed in Japanese Patent Application Laid-Open No. 10-200783, in which the necessary readout control is performed by reducing the required image memory capacity to three fields. Further, for example, Japanese Patent Application Laid-Open No. 7-203383 discloses a method of switching frames by predicting in advance a discontinuous point at which overtaking will occur, based on an input and output vertical synchronization signal.

In Japanese Patent Application Laid-Open No. 11-18082, by using three frame memories and performing writing and reading for different frames, the overtaking occurs for the frame being read. And writing and reading are performed appropriately while converting the frame rate. Specifically, when sequentially reading frames in which data has been written, when writing to the read target frame is not completed, the contents of the previous frame are read, and the read target frame is overwritten with newer data. If it is determined that the frame is read, the frame to be read is determined so that the content of the next frame is read. The determination of the writing frame is the same.

[0012]

However, most of the various methods as described above require that the target video signal is an interlaced signal and that the video signal is efficiently processed with respect to a non-interlaced signal represented by a computer graphic signal. There is a problem that it cannot be applied.
Further, these methods require a memory capable of storing video signals for three to four frames, and thus have a problem that the circuit scale is increased and the cost is increased.

In the method of predicting the overtaking and avoiding the overtaking, it is necessary to know in advance from the frame interval of writing and reading whether the conversion is the up-rate conversion or the down-rate conversion before performing the frame synchronizing operation. The input (writing) vertical synchronizing signal and the output (reading) vertical synchronizing signal deviate in time for some unexpected reason, or the vertical synchronizing frequency fluctuates (the speed of writing to or reading from memory is In this case, there is a problem that the image is disturbed during that time because it cannot be predicted.

When such prediction is performed, a mode switching is performed by the input source signal itself, and when a switching of the output refresh frequency occurs, a preparation time for prediction is required for a while after the switching. However, there is a problem that an image may not be displayed normally due to, for example, overtaking of a memory during that time. To address this issue, for example, the latest successfully written one
The video of the frame is saved, and this video is frozen or blacked out (blanking the picture) until it returns to normal operation.
In any case, an image cannot be output correctly during that time.
Furthermore, when such prediction is performed, a separate circuit for prediction is required in terms of hardware, which has been a factor of cost increase. Furthermore, since the ratio between the frame rates of the input video signal and the output video signal is considered only in a limited combination to some extent, there is a problem that a failure occurs in a ratio of an unexpected combination.

Therefore, an object of the present invention is to convert a non-interlaced video signal having a predetermined frame rate into a non-interlaced video signal having an arbitrary phase at an arbitrary frame rate ratio by a circuit having a simple configuration using a smaller number of frame memories. It is an object of the present invention to provide a frame rate conversion device for converting a frame rate into a frame rate.

[0016]

In order to solve the above-mentioned problems, a frame rate conversion device according to the present invention comprises a first image memory means and a second image memory means each having a storage capacity capable of storing a predetermined unit of image data. Image memory means, and memory means for sequentially writing image data for each predetermined unit, which is sequentially selected from the first image memory means or the second image memory means, Image writing means for writing the image data for each of the predetermined units into the image memory means based on the synchronization signal of the input image data, and a new predetermined image data for each of the predetermined units which are sequentially output. A read memo for sequentially selecting a memory means for reading a unit of image data from the first image memory means or the second image memory means; A selecting means, the image data for each of the predetermined unit stored in the selected image memory means, and an image reading means for reading based on the desired output synchronizing signal.

In the frame rate converter having such a configuration, the input video signal is converted by the image writing means on the basis of the synchronizing signal of the input video signal, that is, based on the input phase and frame rate. hand,
The data is stored in the first image memory means or the second image memory means selected by the writing memory selection means. Further, the first image memory means or the second image memory means selected by the read memory selecting means allows the image reading means to execute the desired phase and frame rate based on the synchronization signal of the desired output video signal. The video signal is read and output based on.

Preferably, the writing memory selecting means alternately selects the first image memory means or the second image memory means, and the reading memory selecting means selects the first image memory means or the first image memory means. The second image memory means is alternately selected. More preferably, the writing memory selecting means, when writing the image data of the predetermined unit in one of the first or second image memory means in the image writing means, the writing location, When the image reading unit reaches the position where the image data is sequentially read, the writing is stopped, and the image data following the image data being written is the same as the image memory unit that is writing. Select the image memory means. Also preferably, it is assumed that the read memory selecting means selects one of the first and second image memory means and sequentially reads out image data from the selected image memory means by the image reading means. In this case, if there is a possibility that the read location may reach a location where image data is being written by the image writing means, the other image memory means is selected.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a frame rate converter according to the present invention will be described with reference to FIGS.

First, the configuration of the frame rate conversion device according to the present embodiment will be described. FIG. 1 is a block diagram illustrating a configuration of a frame converter 100 according to the present embodiment. The frame rate conversion device 100 includes an input bank switch 102, a first image memory (bank A) 10
4. It has a second image memory (bank B) 106, an output bank switch 110, a write control circuit 112, a read control circuit 114, a write overtake detection circuit 116, and an address comparator 118.

First, the configuration of each part of the frame rate conversion device 100 will be described. Input bank switch 10
2 extracts a video signal for each frame from a video signal input to the frame rate conversion device 100 based on a control signal input from the writing control circuit 112. Also, the extracted video signal for each frame is transferred to either the first image memory (bank A) 104 or the second image memory (bank B) 106 based on the bank designation signal also input from the write control circuit 112. Selectively output crabs.

The first image memory 104 and the second image memory 106 are image storage sections each configured as a so-called bank (banks A and B) in a memory unit. Each bank has a capacity capable of recording a video signal for one frame, and stores a video signal for each frame selectively input by the input bank switch 102.
Recording is performed based on a control signal input from the write control circuit 112. The recorded video signal is reproduced based on the control signal input from the read control circuit 114 and output to the output bank switch 110.

The output bank switch 110 receives a signal from one of the first image memory (bank A) 104 and the second image memory (bank B) 106 based on a bank designation signal input from the read control circuit 114. A video signal for each frame reproduced and output is selectively read. Then, based on the control signal similarly input from the read control circuit 114, a series of video signals are assembled from the read video signals for each frame and output from the frame rate conversion device 100 as output video signals.

The write control circuit 112 converts the video signal input to the frame rate converter 100 into a first image memory (bank A) 104 or a second image memory (bank B) via the input bank switch 102. 106
Controls writing to. The write control circuit 112
A control signal for extracting a signal for each frame from the input video signal is generated based on the vertical synchronization signal of the input video signal, and output to the input bank switch 102. A bank (first or second image memory 104) for recording a video signal for each frame based on a vertical synchronizing signal of an input video signal input and an overtaking detection signal input from a writing overtaking detection circuit 116 described later. , 106) are generated and output to the input bank switch 102 in the same manner.

The video signal selected by the input bank switch 102 is supplied to a first image memory (bank A) 104.
Alternatively, the first image memory (bank A) 104 may be configured to be appropriately recorded in the second image memory (bank B) 106 and may be written when the write address attempts to overtake the read address. And data recording to the second image memory (bank B) 106 is controlled. The detailed operation of the write control circuit 112 will be described later.

The read control circuit 114 controls the first image memory (bank A) 104 and the second image memory (bank B) so that a video signal of a frame rate required by the frame rate converter 100 is output. 106
And the output bank switch 110.

The read control circuit 114 selects a bank from which a video signal is to be read, based on a vertical synchronizing signal of an input output video signal and a signal of an address comparison result input from an address comparator 118 described later. Then, a bank designating signal for selecting the bank is generated and output to the output bank switch 110, and the video signal for each frame for assembling the output video signal is appropriately read from the selected bank. In this way, the reproduction of data to the first image memory (bank A) 104 and the second image memory (bank B) 106 is controlled. Further, a control signal for assembling an output video signal is generated from a signal for each frame based on a vertical synchronization signal of the input output video signal, and is output to the output bank switch 110. The detailed operation of the read control circuit 114 will be described later.

The write overtaking detection circuit 116 performs write based on information indicating the write bank and write address output from the write control circuit 112 and data indicating the read bank and read address output from the read control circuit 114. Detects a state where the address tries to overtake the read address,
A signal indicating this is output to the write control circuit 112. This signal is sent to the write control circuit 112.
It is used for the process of determining the write bank.

The address comparator 118 outputs information indicating the write bank and the write address output from the write control circuit 112 and the read control circuit 114
Based on the output data indicating the read bank, if the bank to which the video signal is being written is the same as the bank to which the video signal is being read, whether or not the write address has reached a predetermined ratio or more in the entire write space of that bank And outputs the detection result to the read control circuit 114. This signal is used by the read control circuit 114 for processing for determining a read bank. The frame rate conversion device 100 has such components.

In the frame rate conversion apparatus 100 having such a configuration, in order to perform a desired frame rate conversion, how to select a write bank and a read bank of a video signal based on their mutual relationship is required. That is important. Hereinafter, a method of selecting a write bank and a method of selecting a read bank, which are mainly performed in the write control circuit 112 and the write overtaking detection circuit 116, and in the read control circuit 114 and the address comparator 118, will be described in detail.

First, a method of selecting a write bank will be described. The video signal for each input frame is
Which of the image memory (bank A) 104 and the second image memory (bank B) 106 is to be recorded is
The determination is made based on whether or not the write address has caught up with the read address during writing of the previous frame. That is, while writing the previous frame,
If the write address cannot keep up with the read address, all video signals for that frame have been properly written to that bank, so the signal for the next frame will be in a different bank than the bank that wrote the previous frame. Write to. If the write address catches up with the read address during the writing of the previous frame, the writing is stopped at that point, and only the input video signal is received until the beginning of the next frame. Is not performed. This prevents the write address from overtaking the read address and ensures read data continuity. Then, when such a state occurs, the video signal of the next frame is written to the same bank in which the writing was performed in the previous frame.

Next, a control circuit for selecting a write bank by such a method will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of specific circuits of the write overtaking detection circuit 116 and the write control circuit 112. As shown in FIG. 2, the write overtaking detection circuit 11
6 is a comparator 201, AND elements 202 and 204
And an XNOR element 203. The write control circuit 112 includes an RS flip-flop (RS-FF)
205, an AND element 206, a selector 207, and a D flip-flop (D-FF) 208.

First, the comparator 201 of the write overtaking detection circuit 116 compares the write address with the read address, and outputs 1 only when they are equal. This output is gated by the AND element 202 based on the write-side frame synchronization signal, and applied to one input of the AND element 204. Also, the XNOR element 203 has a signal (1: second image memory (bank B) 106, 0: output of the D-FF 208 of the write control circuit 112, which indicates the write bank; ) 104) and a signal indicating the read bank is input, and the output is applied to the other input of the AND element 204. As a result, the output of the AND element 204 becomes 1 when the write bank and the read bank are equal and the write address and the read address are equal.

The output of the AND element 204 is RS-F
The signal is input to F205 as a set signal. Therefore,
When the above conditions are not met, this RS-FF20
5 is in a reset state, and its inverted output becomes 1, so that the output of the AND element 206 becomes 1, and a signal is written to the first image memory (bank A) 104 or the second image memory (bank B) 106. Is valid. Also,
Since the selector 207 selects the inverted output of the D-FF 208, the write bank is alternately selected for each write frame synchronization signal, that is, for each frame.

When the write bank and the read bank are equal and the write address and the read address are equal, the output of the AND element 204 becomes 1, and
The RS-FF 205 is set. As a result, the inverted output becomes 0, the output of the AND element 206 also becomes 0,
Writing of data to the first image memory (bank A) 104 or the second image memory (bank B) 106 is immediately invalidated. The output of the selector 207 is DF
The output of F208 is selected, and the write bank is not changed.

As described above, according to the circuit shown in FIG.
Normally, write banks are alternately selected, and signal writing to memory is also enabled.However, when the write bank and read bank are equal and the write address and read address are equal, writing to memory is invalid. And the same bank is subsequently selected as the write bank.

Next, the actual process of writing a video signal in the write control circuit 112 will be described with reference to the flowchart of FIG. First, as an initial state, the first image memory (bank A) 104 is selected as a write bank (wbank) (step ST30).
1). Then, the vertical synchronization signal of the input video signal is observed, and the head of the frame of the video signal is detected (step ST302). When the head of the frame is detected, writing of the input video signal to the previously selected bank is started. That is, the input bank switch 102 and the first image memory (bank A) 104 or the second image memory (bank B) 106 are controlled to sequentially read signals for each pixel and write them to the selected bank. The write address is sequentially incremented (step ST30).
3).

Every time a signal for one pixel is stored, it is checked whether the write bank and the read bank are equal and the write address and the read address are equal within one frame period (step ST304).
If the condition of step ST304 is satisfied, it means that the write address has caught up with the read address, and the writing is stopped until the next input frame (step ST305). Then, without changing the write bank (wbank) (step ST306),
The process moves to the next frame writing process after step ST302.

When the condition of step ST304 is not satisfied, it is detected whether or not the input and storage of the image for one frame is completed (step ST307). If not completed, the process returns to step ST303 to write the next pixel. I do. In step ST307, if the input and storage of the image for one frame has been completed, the writing bank (wbank) is changed (step ST308), and the process proceeds to the next frame writing process after step ST302.

Next, a method of selecting a read bank will be described. Which of the first image memory (bank A) 104 or the second image memory (bank B) 106 is used to read the video signal for each frame to be output depends on the read bank of the previous frame and the currently accessed bank. The determination is made based on the write bank that is present and the write address when the read bank is switched. That is, when the read bank of the previous frame is the same as the write bank being accessed at the time of the bank switching determination, the bank to be read next is different from the read bank of the previous frame.

When the read bank of the previous frame is different from the write bank being accessed at the time of the bank switching decision, the write address of the write bank currently being accessed is checked to see if this address exceeds a certain set margin. Check if not. If it has exceeded, it is considered that this writing bank has already been written, and this bank is set as the bank to be read next.
Conversely, if the write address does not exceed a certain set margin, the next time the bank is switched, the read address may overtake the write address, and the data in the same bank as the previous frame is read again. The setting margin is appropriately determined depending on the allowable range of the frame rate conversion ratio, but is set to 3/4 in the present embodiment.

Next, a control circuit for selecting a read bank by such a method will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of a specific circuit of the address comparator 118 and the read control circuit 114. As shown in FIG. 4, the address comparator 118
01, an AND element 402 and an XOR element 403. Further, the read control circuit 114 includes a selector 404
And a D flip-flop (D-FF) 405.

The comparator 40 of the address comparator 118
At 1, the write address is compared with the set margin, and if the write address is equal to or less than the set margin, 1 is applied to one input of the AND element 402.
The XNOR element 403 includes a read control circuit 11
4 which is an output of the D-FF 405 and indicates a read bank (1: a second image memory (bank B) 106,
0: a signal indicating the first image memory (bank A) 104) and the write bank are input, and the output is applied to the other input of the AND element 402. As a result, the output of the AND element 402 becomes 1 when the write bank is different from the read bank and the write address is equal to or smaller than the set margin.

The output of the AND element 204 is input to the selector 404 as a select signal. When the output is 0, that is, the write bank and the read bank are the same or the write address of the write bank and the read bank are different. Is greater than the set margin,
The inverted output of the D-FF 405 is selected. As a result, a different read bank is selected for each read frame synchronization signal. When the output of the AND element 204 is 1,
That is, when the write bank and the read bank are different and the write address is equal to or smaller than the set margin, the output of the selector 404 is the output of the D-FF 405, and the read bank is not changed.

As described above, according to the circuit shown in FIG.
Usually, the read banks are alternately selected. However, only when the write bank and the read bank are different and the write address is equal to or smaller than the set margin, the same bank is again selected as the read bank.

Next, the process of actually reading the video signal in the read control circuit 114 will be described with reference to the flowchart of FIG. First, one of the banks is set as the read bank (rbank), the vertical synchronization signal of the input output video signal is observed, and the head of the frame of the output video signal is detected (step ST50).
1). When the head of the frame is detected, reading of the video signal from the previously selected bank is started. That is, the first
Image memory (bank A) 104 or second image memory (bank B) 106 and output bank switch 11
By controlling 0, the signal for each pixel is sequentially read, and the read address is sequentially incremented (step ST502).

Each time a signal for one pixel is stored, it is detected whether or not reproduction and output of one frame of image have been completed (step ST503). If not completed, the process of step ST502 is repeated. . Step ST
If it is determined in step 503 that reproduction and output of an image for one frame have been completed, it is checked whether the writing bank (wbank) of the video signal at that time is equal to the reading bank (rbank) so far. Then, if they are equal, a bank different from the previous read bank is selected as the next read bank (step ST505).

Further, the write bank (wbank) is
If it is different from the previous read bank (rbank) (step ST504), it is checked whether the write address is larger than the set margin (step S5).
06) If it is larger, a bank different from the previous read bank is selected as the next read bank (step ST507). If the write address is equal to or smaller than the set margin, the next read bank is the same as the previous read bank (step ST5).
08). Then, step ST505, step ST5
07 and in step ST508S, the process returns to step ST501 to detect the head of the next frame, and thereafter, repeats the processing in step ST502 and thereafter.

Next, the overall operation of the frame rate conversion apparatus 100 having such a configuration will be described. A video signal input at an arbitrary timing (phase) and at an arbitrary frame rate is switched by the input bank switch 102 based on a control signal from the write control circuit 112, and the first image memory 104 (bank A) Or second
Is written to any of the image memories (banks B) 106 of FIG. The video signals written in the first image memory (bank A) 104 and the second image memory (bank B) 106 are sequentially read by an output bank switch 110 based on a control signal from a read control circuit 114. The video signal is assembled and output as a video signal of any required timing (phase) and any frame rate.

The signal writing at this time is basically performed as follows.
Control is performed so that video signals for each frame are alternately written to the two banks. However, if the data is caught up to the read location during the write, that is, if the write and the read have the same address in the same bank, the write is immediately stopped and the original read data is stored. In addition to not destroying the data that has been written, the video signal written halfway is substantially discarded, and the video signal of the next frame is written again to the same bank. Such a situation occurs in the case of down-rate conversion in which the read rate is lower than the write rate. In the case of down-rate conversion, frames are thinned out and output, but such writing catches up with reading. Frames that have been lost are eventually thinned out.

In the case of reading a signal, since a video signal for each frame must be output continuously, referring to a write address on the writing side, a bank in which the video signal to be read is already stored, or a bank in the middle of the process. A bank that is sufficiently stored so that a state where a signal has not been stored yet does not occur is selected, and the video signal of the bank is read. Specifically, when the video signal is written to the bank from which the video signal was read, the video signal has already been stored in the other bank. Is read from a different bank from the previous one.

If the writing of the video signal is performed to a bank different from the bank from which the video signal was previously read, the extent to which the signal is written by referring to the write address is described. Is checked, and if the data is sufficiently stored so as not to be read, the reading of the video signal from the different bank is started. Also, when such writing of the video signal is performed to a bank different from the bank from which the video signal was previously read, and if the amount of the written signal is not sufficient, The video signal of the bank from which the signal was read is read again. In such a case, it is a case of the Uplego conversion in which the read rate is higher than the write rate,
Although it is necessary to read out the video signal for each frame as appropriate, the previous frame in which such writing is unlikely to be ready for reading will be repeatedly read out and inserted into the video signal as a result.

Next, a more detailed description of the operation of the frame rate conversion apparatus 100 will be described with reference to FIGS. 6 to 8 in a state where the frame rate conversion is actually performed. The frame rate conversion includes down-rate conversion in which the output frame rate is lower than the input frame rate, up-rate conversion in which the output frame rate is higher than the input frame rate, and equal-size conversion in which the input frame rate and the output frame rate are the same. .

FIG. 6 shows a frame rate down conversion from three input frames to two output frames.
(A) is a diagram showing a video signal for each input frame, (B) is a diagram showing a video signal for each output frame, (C) )
FIG. 7 is a diagram showing an access state to the first image memory (bank A) 104; FIG. 9D is a diagram showing an access state to the second image memory (bank B) 106;
(E) is a result of examining the conditions for determining the read bank, and the write data amount of a bank different from the bank that has been read so far is a predetermined ratio (3/4 in the present embodiment) of the total data amount. (F) is a diagram showing a bank to which an input video signal is written, and (G) is a diagram showing a bank from which an output video signal is read.

Note that in (A) and (B), i-1
To i11 are numbers for specifying the frame. In (C) and (D), the solid line indicates the write position (address).
, The broken line indicates the read position (address), and in (E), 1 indicates that the write data amount of a bank different from the bank from which the data has been read so far is equal to or more than a predetermined ratio of the total data amount, and 0 indicates that it is not X indicates a case where the condition is not required. In (F) and (G), 0 indicates the first image memory (bank A) 104, and 1 indicates the second image memory (bank A).
The image memory (bank B) 106 of FIG.

As shown in FIG. 6, in down-rate conversion, reading does not catch up with writing.
As a result, as shown in (C), (D) and (G), reading is performed alternately with respect to bank A and bank B. Writing is normally performed on the banks B and A for the frames i0 and i1, but when the frame i2 is being written on the bank B, (C),
At the position indicated by point C in (D), reading catches up. Therefore, the write control circuit 112
Only the input of the signal after the frame i2 is accepted, and the writing is stopped. Then, as shown in (F), the next frame i3 is in the same bank B as frame i2.
Write to. As a result, when the read side is the bank A, B,
When A and B are selected in that order, the frames i-1,
After i0 and i1, the frame i3 is read, and as a result, the frame i2 is thinned out.

Similarly, when writing each of the frames i5, i8, and i11, catch-up occurs at the position indicated by the point C to the read position. As a result, the writing is stopped, the next frames i6, i9 and i12 are overwritten on the same bank, and the signals of the frames i5, i8 and i11 are thinned out. By repeating such processing, only the video signal of the frame with the mark R among the video signals input as shown in FIG.
Are output in order as shown in FIG.

FIG. 7 shows a frame rate up-rate conversion from two input frames to three output frames.
FIG. 8 is a diagram showing the operation of “→ 3 conversion”. The description of each drawing in (A) to (G) and the meaning of each code are the same as those in FIG. 6 described above. In the up-rate conversion, writing does not catch up with reading, and as a result, writing is performed alternately on banks A and B as shown in (C), (D) and (F). For reading, for example, after reading the frame i-1 from the bank A, the bank to be read next is determined based on the writing position of the video signal at that time.
In this case, writing is performed to bank B,
The write amount indicated by the write address is an amount that is well over 3/4 of the whole. Therefore,
Assuming that the reading of the video signal from the bank B has started, it is assumed that the video signal for one frame can be continuously read without interruption, and the next video signal is read from the bank B.

Thus, when the video signal of the frame i0 is read from the bank B, the read of the video signal of the next frame is similarly determined. In this case, the writing at that time is performed on the bank A different from the bank B from which the video signal has been read, and the writing amount is about half, and Not reached. In such a case, even if the reading is started from the bank A, the reading may catch up with the writing on the way, and it may be impossible to continuously output the video signal for one frame. high. Therefore, access is made to bank B from which video signals for one frame can be read continuously, and video signals for the same frame i0 as before are accessed. That is, on the reading side, the banks A, B, and B are selected, and the frames i-1, i0, i0 and the frame i0 are read in an overlapping manner, and as a result, the frame i2 is thinned out.

Similarly, first, frames i2, i4, i6
After reading each of the video signals, the write bank is different from the read bank, and the write address has not reached 3/4 of the whole. Therefore, the same bank is accessed, and its frame i2, i4, i6 is repeatedly read. By repeating such processing, as shown in (B), a signal in which the video signal of the frame with the mark D is repeatedly inserted into the input video signal is output, and the up-rate conversion is performed. Is achieved.

FIG. 8 is a diagram showing an operation of outputting a video signal at an equal frame rate with respect to an input frame rate and performing an equal rate conversion. The description of each of the drawings (A) to (G) and the meaning of each reference numeral are the same as those in the case of FIG. 6 described above. As shown in FIG. 8, in the constant rate conversion, both writing and reading do not catch up with each other, and writing and reading are alternately performed for the banks A and B. When the write bank and the read bank are determined, the same processing as in the case of the down-rate conversion and the up-rate conversion described with reference to FIGS. 6 and 7 is performed. The state to be determined does not appear, and is accessed regularly and alternately as shown. Although the frame rate is not converted, the phase can be changed to a desired difference by passing through the frame rate converter 100. In other words, an input video signal can be extracted as a video signal having a desired phase.

As described above, the frame rate conversion apparatus 100 according to the present embodiment can appropriately perform a desired frame rate conversion. The frame memory for conversion requires only two frames, so that the circuit configuration can be greatly simplified. In addition, since it is not necessary to make an overtaking prediction, the circuit configuration can be extremely simplified in that respect. As a result, a significant reduction in circuit cost can be realized as compared with the related art.

Further, it is not necessary to know in advance whether the frame rate conversion is up-rate conversion, down-rate conversion, or equal-rate conversion (no prediction is needed). A response is possible. In addition, the operation of the frame rate conversion itself,
Even if the input / output image frames have a temporal initial phase shift, the output image does not break down, and the conversion ratio between the input frame and the output frame is not limited. Can do it.

Further, by combining the frame rate conversion apparatus 100 of the present embodiment with a pixel number converter, an image format converter capable of converting to an arbitrary frame rate and an arbitrary number of pixels can be realized.

[0065]

As described above, according to the present invention, a non-interlaced video signal having a predetermined frame rate can be converted to an arbitrary frame rate ratio by a circuit having a simple configuration using a very small number of frame memories of two frames. Thus, it is possible to provide a frame rate conversion device for converting a video signal into a non-interlaced video signal having an arbitrary phase.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a frame rate conversion device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of specific circuits of a write overtaking detection circuit and a write control circuit of the frame rate conversion device illustrated in FIG. 1;

FIG. 3 is a flowchart for explaining a flow of processing in a write control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 4 is a diagram illustrating an example of specific circuits of an address comparator and a read control circuit of the frame rate conversion device illustrated in FIG. 1;

FIG. 5 is a flowchart for explaining a flow of processing in a read control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 6 is a diagram showing an operation when the frame rate conversion apparatus shown in FIG. 1 performs down-rate conversion of a frame rate from three input frames to two output frames.

FIG. 7 is a diagram showing an operation when up-rate conversion of a frame rate from two input frames to three output frames is performed in the frame rate conversion device shown in FIG. 1;

FIG. 8 is a diagram showing an operation in the case of performing equal rate conversion in the frame rate conversion apparatus shown in FIG. 1;

FIG. 9 is a conceptual diagram illustrating the operation of a conventional frame rate conversion device.

FIG. 10 is a diagram for specifically explaining the operation of the frame rate conversion device shown in FIG. 9;

FIG. 11 is a diagram showing the state of input / output data and memory access when the write address overtakes the read address and when the read address overtakes the write address in the frame rate conversion device.

[Explanation of symbols]

100: frame rate converter, 102: input bank switch, 104, 106: image memory, 110: output bank switch, 112: write control circuit, 11
4: Read control circuit, 116: Write overtaking detection circuit, 118: Address comparator, 201: Comparator, 202, 204, 206: AND element, 203: X
NOR element, 205 ... RS flip-flop (RS-F
F), 207 ... selector, 208 ... D-FF, 401 ...
Comparator, 402: AND element, 403: XOR element, 404: Selector, 405: D flip-flop (D-FF)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Seiichiro Iwase 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5B047 BC21 EA05 EB07 5C020 AA14 AA15 BA01 5C063 AA01 AC01 BA01 CA05 CA09

Claims (10)

[Claims] 1. A first image memory means and a second image memory means each having a storage capacity capable of storing image data of a predetermined unit, and a memory means for writing sequentially inputted image data of each predetermined unit. A writing memory selecting means for sequentially selecting the image data from the first image memory means or the second image memory means; and inputting the image data for each of the predetermined units to the selected image memory means. An image writing unit for writing based on a synchronization signal of the image data, and a memory unit for reading out image data of a new predetermined unit of the image data for each predetermined unit sequentially output,
Reading memory selecting means for sequentially selecting from the image memory means or the second image memory means, and converting the image data for each predetermined unit stored in the selected image memory means into a desired output synchronization signal. A frame rate conversion device comprising: an image reading means for reading based on a frame rate. 2. The method according to claim 1, wherein said write memory selecting means includes:
2. The image memory unit or the second image memory unit is alternately selected, and the read memory selection unit alternately selects the first image memory unit or the second image memory unit. Frame rate converter. 3. The writing memory selecting means, wherein when the image writing means writes the image data of the predetermined unit into one of the first and second image memory means, In the case where the image reading unit reaches a position where the image data is sequentially read out, for the image data of the predetermined unit next to the image data of the predetermined unit being written,
3. The frame rate conversion device according to claim 2, wherein the same image memory unit as the image memory unit performing the writing is selected. 4. The image writing means, when writing a predetermined unit of image data into one of the first and second image memory means,
4. The frame rate conversion apparatus according to claim 3, wherein when the image reading unit reaches a position where the image data is sequentially read, writing of the predetermined unit of image data is stopped. 5. The read memory selecting means according to claim 1, wherein:
Or selecting one of the second image memory means,
If it is assumed that the image reading means sequentially reads out the image data from the selected image memory means, and the read location may reach a location where the image writing means is writing image data, 4. The frame rate conversion device according to claim 3, wherein the other one of the first and second image memory means is selected. 6. The frame rate conversion device according to claim 5, wherein the image data for each predetermined unit is image data for each frame. 7. The read memory selecting means according to claim 1, wherein:
Or selecting one of the second image memory means,
If it is assumed that the image reading means sequentially reads out the image data from the selected image memory means, and the read location may reach a location where the image writing means is writing image data, 3. The frame rate conversion device according to claim 2, wherein the other one of the first and second image memory means is selected. 8. The read memory selecting means comprises: an address in the image memory means to which the image data is written by the image writing means; and a last address when the image data of the predetermined unit of the image memory means is written. 8. The frame rate conversion device according to claim 7, wherein the frame rate conversion device detects whether there is a possibility that a portion where the image data is sequentially read may reach a portion where the image data is written. 9. The read memory selecting means, wherein an address in the image memory means to which image data is written by the image writing means writes a predetermined ratio of the image data of the predetermined unit of the image memory means. 9. The frame rate conversion device according to claim 8, wherein when at least the address at that time has not been reached, it is determined that the portion where the image data is sequentially read may reach the portion where the image data is being written. 10. The frame rate conversion device according to claim 9, wherein said image data for each predetermined unit is image data for each frame.