JP2001044895A - Decision feedback encoder and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decision feedback encoder that can be configured with a far smaller number of high speed comparators and high speed circuits than those of a conventional encoder. SOLUTION: This decision feedback encoder includes an A/D converter 4, that converts an input signal into a digital signal denoting a discrimination level, a digital processing circuit that provides a consecutive symbol value and one set of coefficients in response to the signal from the A/D converter, a D/A converter 8 that converts the coefficient into a corresponding analog value, and an analog circuit 9 that obtains a sum of products between respective symbol values and respective analog values to produce a feedback signal, so as to reduce inter-symbol disturbance in the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the reception of encoded signals employing decision feedback equalization. In particular, but not necessarily, an Ethernet or ATM data communication system, especially a 10 MHZ
The present invention relates to receiving data in the form of data packets in a dual system operable at various frequencies such as z and 100 MHz.

The invention is particularly intended for use in Ethernet local area standards where the amplitude of an analog carrier signal having a constant frequency is modulated according to an encoded binary digital bit stream. Amplitude changes to the analog carrier signal result in three amplitude levels known as -1, 0 and +1;
These represent a negative voltage for the data level, a data level and a positive voltage for the data level, respectively. Typically, by the occurrence of two consecutive similar symbols, i.e., the same carrier amplitude occurring in one symbol period as in the previous symbol period,
A binary zero is represented, and a change from one symbol to another represents a binary one.

[0003]

BACKGROUND OF THE INVENTION Data signals, such as partial response signals, having in particular more than two possible states and thus more than one decision level, and in particular the intended level is -1, 0 And +1 Ethernet signals have variability problems when transmitted over many practical channels, exhibited by both base line wander and intersymbol interference. For example, at each port of a device of the Ethernet system, it is possible to provide a receiver, which performs equalization to compensate for variations in the incoming signal in the transmission medium coupled to the port and then performs analog-to-digital conversion later It is a practice. It will be appreciated that this relates to the “physical layer” or layer 1 of the OSI model. With the growing trend of integrating many ports into Ethernet devices, keeping the cost of these devices reasonable requires minimizing the area on the silicon chip occupied by physical layer devices for all channels. It is desirable to reduce the power consumption associated with

As is generally known in the art, a decision feedback equalizer basically operates to provide a feedback signal representing an estimate of intersymbol interference. It typically includes a multi-tap transversal filter through which the decoded data is sequentially shifted. The decoded individual symbol values obtained at the taps are multiplied by respective coefficients and their products are added to obtain an estimate of the intersymbol interference in the received signal. This estimate is algebraically combined with the received signal before the received signal is subjected to analog-to-digital conversion to shift the received signal to a decision level provided by the analog-to-digital converter.

[0005] The actual intersymbol interference is represented by the convolution of the impulse response of the transmission path with the data passing through it. In practice, it is necessary to first assume a set of coefficients from the probability density function calculated by assuming that the input signal is represented by a pseudo-random sequence. In this case, it is desirable to adapt the coefficients using some suitable algorithm, and the coefficients are adjusted to provide a measure of intersymbol interference for the particular data pattern employed.

[0006]

2. Description of the Related Art U.S. Pat. No. 5,157,690 discloses an adaptive convergence decision feedback equalizer.
gent decision feedback equalizer), where the coefficients, the product of the coefficients and the estimated intersymbol interference are calculated digitally.

US Pat. No. 5,581,585 includes:
An analog clock timing recovery circuit including a decision feedback equalizer is described. Here, the "least mean square" algorithm is briefly described, and the "least squares" and "recursive least squares" algorithms for adapting the coefficients generated by the feedback equalizer are briefly described.

US Pat. No. 5,604,741 includes:
An Ethernet receiver is described that includes a three level data slicer whose output provides a symbol to a decision feedback equalizer.

Broadly speaking, for example, the well-known 100B
There are two techniques available for receiving signals transmitted over a physical medium according to the ASE-TX standard. The first is an all analog receiver where equalization is performed in the analog domain. The second technology is an all digital receiver,
It has some required analog components, such as an analog receiver, before the gain control stage, but performs equalization in the digital domain.

[0010] Analog receivers typically include an analog low-pass filter coupled to a gain control stage, the output of which is coupled to an analog equalizer. The output of the analog equalizer is coupled to an analog phase lock loop to provide the data clock recovery necessary for both digital processing of the received signal and clock control of the analog to digital converter. The analog-to-digital converter converts the input signal into a binary, non-return-to-zero format after equalization. The output of the analog equalizer also provides a control signal to a gain control circuit that operates the aforementioned gain control stage. Broadly speaking, such receivers require fairly complex analog filters and analog equalizers. It is difficult to reduce intersymbol interference, offset and noise. These problems are exacerbated as the operating frequency increases.

At the front end of a typical "digital" receiver used in similar situations is provided a fixed analog filter, which is coupled to a gain control stage,
The output of this gain control stage is coupled to the input of a multi-level flash analog-to-digital converter. Typically 100M
For a 1 Hz system, the flash converter operates at at least 125 MHz and provides 64 levels of analog to digital conversion. The flash converter is coupled to an input of a digital equalization filter, the output of which is coupled to a digital clock recovery circuit and a digital automatic gain control circuit. The digital automatic gain control circuit drives a digital-to-analog converter that provides a gain control signal to the aforementioned gain control stage. A digital clock recovery circuit provides a control signal to a voltage controlled oscillator, which is used in further digitally processing the received signal, and which is also used to control the clock of the flash converter. Give a clock signal. The final sum of the product of the previously decoded symbol values and the respective coefficients is provided to a digital representation of the input signal. Broadly speaking, receivers on these lines are expensive in terms of occupied chip area and power consumption.

A digital equalizer of the type described above is typically a decision feedback equalizer in which the decision or slicing level is adjusted according to a weighted sum of the values of a number of previously received signals, the weights being adjusted appropriately. Adjusted according to the algorithm. Several algorithms are known for this purpose. Generally preferred is the "least mean square" algorithm first described by B. Widrow. In all digital domains, the weights or coefficients of the previous symbols and the multiplication of the weight values must all be done digitally, and the digital circuits need to operate at the symbol rate. Such practices are expensive both in terms of silicon area used and power consumption.

[0013]

SUMMARY OF THE INVENTION The present invention is a hybrid system that calculates coefficients digitally, converts these coefficients to analog form, and adjusts or equalizes the input signal in the analog domain to provide inverting feedback and the like. It is based on what is done. Broadly speaking, compared to known digital systems, the number of high-speed comparators required for the system according to the invention and the number of high-speed circuits required for the invention (i.e., digital circuits operating above the symbol rate) are small. . In addition, reduction of quantization noise is required. Furthermore, performing high-precision digital-to-analog conversion is much easier than analog-to-digital conversion.

BRIEF DESCRIPTION OF THE DRAWINGS To illustrate further various features of the invention and the various features of the invention, reference is made to the accompanying drawings.

[0015]

DETAILED DESCRIPTION Although the system described below relates to a single port of an Ethernet receiver, the present invention can be implemented as an ASIC in a multi-port device, and to implement an Ethernet hub on a single silicon chip. It is intended that a starting point can be formed.

FIG. 1 shows that, after first analog filtering, as a constant frequency carrier by three levels of amplitude modulation, a positive level (+1), a data or zero level (0) and a negative level (-1). Briefly shows the part of the receiver intended to receive the originally coded Ethernet signal. This configuration is simplified for convenience of explanation. An input combiner 1, which may in fact be a current mode operational amplifier, receives (after bandpass filtering) an input data signal, such as the three-level signal described above, on an input line 2. The combiner also has some other input lines 3. In practice, as shown, there are usually more than three other input lines 3, typically 12 components, each of which has a symbol value (-
1, 0 or +1).

The output of combiner 1 is input to an analog-to-digital converter (quantizer) 4, which defines several slicing levels, various combinations of which are used for various purposes. Can be Since there are three possible states for the symbols in this example, two of the slicing levels may be used to decode them. The decoded symbols are sent to a shift register 5, which holds at any time the value of a set of previous symbols, in particular the twelve previously decoded symbols. Clock signal for controlling a voltage controlled oscillator, not shown in FIG. 1, which determines automatic gain control, calculations required for the adaptive algorithm, monitoring of convergence and sampling time for the digital-to-analog converter Various slicing levels are employed for recovery.

FIG. 1 is limited to the process in which the previous symbol values and decision feedback equalizer coefficients are employed to adjust the decision level. The coefficients are digitally calculated (described later) and stored in the coefficient register 6. The coefficients are provided by 12 groups of registers on output line 7. As will be described in detail later, in practice the resolution of the coefficients need not be constant and may decrease as the coefficients are associated with older (previous) symbols. Typically, a 6-bit resolution would be typical for the three most recent symbols, but a 2-bit resolution would be sufficient for older symbols, and typically the 12 most recently converted In the case of a 12 tap shift register giving symbol values to the symbols, the total number of magnitude bits on the twelve outputs from the coefficient register may be 48 bits instead of 72 bits which may be required for a constant resolution. .

Each of the twelve coefficients provided by the coefficient register is converted into an analog signal, such as a current voltage, by a respective digital-to-analog converter 8 or the like. Each of these analog signals is applied to a respective multiplier 9
Must be multiplied by the symbol value. When the symbol value is represented only by the value of −1, 0 or +1 depending on the coding mode, the so-called multiplier 9
It is only necessary to limit the analog output from converter 8 by one or the other of these three values, each of which may be constituted by a relatively simple analog gate including, for example, four N-channel FETs. .

The mechanism shown in FIG. 1 is based on digitally calculating (various) coefficients, converting these coefficients into analog form, and multiplying coefficients and symbol values analogously. . The digital-to-analog converter does not need to operate at the symbol rate, but only at a variable rate at which coefficients are adapted or updated. In practice it is much lower than the symbol rate.

FIG. 2 shows a detailed embodiment of the invention in connection with FIG. In the receiver shown in FIG. 2, an input line 10 from a transmission medium (such as a twisted pair) couples an Ethernet signal to a receive filter 11. This filter and the other individual stages shown in FIG. 2 will be described more specifically later. The purpose of the filter 11 is to perform coarse equalization on the channel, shorten the length of the decision feedback equalizer (depending on the number of symbol values and coefficients to be employed), and add it when combined with the effect of the decision feedback equalizer. Performing band-pass filtering to compensate for baseline wander without the need for a special circuit. The filter also needs to set a noise band that appropriately maintains the relationship between noise suppression and desired signal distortion. For reasons explained later, the reception filter has a frequency of 0.
, Has a real axis pole at a relatively low frequency (typically 24 MHz) compared to the carrier frequency, and has a frequency substantially higher than the transmission frequency (eg, 1).
60 MHz) would be a bandpass filter with another real axis pole. These requirements can be easily satisfied by using an RC filter.

The output of the filter 11 is a gain control amplifier 12
The gain control amplifier 12 is controlled by a gain control signal in a manner described later. The amplifier 12 may be a two-stage amplifier by switching between stages for controlling the gain.

The output of the gain control amplifier 12 is the combiner 1
The combiner 1 combines the input signal with an offset signal (generated as described generally with reference to FIG. 1 and shown as a single line 13) to receive the signal prior to quantization. The signal is corrected so that the previously received signal substantially cancels the intersymbol interference superimposed on the ideal amplitude of the current signal.

In FIG. 2, the converter 8 and the multiplier 9 described with reference to FIG.

The input signal thus corrected is applied to an analog-to-digital converter 15 including a plurality of comparators 16;
Each of these plurality of comparators 16 has a reference level set by a respective node in the chain of resistors 17, and another input is coupled to the output from stage 14. In effect, this chain is a double chain of resistors providing various inputs to the comparator. The particular configuration of the transducer is not important. Sampling of the input signal is performed under the control of a voltage-controlled oscillator 18 described later. Eight levels of quantization and eight binary signals C0-C7 are provided by the digital-to-analog converter according to whether the input signal exceeds the respective level. The level of output C0 is defined as a negative data voltage, such as -1 volt, and the level of output C7 is defined as a positive data voltage, such as 1 volt. The intermediate level is set by the value of the resistors, preferably these resistors are symmetrically arranged as shown, the top and bottom resistor in the chain being 0.1R, where R is a selectable value;
The central resistor separating the levels of outputs C3 and C4 is 0.2R and the remaining resistors are 0.4R.

In addition, in practice, the entire analog signal path is preferably differential to reduce the effects of noise, and is not a "disproportionate" mechanism shown schematically for convenience of illustration.

As with the Ethernet standard, two comparator levels are sufficient to digitize a signal that should have three values. In this embodiment, these two levels are for outputs C2 and C5 and occur at 25% and 75% of the total range of the comparator between the levels associated with outputs C0 and C7, respectively. Output C
2 and C5 are sent to a decoder 19, which generates, for each symbol interval, a respective decoded symbol value that is either -1, 0 or +1 as appropriate. For example, if C2 = 1 and C5 = 0, the symbol value of the decoder is 0. These values are preferably coupled to a converter 20 which converts the three levels of the signal into an NRZ binary output on a first output line 21 according to the original coding and outputs a "symbol valid" Signal. The output rate in this embodiment is 125 MHz.

The decoded symbol values from the decoder 19 are successively sent to a shift register 5, which in this embodiment of the present invention stores the symbol value of each of the 12 most recently received symbols. It has 12 taps to give (-1, 0 or +1). The individual symbol values are multiplied by the analog of the decision feedback coded coefficients as described with reference to FIG.

The identification of the symbol value and the polarity of the residual ISI (described below) is used to control an automatic gain control circuit 23, the output of which controls a digital analog Converter 24
To a digital gain control signal.

The symbol values and the polarity of the residual ISI are coupled to an equalizer adaptation circuit 25, which calculates and updates the equalizer coefficients, if necessary, in the manner described.

The outputs C1, C3, C4 and C6 of the comparator
Controls the convergence monitor 26, which, as will be described, is provided essentially to indicate whether equalizer adaptation, automatic gain control, and clock recovery all converge in a satisfactory manner. .

The outputs C1, C3, C4 and C6 of the comparator
Is used in a clock recovery circuit 27, which is operable to recover and track the clock signal contained in the received signal. The output of the clock recovery circuit is a frequency trimming signal, which is provided to a digital to analog converter 28 to control a voltage controlled oscillator 18 that determines the sampling time for the comparator.

The operation of the clock recovery circuit, convergence monitor and equalizer adaptation circuit, automatic gain control, and the calculation of coefficients for the decision feedback encoder is governed by microprocessor 29 or other high-level control unit. For example, sets an initial value of a coefficient, sets a time constant relating to adaptation of an equalizer, checks the operation of a convergence monitor, and generally handles data transfer between circuits to be controlled. The construction and operation of the microprocessor or high-level control unit is not directly relevant to the present invention and will not be described in detail.

In the following, various important parts of the system will be described. Receive Filter The receive filter 11 is responsible for filtering the received signal before it is processed later.

If the cable is long, 100BASE-T
The frequency response of the X channel peaks significantly at low frequencies. This is because the channel has a low-pass characteristic with attenuation in dB proportional to the cable length times the square root of the frequency. This means that the channel impulse response decays fairly slowly and equalizers with only feedback filters need to be very long to reduce the residual intersymbol interference to acceptable levels. To overcome this problem, the proposed architecture preferably uses a non-adaptive analog forward feed receive filter, with coarse equalization by attenuating low frequencies to eliminate peaks in the channel frequency response. I do. This greatly reduces the length of the digital decision feedback equalizer.

Since the filter 11 is non-adaptive, it is relatively simple to implement as an RC filter having one transmission 0 at the origin and the two real poles described above. Receiver performance is less sensitive to the exact response of the filter. This is because the decision feedback equalizer adapts accordingly. Preferably, the filter is designed to be more suitable for long cables. Because they are the most difficult to equalize. For short cables, the filter can actually increase the amount of intersymbol interference, but this is not a problem. This is because a decision feedback equalizer can usually compensate.

Quantizer (ADC) Only two comparators 16 are required for slicing the MTL3 data, but if all transitions are used, two more are needed for equalization and another four for clock recovery. One is needed, for a total of eight. The bandwidth required for the comparator is about 160 MHz (1 ns time constant)
This can be done quite easily with CMOS processing of 0.5μ or less.

The comparator 16 uses the lowest possible sampling rate of 125 MHz to provide one sample for a symbol period. Clocked by a 125 MHz VCO, the frequency and phase are controlled by clock recovery.

Prior attempts at digital equalization for 100BASE-TX required an ADC with 64 quantization levels. This requires 64 comparators for the flash converter, which results in increased power consumption. In the proposed architecture, only eight comparators are needed to meet all receiver requirements. This means that the feedback signal from the decision feedback equalizer is sent back to the analog circuit via the DAC,
This is because it is used to modify the input signal before digitization. The justification of this architecture is that many of the outputs from the 64 comparators used for the 6-bit ADC are not actually needed because the equalization is done before digitization. In practice, up to eight comparators are required. This simplification is made possible by the comparator threshold being modified symbol-by-symbol from the decision feedback equalizer via the DAC. As a result, the high-speed DAC in the current mode is
Because it is much simpler than C, it can save power and silicon area, which are important concerns.

Symbol Decoder The symbol decoder shown in FIG. 2, including the decoder, converter and shift register blocks 19, 20 and 5, is responsible for decoding the current symbol and providing the relevant inputs to other blocks. It has four functions.

(I) Compute the MLT3 value (-1, 0 or +1) for the current symbol using the comparator outputs C2 and C5.

(Ii) The two most recently decoded Ms
Convert the value of MLT3 to a binary output symbol according to whether the value of LT3 is the same or different.

(Iii) Store a finite length history of previously decoded symbols in a buffer (eg, shift register 5).

(Iv) Outputs C0, C3, C4 of the comparator
And C7, ie, using the levels that are both outside and inside the range between the levels used to determine the value of MLT3, the received signal equalized (the actual signal amplitude at the sampling time and The residual intersymbol interference (IS) in the sign of the error between the ideal signal amplitude)
Determine the polarity of I).

The polarity of the residual ISI is calculated for MLT3 = + 1 by determining whether C7 is "true" and by determining whether C0 is "true".
3 = −1, and the equation [(C4) == TRU
E]-[(C3) == FALSE] using MLT3 =
Calculated for zero.

Equalizer The equalizer (described above) is responsible for compensating for signal degradation caused by cables, transformers, and other elements of the receive chain. It performs correction of the received signal based on the weighted sum of the previous N decoded symbols prior to digitization and cancels intersymbol interference superimposed on the ideal amplitude of the current symbol. To do it. It consists of a symbol history held in the shift register 5 and constituted by the MLT3 values {-1, 0, +1} for the 12 most recently decoded symbols, and each of the 12 taps of the shift register 5 1 in
Each time, the coefficient value held in the register 6 is adopted.
The number of bits m used to represent each coefficient depends on the coefficient index. The output from the equalizer, which acts to correct the input signal to the comparator, must be in the proper state before the next clock signal to the comparator, ie, before the next sampling of the input signal. .

The output from the DFE is calculated as follows.

[0048]

(Equation 1)

DfeOut is the combined output from multiplier 8, SymbolHistory [n] is the value of MLT3 obtained from the n-th tap, and DfeTaps [n] is the respective coefficient.

The value of SymbolHistory [n] is {-1, 0, +
Since 1｝, only addition is needed to calculate this equation. In fact, the equation can be implemented very effectively with analog circuits in which the addition is performed by adding the currents.

The number of bits required to store each coefficient depends on its position. If the coefficient corresponding to the more recent symbol (small value of n) has the largest dynamic range, more bits are needed. The assignment of bits to each tap (not including the sign bit) is as follows.

[0052]

(Equation 2)

The total number of bits for all taps is 48, which determines the complexity of the analog cell when calculating the DFE output.

The weight of the least significant bit for all coefficients is the same, which in this example corresponds to a feedback correction of 10 mV to the equalized ideal signal amplitude of 1000 mV (for a + 1 MLT3 level after automatic gain control). I do. That is, the resolution of each coefficient is equal to 1% of the desired signal amplitude. Therefore, the maximum residual intersymbol interference due to the quantization of the coefficients is 12 * 0.5% = 6% (the coefficients are fully adapted and are not equalized by the coefficients, from the previous or future symbols to the intersymbols). Assuming no interference).

Equalizer Adaptation Equalizer adaptation is responsible for updating the equalizer coefficients to equalize the channel with high accuracy.

The programmable parameters for controlling the operation are as follows. (I) 'DfeTapsInitial' is an initial value of a coefficient before adaptation. It is preferably stored with the same precision as DfeTaps. There may be multiple sets of default coefficients.

(Ii) 'DfeLambda' is an update rate by a power of 2. It is inversely proportional to the adaptation time constant. There may be various update rates for initial reservation and normal operation.

To allow for a relatively long time constant for the adaptation of the equalizer, the coefficients are extra 6 compared to the coefficients DfeTaps [n] sent to the DFE application block.
Stored internally as DfeTapsInternal [n] using bit precision.

[0059]

(Equation 3)

M is the equalizer block 1 for the coefficient n
The number of bits sent to 4 and used for DfeTapsInternal [n], excluding the sign bit, is shown below.

[0061]

(Equation 4)

The updating formula for adapting each of the equalizer coefficients is as follows.

[0063]

(Equation 5)

DfeLambda is limited to a power of two and
Note that since gn and SymbolHistory [n] take only the values {-1, 0, +1}, the equation can be implemented using only additions and bit shifts. DfeTapsInternal
The new value of [n] needs to be limited by the minimum and maximum allowed.

Updating all 12 coefficients every clock cycle is probably not practical. An acceptable alternative is to implement hardware that can adapt a single coefficient per clock cycle,
That is, each coefficient can be updated by a continuous clock. This increases the convergence time of the equalizer by a factor of twelve.

The updating formula is based on the well-known least mean square algorithm. The true least mean square algorithm uses the actual ISI value in the update equation, but replacing this with the ISI code facilitates implementation.

Clock Recovery The clock recovery circuit is responsible for recovering and tracking the clock contained in the received signal. It is necessary to determine whether the sampling point for the current symbol is early, late, or acceptable. A temporary offset should be added to the frequency trim applied to the VCO so that it changes in phase with the receive clock (acting as a sampling clock for the comparator). VC
The frequency of the receive clock may be changed by adding a permanent offset to the frequency trim applied to O. It may be possible to track a frequency error of up to ± 400 ppm between the nominal received clock and the transmitted clock contained in the received signal.

The specific features of the clock recovery circuit are not directly related to the present invention and will not be described in detail. It is important to operate on the equalized signal regardless of the internal operation of the clock recovery circuit. This is because the equalization is performed prior to the comparator. This can achieve a clock recovery that is much less sensitive to inter-symbol interference caused by the channel as compared to alternative mechanisms that use a PLL that operates on the received signal prior to equalization.

A narrow bandwidth loop and a wide bandwidth loop are used for clock recovery. A narrow bandwidth loop provides a long-term estimate of the ideal sampling phase. Such a loop cannot track fast changes in the phase of the clock contained in the received signal, but can suppress noise from the timing detector. A wide bandwidth loop can track fast changes in phase, but is sensitive to noise. The programmable parameters determine the bandwidth of each loop and how much the overall phase estimate can deviate from a narrow bandwidth loop.

Automatic Gain Control Automatic gain control 23 is responsible for adapting the gain applied to the input signal so that the amplitude of the equalized signal at the input to the comparator is set to a desired value. It may define a default gain value that is loaded before the first capture and stored with the same precision as the output signal, which will be sent to the digital-to-analog converter. There may be multiple initial gain values.

To enable a relatively long time constant for automatic gain control, the gain value can be stored internally with additional bit precision compared to the output signal.

The gain may be updated by subtracting the product of the update rate, the current symbol value [-1, 0 or +1] and the sign of the residual intersymbol interference from the stored gain. The process can be realized by performing only addition. The new value of the gain should be limited according to the minimum and maximum allowed.

It should be understood that the gain is low if both the symbol value and the sign of the intersymbol interference are positive. This is because these inputs indicate that the signal amplitude was too large at the sampling point. Similarly, if these inputs indicate that the signal amplitude is too small at the sampling point, the gain will increase. If the symbol value is 0, the gain does not change. Because the gain information is 0 ML
This is because it cannot be easily obtained from the T3 level.

The effect of the automatic gain control is to set the intermediate signal amplitude for the outer symbol equal to the ideal signal amplitude (determined by the threshold level of the outer comparator).

Convergence Monitor The convergence monitor 26 is responsible for indicating whether the equalizer adaptation, automatic gain control, and clock recovery have all converged in a satisfactory manner. This is used by the control software to determine whether it is necessary to try again using various initial coefficients and gain values.

For each decoded symbol, a binary decision is made as to whether the defined "signal quality" for that symbol is good or bad. This means that the intersymbol interference for that symbol is 10% (5
(ISI higher than 0% will result in bit errors). The decision depends on the current symbol value. If the symbol value is +1, the output C6 of the comparator needs to be "true" (i.e., the signal level is higher than the level associated with output C6). If the symbol value is -1, the signal level must be less than the level for output C1. If the symbol value is 0, the signal level is C3
And C4 (narrower than the band between C2 and C5). The decision is low-pass filtered and the result is tested against a threshold, where convergence has occurred if the threshold is exceeded.

High Level Control High level control includes the following.

(I) Monitor whether the adaptation of the equalizer, automatic gain control and clock recovery have converged correctly.

(Ii) If convergence does not occur within a certain time range, change the initial conditions and automatic gain control for the equalizer and restart the acquisition procedure.

(Iii) When convergence is performed, the time constant relating to the adaptive and automatic gain control of the equalizer is increased, and the sensitivity to noise is reduced.

[0081] High level control can be implemented as a state machine in either software or hardware.

FIG. 3 shows another, but at the same time not a preferred alternative to FIG. The combiner 1 drives the analog-to-digital converter 5 as described above. However, each successive output from the converter 5 is digitally multiplied by a respective digital multiplier 30 with the coefficient from the coefficient register 4. The products are added by one store 31 (for the product of the coefficients for the oldest symbols) and 11 digital adders 32, and the cumulative sum is sent from the final adder to the high-speed digital-to-analog converter 33. The converter 33 outputs the offset signal to the combiner 1. While such a system is an improvement on all digital receivers already proposed, the analog-to-digital converter 5 requires only a small number of decision levels, and the high-speed digital-to-analog converter is a 64-level analog-to-digital converter. Is more efficient than
This configuration is not preferred. This is because the area and power consumption are larger than those of the mechanism of FIG.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic concept of decision feedback equalization according to the present invention.

FIG. 2 shows a receiver according to the invention in more detail.

FIG. 3 illustrates an alternative form of decision feedback equalization.

[Explanation of symbols]

4 analog-digital converters, 8 digital-analog converters, 9 analog circuits, 15 analog-digital converters.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H04L 25/03 H04L 11/00 (72) Inventor Robert William Young UK, UK Di You Cambridgeshire, Erie, Meldon Place, 2 (72) Inventor James Digby Collier United Kingdom, SBI 61 SBS Cambridgeshire, Erie, Chettisham, Church Farm ( No address) F term (reference) 5J022 AA01 AA06 AB01 AC02 BA01 CA07 CB06 CD02 CE09 5K029 AA03 DD15 EE20 HH03 HH05 LL01 LL10 LL16 5K030 GA11 HC14 HD06 LA15 MA06 MB06 5K046 AA01 DD13 EE06 EE10 EF47

Claims (9)

[Claims] 1. A decision feedback encoder, comprising: an analog-to-digital converter for converting an input signal into a digital signal representing a decision level; and a continuous symbol value and one set in response to a signal from the converter. A digital processing circuit for providing a coefficient of; a digital-to-analog converter for converting the coefficient to a corresponding analog value; obtaining a sum of products of each of the symbol values and each of the analog values; An analog circuit for providing a feedback signal for reducing inter-symbol interference in the input signal. 2. The digital circuit includes means for storing a digital value for the coefficient, and calculates a new value for the coefficient in response to the symbol value, wherein the digital value is the digital to analog conversion. The decision feedback encoder of claim 1, wherein the decision feedback encoder is stored at a higher resolution than the coefficients transformed by the multiplier. 3. The coefficient of a product with a previous symbol value in the set is represented with a lower precision than the coefficient of a product with a subsequent symbol value in the set.
3. The decision feedback encoder according to 1. 4. The analog to digital converter is a flash converter, wherein the flash converter samples the input signal at the selected symbol rate,
An output digital signal indicative of more than two decision levels is provided, wherein two of the levels define a decision level for decoding the input signal into a symbol value, the store and calculate. The means for
4. The decision feedback encoder according to claim 1, responsive to an output signal indicating more than two of the decision levels. 5. A digital circuit for providing a digital gain control signal for the input signal in response to an output from the flash converter and the symbol value, and a digital-to-analog converter for the digital gain control signal. The decision feedback encoder according to claim 1, further comprising: 6. The means for summing the products includes analog gates, each of the analog gates being arranged to send one of the values of the analog coefficients modified by the respective symbol value. 6. The method of claim 1, wherein said means further comprises an analog adder, said analog adder having a number of inputs each coupled to one of said gates and an input to said input signal. The determination feedback encoder according to any of the above. 7. A receiver for an input signal in the form of a carrier signal, said carrier signal being amplitude modulated according to successive symbols, said successive symbols occurring at a defined rate and having three values. An input signal having three levels of amplitude when uninterrupted, the receiver comprises: an analog input filter for attenuating frequency components far below the specified rate; A gain control amplifier; means for adjusting the level of the input signal according to an analog signal representing an estimate of the intersymbol interference; and a quantizer including a number of comparators, each of the number of comparators comprising: Digital output for providing a continuous symbol value in response to two of the outputs of the comparators; Digital means for establishing and adapting a set of coefficients in response to a selected output of the comparator; and each of the coefficients and each of the consecutive symbol values. Means for forming the analog signal as the sum of the products of 8. The means for forming an analog signal includes a digital-to-analog converter for each of the coefficients and an analog circuit, each of the analog circuits being configured to convert the analog signal into an analog form by a respective symbol value. The receiver of claim 7, wherein the receiver is arranged to modify each of the coefficients. 9. The means for forming an analog signal comprises a digital multiplier and an adder for obtaining the sum, and a digital-to-analog converter for converting the sum to the analog signal. Receiver.